KR20040008611A - Method for fabricating capacitor using metal electrode - Google Patents
Method for fabricating capacitor using metal electrode Download PDFInfo
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- KR20040008611A KR20040008611A KR1020020042276A KR20020042276A KR20040008611A KR 20040008611 A KR20040008611 A KR 20040008611A KR 1020020042276 A KR1020020042276 A KR 1020020042276A KR 20020042276 A KR20020042276 A KR 20020042276A KR 20040008611 A KR20040008611 A KR 20040008611A
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- film
- amorphous silicon
- forming
- hsg
- capacitor
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- 239000003990 capacitor Substances 0.000 title claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 25
- 239000002184 metal Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 24
- 238000003860 storage Methods 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000003795 desorption Methods 0.000 abstract description 2
- 230000000452 restraining effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 91
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 208000012868 Overgrowth Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000011856 silicon-based particle Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 캐패시터의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a capacitor.
DRAM을 비롯한 반도체소자에서 집적도가 높아짐에 따라 캐패시턴스를 높이기 위하여 한정적인 2차원 면적에 대한 3차원으로의 구조 변화 또는 다결정폴리실리콘 박막의 미세 구조 특성을 이용한 HSG(Hemi Spherical Grain)로 전극 표면적을 증가시키는 방법, 고유전상수를 갖는 고유전물질로 대체하는 방법 등이 이용되고 있다.Increasing density in semiconductor devices including DRAM increases electrode surface area with HSG (Hemi Spherical Grain) using structural change in three dimensions or limited microstructure of polycrystalline polysilicon thin film to increase capacitance in order to increase capacitance Or a method of replacing with a high dielectric material having a high dielectric constant.
도 1은 종래기술에 따른 캐패시터의 제조 방법을 도시한 공정 단면도이다.1 is a process cross-sectional view showing a method of manufacturing a capacitor according to the prior art.
트랜지스터 및 비트라인(도시 생략)이 형성된 반도체기판(11)상에 층간절연막(12)을 관통하여 반도체기판(11)에 이르는 스토리지노드콘택홀에 스토리지노드콘택(13)이 매립되며, 층간절연막(12)상에 캐패시터의 높이를 결정짓는 캐패시터산화막(14)이 형성된다.The storage node contact 13 is buried in the storage node contact hole that penetrates the interlayer insulating film 12 and reaches the semiconductor substrate 11 on the semiconductor substrate 11 on which the transistor and the bit line (not shown) are formed. A capacitor oxide film 14 is formed on 12 to determine the height of the capacitor.
그리고, 캐패시터산화막(14)을 식각하여 스토리지노드콘택(13)을 오픈시킨 개구내에 HSG(15a)를 구비한 하부전극(15)이 형성되고, 하부전극(15)을 포함한 캐패시터산화막(14)상에 유전막(16)과 상부전극(17)이 차례로 적층된다.Then, the lower electrode 15 having the HSG 15a is formed in the opening in which the capacitor oxide film 14 is etched to open the storage node contact 13, and the capacitor oxide film 14 including the lower electrode 15 is formed. The dielectric film 16 and the upper electrode 17 are sequentially stacked on the top.
도 1의 캐패시터는 3차원 구조중의 하나인 콘케이브(concave) 또는 컵(cup) 구조의 캐패시터라 일컫는다.The capacitor of FIG. 1 is referred to as a capacitor of a concave or cup structure, which is one of three-dimensional structures.
전술한 도 1에서, HSG(15a)를 갖는 하부전극(15)의 형성은, 먼저 500℃∼600℃와 10-7∼10-8torr의 압력으로 진공 어닐 챔버에서 SiH4또는 Si2H6가스를 이용하여 비정질실리콘막을 증착한다. 이때, 분해된 실리콘이 핵생성 사이트(nucleation site)로 작용하고, 이후 열처리를 통해 실리콘 입자들이 핵생성사이트로 이동해서 오목하고 볼록한 굴곡면의 HSG(15a)를 형성시킨다. 다음에, 고온 열처리가 가능한 저압화학기상증착(LPCVD) 챔버에서 포스핀(PH3) 가스를 흘려 챔버의 분위기를 포스핀(PH3) 가스 상태로 만든다. 따라서, 포스핀 가스를 이용하여 도핑되지 않은 비정질실리콘막에 인(Phosphorous; P)을 도핑시키므로써 전도성을 부여하여 하부전극을 형성한다.1, the formation of the lower electrode 15 having the HSG 15a is first performed by SiH 4 or Si 2 H 6 in a vacuum annealing chamber at a pressure of 500 ° C. to 600 ° C. and a pressure of 10 −7 to 10 −8 torr. The amorphous silicon film is deposited using a gas. At this time, the decomposed silicon acts as a nucleation site, and the silicon particles then move to the nucleation site through heat treatment to form a concave and convex curved HSG 15a. Next, a phosphine (PH 3 ) gas is flowed into a low pressure chemical vapor deposition (LPCVD) chamber capable of high temperature heat treatment to make the atmosphere of the chamber into a phosphine (PH 3 ) gas state. Therefore, the lower electrode is formed by imparting conductivity by doping Phosphorous (P) to the undoped amorphous silicon film using a phosphine gas.
그리고, 유전막(16)으로는 질화막, Ta2O5, BST 등의 고유전막을 이용하고, 이 고유전막을 증착한 후에 막특성 개선을 위해 후속 열처리 과정을 수행한다.As the dielectric film 16, a high dielectric film such as a nitride film, Ta 2 O 5 , BST, or the like is used, and after the high dielectric film is deposited, a subsequent heat treatment process is performed to improve the film properties.
그리고, 상부전극(17)으로는 도핑된 폴리실리콘막, CVD TiN/스퍼터 TiN의 적층막, CVD TiN/W의 적층막, CVD TiN/도핑된 폴리실리콘막의 적층막을 이용한다.As the upper electrode 17, a doped polysilicon film, a CVD TiN / sputter TiN laminated film, a CVD TiN / W laminated film, and a CVD TiN / doped polysilicon film are used.
상술한 종래기술은 3차원구조인 콘케이브 구조이면서 하부전극(15)의 표면에 HSG(15a)을 형성하고, 아울러 유전막(16)으로 고유전막을 이용함에 따라 셀캐패시턴스를 증대시키고자 하였다.In the above-described conventional technology, the HSG 15a is formed on the surface of the lower electrode 15 while the concave structure has a three-dimensional structure, and the cell capacitance is increased by using the high dielectric film as the dielectric film 16.
그러나, 종래기술은 하부전극으로 이용되는 HSG(15a)가 형성된 비정질실리콘막내 인(P)의 도핑농도가 낮은 경우 하부전극에 공핍층이 발생하여 축전용량을 떨어뜨리고 하부전극의 면저항또한 높아 메모리소자의 특성을 열화시키는 문제가 있다.However, in the related art, when the doping concentration of phosphorus (P) in the amorphous silicon film having the HSG 15a used as the lower electrode is low, a depletion layer is generated in the lower electrode, thereby reducing the capacitance and the sheet resistance of the lower electrode. There is a problem of deteriorating the characteristics.
또한 비정질실리콘막이 얇은 경우 HSG(15a) 형성과정에서 발생되는 과도성장(over growth)에 의해 후속 유전막과 상부전극 형성시 보이드가 발생되거나, HSG(15a)가 후속 전세정(precleaning) 공정에서 이탈하여 오염을 발생시키는 문제가 있다.In addition, when the amorphous silicon film is thin, voids are generated during the formation of the subsequent dielectric film and the upper electrode due to overgrowth generated during the formation of the HSG 15a, or the HSG 15a is separated from the subsequent precleaning process. There is a problem that causes contamination.
이를 개선하기 위해 하부전극으로서 금속막을 적용하는 MIM(Metal Insulator Metal) 캐패시터가 제안되었으나, 금속막은 콘케이브, 실린더(Cylinder)와 같은 3차원 구조의 형성이 어렵고, 특히 금속막 표면에 HSG를 형성하는 것이 어려워 셀캐패시턴스 증대 효과를 얻을 수 없다.In order to improve this problem, a metal insulator metal (MIM) capacitor has been proposed to apply a metal film as a lower electrode. It is difficult to obtain the effect of increasing the capacitance.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, HSG를 갖는 하부전극형성시 하부전극내 인의 도핑 농도 저하로 인한 공핍층 발생을 억제하면서 HSG의 이탈을 방지하는데 적합한 캐패시터의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, a method of manufacturing a capacitor suitable for preventing the desorption of HSG while suppressing the depletion layer caused by the lower doping concentration of phosphorus in the lower electrode when forming the lower electrode having HSG The purpose is to provide.
또한, 본 발명의 다른 목적은 셀캐패시턴스를 증대시키는데 적합한 MIM 캐패시터의 제조 방법을 제공하는데 있다.In addition, another object of the present invention is to provide a method for manufacturing a MIM capacitor suitable for increasing cell capacitance.
도 1은 종래기술에 따른 캐패시터를 도시한 도면,1 is a view showing a capacitor according to the prior art,
도 2a 내지 도 2d는 본 발명의 실시예에 따른 캐패시터의 제조 방법을 도시한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 층간절연막21 semiconductor substrate 22 interlayer insulating film
23 : 스토리지노드콘택 24 : 식각배리어막23: storage node contact 24: etching barrier film
25 : 캐패시터산화막 26 : 콘케이브 패턴25: capacitor oxide film 26: concave pattern
27 : 비정질실리콘막 27a : HSG27 amorphous silicon film 27a: HSG
28, 28a : 인도핑 비정질실리콘막 29, 29a : 금속막28, 28a: guided amorphous silicon film 29, 29a: metal film
31 : 유전막 32 : 상부전극31 dielectric film 32 upper electrode
상기의 목적을 달성하기 위한 본 발명의 캐패시터의 제조 방법은 반도체기판 상부에 층간절연막을 형성하는 단계, 상기 층간절연막을 관통하여 상기 반도체기판에 연결되는 스토리지노드콘택을 형성하는 단계, 상기 층간절연막을 식각하여 상기스토리지노드콘택을 오픈시키는 콘케이브패턴을 형성하는 단계, 상기 콘케이브패턴을 포함한 전면에 비정질실리콘막을 형성하는 단계, 상기 비정질실리콘막 표면에 HSG를 형성하는 단계, 상기 HSG가 형성된 비정질실리콘막상에 금속막을 형성하는 단계, 상기 콘케이브패턴내에 상기 HSG가 형성된 비정질실리콘막과 상기 금속막의 이중층으로 이루어진 하부전극을 잔류시키는 단계, 및 상기 하부전극상에 유전막과 상부전극을 차례로 형성하는 단계를 포함함을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor, the method comprising: forming an interlayer insulating layer on an upper surface of a semiconductor substrate, forming a storage node contact connected to the semiconductor substrate through the interlayer insulating layer, and forming the interlayer insulating layer; Forming a concave pattern to open the storage node contact by etching, forming an amorphous silicon film on the entire surface including the concave pattern, forming an HSG on the surface of the amorphous silicon film, and forming the amorphous silicon film on which the HSG is formed Forming a metal film on the film, leaving a lower electrode composed of a double layer of the amorphous silicon film and the metal film in which the HSG is formed in the concave pattern, and sequentially forming a dielectric film and an upper electrode on the lower electrode. It is characterized by including.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2d는 본 발명의 실시예에 따른 캐패시터의 제조 방법을 도시한 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 트랜지스터 및 비트라인이 형성된 반도체기판(21)상에 층간절연막(22)을 형성한 후, 층간절연막(22)을 식각하여 반도체기판(21)에 이르는 스토리지노드콘택홀(도시 생략)을 형성한다.As shown in FIG. 2A, after forming the interlayer dielectric layer 22 on the semiconductor substrate 21 on which the transistor and the bit line are formed, the interlayer dielectric layer 22 is etched to form the storage node contact hole reaching the semiconductor substrate 21. (Not shown) is formed.
다음에, 스토리지노드콘택홀에 매립되는 스토리지노드콘택(23)을 형성한다. 이때, 스토리지노드콘택(23)은 잘 알려진 바와 같이, 폴리실리콘플러그 (Polysilicon plug), 티타늄실리사이드막(Ti-silicide), 티타늄나이트라이드막 (TiN)의 적층구조일 수 있으며, 티타늄나이트라이드막은 하부전극과 폴리실리콘플러그간 상호확산을 억제하는 확산배리어막이다.Next, a storage node contact 23 embedded in the storage node contact hole is formed. In this case, as is well known, the storage node contact 23 may be a laminated structure of a polysilicon plug, a titanium silicide layer, a titanium nitride layer, and a titanium nitride layer. A diffusion barrier film that suppresses mutual diffusion between an electrode and a polysilicon plug.
다음에, 스토리지노드콘택(23)이 매립된 층간절연막(22)상에 스토리지노드콘택의 산화 방지 및 후속 식각과정의 식각정지막 역할을 수행하는 식각배리어막(24)을 형성한 후, 식각배리어막(24)상에 캐패시터의 높이를 결정짓는 캐패시터산화막(25)을 형성한다. 이때, 식각배리어막(24)은 캐패시터산화막(25)에 대해 식각선택비를 갖는 질화막을 주로 이용하며, 캐패시터산화막(25)은 USG, BSG, BPSG, PSG, LPTEOS 또는 PETEOS 중에서 선택된다.Next, an etching barrier layer 24 is formed on the interlayer insulating layer 22 having the storage node contacts 23 embedded therein to serve as an etch stop layer for preventing oxidation of the storage node contacts and subsequent etching processes. A capacitor oxide film 25 is formed on the film 24 to determine the height of the capacitor. In this case, the etching barrier film 24 mainly uses a nitride film having an etching selectivity with respect to the capacitor oxide film 25, and the capacitor oxide film 25 is selected from USG, BSG, BPSG, PSG, LPTEOS or PETEOS.
다음에, 식각배리어막(24)에서 식각이 멈추도록 캐패시터산화막(25)을 식각하고 연속해서 스토리지노드콘택(23)이 오픈되도록 식각배리어막(24)을 식각하여 캐패시터가 형성될 영역을 오픈시킨다. 이때, 캐패시터가 형성될 영역을 통상적으로 콘케이브 패턴(26)이라고 한다.Next, the capacitor oxide film 25 is etched in the etching barrier film 24 to stop the etching, and the etching barrier film 24 is etched so that the storage node contact 23 is continuously opened to open the region where the capacitor is to be formed. . In this case, the region where the capacitor is to be formed is commonly referred to as a concave pattern 26.
다음에, 500℃∼600℃의 온도와 10-7torr∼10-8torr의 압력으로 진공 어닐 챔버에서 SiH4또는 Si2H6가스를 열분해시켜 콘케이브패턴(26)을 포함한 전면에 비정질실리콘막(27)을 증착한다. 다음으로, 후속 열처리 과정을 실시하여 비정질실리콘막(27) 표면에 HSG(27a)를 형성시킨다.Next, SiH 4 or Si 2 H 6 gas is thermally decomposed in a vacuum annealing chamber at a temperature of 500 ° C. to 600 ° C. and a pressure of 10 −7 torr to 10 −8 torr to form amorphous silicon on the entire surface including the concave pattern 26. A film 27 is deposited. Next, a subsequent heat treatment is performed to form HSG 27a on the surface of the amorphous silicon film 27.
다음으로, HSG(27a)가 형성된 비정질실리콘막(27)에 고농도(1×1018∼1×1022atoms/cm2)의 인(P)을 도핑시켜 전도성을 부여한다. 이하, 고농도의 인이 도핑된 HSG(27a)가 형성된 비정질실리콘막(27)을 인도핑 비정질실리콘막(28)이라 약칭한다.Next, the amorphous silicon film 27 on which the HSG 27a is formed is doped with phosphorus (P) of high concentration (1 × 10 18 to 1 × 10 22 atoms / cm 2 ) to impart conductivity. Hereinafter, the amorphous silicon film 27 on which the HSG 27a doped with a high concentration of phosphorus is formed is referred to as a guided amorphous silicon film 28.
도 2b에 도시된 바와 같이, 인도핑 비정질실리콘막(28)상에 금속막(29)을 증착한다.As shown in FIG. 2B, a metal film 29 is deposited on the guided amorphous silicon film 28.
이때, 금속막(29)은 MIM 캐패시터의 하부전극으로서 단차피복성(step coverage)이 우수한 화학기상증착법(CVD) 또는 원자층증착법 (Atomic Layer Deposition; ALD)을 통해 증착된 티타늄나이트라이드막(TiN), 텅스텐막(W) 또는 루테늄막(Ru) 중에서 선택된다. 예컨대, CVD TiN, CVD W, CVD Ru, ALD TiN, ALD W 또는 ALD Ru 중에서 선택되며, 그 두께는 10Å∼3000Å이다.In this case, the metal layer 29 is a lower electrode of the MIM capacitor, and a titanium nitride layer (TiN) deposited through chemical vapor deposition (CVD) or atomic layer deposition (ALD), which has excellent step coverage. ), Tungsten film W or ruthenium film Ru. For example, it is selected from CVD TiN, CVD W, CVD Ru, ALD TiN, ALD W, or ALD Ru, and the thickness is 10 micrometers-3000 micrometers.
이와 같이, 인도핑 비정질실리콘막(28)상에 금속막(29)을 증착하면, 비록 HSG(27a)의 과도성장이 발생되더라도 단차피복성이 좋은 금속막(29)을 증착하므로써 과도성장에 따른 보이드 발생 요인을 제거하고, 인도핑 비정질실리콘막(28)의 공핍층 발생을 줄여 축전용량 저하를 억제한다. 아울러, 금속막(29)을 하부전극으로 이용하므로써 면저항을 감소시킨다.As described above, when the metal film 29 is deposited on the guided amorphous silicon film 28, even if excessive growth of the HSG 27a occurs, the metal film 29 having high step coverage can be deposited by the deposition. The void generation factor is eliminated and the depletion layer generation of the guided amorphous silicon film 28 is reduced to suppress the reduction of the capacitance. In addition, the sheet resistance is reduced by using the metal film 29 as the lower electrode.
결국, 하부전극은 HSG가 형성된 인도핑 비정질실리콘막(28)과 금속막(29)의 이중층 구조를 갖는다.As a result, the lower electrode has a double layer structure of the guided amorphous silicon film 28 and the metal film 29 having the HSG formed thereon.
도 2c에 도시된 바와 같이, 산화막 또는 감광막(30)을 전면에 도포한 후, 에치백 또는 화학적기계적연마(Chemical Mechanical Polishing; CMP)를 통해 콘케이브패턴(26)내에만 이웃한 하부전극과 서로 절연되는 하부전극을 형성한다. 이때, 하부전극은 인도핑 비정질실리콘막(28a)과 금속막(29a)의 적층구조로 이루어진 금속전극의 형태이며, 인도핑 비정질실리콘막(28a)이 HSG를 갖고 금속막(29a)이 HSG의 굴곡면을 따라 증착되므로 하부전극은 표면적이 증대된다.As shown in FIG. 2C, after the oxide film or the photosensitive film 30 is applied to the front surface, the lower electrode adjacent to each other only in the concave pattern 26 through etch back or chemical mechanical polishing (CMP) A lower electrode to be insulated is formed. At this time, the lower electrode is in the form of a metal electrode formed of a laminated structure of the guiding amorphous silicon film 28a and the metal film 29a, the guiding amorphous silicon film 28a has an HSG and the metal film 29a is formed of an HSG. Since the surface is deposited along the curved surface, the surface area of the lower electrode is increased.
도 2d에 도시된 바와 같이, 산화막 또는 감광막(30)을 제거한 후, 하부전극을 포함한 전면에 유전막(31)을 증착한 후, 유전막(31)상에 상부전극(32)용 도전막을 증착한다. 후속 과정으로 상부전극(32)용 도전막과 유전막(31)을 식각하여 셀영역에만 잔류시킨다.As shown in FIG. 2D, after the oxide film or the photosensitive film 30 is removed, the dielectric film 31 is deposited on the entire surface including the lower electrode, and then the conductive film for the upper electrode 32 is deposited on the dielectric film 31. In the subsequent process, the conductive film for the upper electrode 32 and the dielectric film 31 are etched to remain only in the cell region.
여기서, 유전막(31)으로는 Ta2O5, BST 등의 고유전막을 이용하고, 이 고유전막을 증착한 후에 막특성 개선을 위해 후속 열처리 과정을 수행한다. 그리고, 상부전극(32)으로는 CVD TiN/스퍼터 TiN의 적층막, CVD TiN/W의 적층막, CVD Ru, CVD TiN/도핑된 폴리실리콘막의 적층막을 이용한다.Here, a high dielectric film such as Ta 2 O 5 or BST is used as the dielectric film 31, and after the high dielectric film is deposited, a subsequent heat treatment process is performed to improve the film properties. As the upper electrode 32, a laminated film of CVD TiN / sputter TiN, a laminated film of CVD TiN / W, a laminated film of CVD Ru, and CVD TiN / doped polysilicon film is used.
전술한 실시예에 의하면, 본 발명은 하부전극과 상부전극으로서 금속막을 이용하여 MIM 캐패시터를 구현하고, 하부전극 형성시 미리 비정질실리콘막을 이용하여 콘케이브 구조를 형성하므로써 3차원 구조의 MIM 캐패시터를 구현하며, HSG 형성후 금속막을 증착하므로써 후속 과정에서 HSG가 이탈하는 것을 방지한다.According to the embodiments described above, the present invention implements a MIM capacitor using a metal film as a lower electrode and an upper electrode, and implements a three-dimensional MIM capacitor by forming a concave structure using an amorphous silicon film in advance when forming the lower electrode. In addition, by depositing a metal film after the formation of the HSG to prevent the escape of the HSG in the subsequent process.
전술한 실시예에서는 콘케이브 구조의 MIM 캐패시터에 대해 설명하였으나, 캐패시터산화막을 제거한 후 유전막과 상부전극을 형성하는 실린더 구조의 MIM 캐패시터에도 적용 가능하다.In the above-described embodiment, the MIM capacitor of the concave structure has been described, but it is also applicable to the MIM capacitor of the cylinder structure in which the dielectric film and the upper electrode are formed after the capacitor oxide film is removed.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 HSG가 형성된 비정질실리콘막상에 금속막을 형성하므로써 하부전극의 공핍층을 줄여 축전용량을 증대시킴과 동시에 하부전극의 면저항을 낮추어 소자 특성을 개선시킬 수 있는 효과가 있다.According to the present invention, the metal film is formed on the amorphous silicon film on which the HSG is formed, thereby reducing the depletion layer of the lower electrode to increase the capacitance and at the same time lowering the sheet resistance of the lower electrode to improve device characteristics.
또한, HSG 형성 공정에서 발생될 수 있는 파티클 및 보이드 발생을 억제할 수 있는 효과가 있다.In addition, there is an effect that can suppress the generation of particles and voids that can be generated in the HSG forming process.
또한, MIM 캐패시터의 하부전극의 표면적을 증대시켜 셀캐패시턴스를 증가시킬 수 있는 효과가 있다.In addition, there is an effect that can increase the cell capacitance by increasing the surface area of the lower electrode of the MIM capacitor.
Claims (5)
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