KR20040006505A - CMP Device and Method of Forming Semiconductor Device Using the Same - Google Patents
CMP Device and Method of Forming Semiconductor Device Using the Same Download PDFInfo
- Publication number
- KR20040006505A KR20040006505A KR1020020040798A KR20020040798A KR20040006505A KR 20040006505 A KR20040006505 A KR 20040006505A KR 1020020040798 A KR1020020040798 A KR 1020020040798A KR 20020040798 A KR20020040798 A KR 20020040798A KR 20040006505 A KR20040006505 A KR 20040006505A
- Authority
- KR
- South Korea
- Prior art keywords
- slurry
- semiconductor device
- oxide film
- wafer
- manufacturing
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000005498 polishing Methods 0.000 claims abstract description 27
- 239000012528 membrane Substances 0.000 claims abstract description 22
- 239000011261 inert gas Substances 0.000 claims abstract description 5
- 239000002002 slurry Substances 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 239000007789 gas Substances 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 2
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 2
- 229910017604 nitric acid Inorganic materials 0.000 claims description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- 229910052786 argon Inorganic materials 0.000 claims 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 claims 1
- 238000007517 polishing process Methods 0.000 abstract description 11
- 235000012431 wafers Nutrition 0.000 description 28
- 239000000758 substrate Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910021485 fumed silica Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/27—Work carriers
- B24B37/30—Work carriers for single side lapping of plane surfaces
- B24B37/32—Retaining rings
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
- B24B37/044—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor characterised by the composition of the lapping agent
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09G—POLISHING COMPOSITIONS; SKI WAXES
- C09G1/00—Polishing compositions
- C09G1/02—Polishing compositions containing abrasives or grinding agents
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Organic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Abstract
Description
본 발명은 화학적 기계적 연마 (chemical mechanical polishing; 이하 "CMP"라 칭함) 장치 및 이를 이용한 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 리테이너 (retainer) 링과 플랙시블 맴브레인 (flexible membrane) 사이에 에어 갭 라인 (air-gap)을 구비한 CMP 장치를 이용하여 웨이퍼 (wafer) 에지 부분에 기압을 가함으로써, 플레이튼 (platen) 패드의 변형을 방지하고, 균일한 평탄도를 가지는 웨이퍼를 형성할 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chemical mechanical polishing (hereinafter referred to as "CMP") apparatus and a method for manufacturing a semiconductor device using the same, and more particularly, between a retainer ring and a flexible membrane. By applying air pressure to the wafer edge portion using a CMP apparatus having an air gap line, it is possible to prevent deformation of the platen pad and to form a wafer with uniform flatness. It relates to a method for manufacturing a semiconductor device that can be.
일반적으로 집적회로는 기판, 특히 실리콘 웨이퍼 상에 일련의 층들이 회로 미세 구조물을 형성하기 위하여 연속적으로 증착 및 식각 되는데, 이때, 기판의 외부 또는 최상부 표면인 기판의 노출 표면은 불균일하게 형성되어, 후속 공정인 포토리소그래피 (photolithography) 단계에서 문제를 발생시킬 수 있으므로, 상기 기판 표면에 대해서는 주기적으로 평탄화 공정을 수행해야 하는 단점이 있다.In general, integrated circuits are deposited and etched continuously on a substrate, in particular a silicon wafer, to form a circuit microstructure, wherein the exposed surface of the substrate, which is the outer or top surface of the substrate, is formed unevenly, so that subsequent Since a problem may occur in a photolithography step, a process of performing a planarization process on the surface of the substrate periodically.
상기 평탄화 방법 가운데 가장 많이 사용되는 것이 하나 이상의 화학 반응 약품을 포함하는 연마용 슬러리와 웨이퍼 표면과 접촉하여 연마하는 연마 패드를 구비한 장치를 이용하는 CMP 공정이다.The most commonly used planarization method is a CMP process using an apparatus having a polishing slurry containing at least one chemical reaction agent and a polishing pad in contact with and polishing the wafer surface.
상기 CMP 장치에는 웨이퍼가 연마 도중에 이동되는 것을 방지하기 위하여 연마 해드 최외곽에 리테이너 링을 더 구비할 수 있다.The CMP apparatus may further include a retainer ring at the outermost edge of the polishing head to prevent the wafer from being moved during polishing.
또한, 상기 연마 공정을 효과적으로 수행하기 위해선 웨이퍼의 연마할 면의 균일도, 평탄도, 압력 및 높은 연마 속도를 고려하여 웨이퍼를 가공해야 한다.In addition, in order to effectively perform the polishing process, the wafer should be processed in consideration of the uniformity, flatness, pressure, and high polishing rate of the surface to be polished.
상기와 같은 CMP 장치를 이용하는 연마 공정을 도 1을 들어 자세히 설명한다.The polishing process using the CMP apparatus as described above will be described in detail with reference to FIG. 1.
우선, 전체적인 연마 해드 내에는 최외곽에 설치된 리테이너 링 (5)을 구비하고, 연마할 웨이퍼를 로딩 (loading) 하는 부분에는 플랙시블 멤브레인 (12)을구비하였다.First, the overall polishing head was provided with a retainer ring 5 provided at the outermost side, and a flexible membrane 12 was provided at the portion loading the wafer to be polished.
그리고, 상기 플랙시블 멤브레인 하부에 웨이퍼를 장착하고, 상기 웨이퍼의 연마 할 면쪽에는 연마 패드로 사용되는 플레이튼 패드를 구비하였다.Then, a wafer was mounted under the flexible membrane, and a platen pad used as a polishing pad was provided on the side of the wafer to be polished.
이때, 상기와 같이 구조의 CMP 장치로 연마 공정을 수행하는 경우 연마 해드 내의 최외곽에 설치된 리테이너 링 (5)에 의한 웨이퍼 안쪽으로 가해지는 압력 (6)과 플랙시블 멤브레인 (12)에 의한 웨이퍼 바깥쪽으로 가해지는 압력 (9)의 영향으로 웨이퍼 (3)와 플레이튼 패드 (1)가 접촉 할 때, 상기 압력의 작용 위치 차이로 인하여 웨이퍼 에지 부근에서 플레이튼 패드 (1)의 변형이 발생되었다.At this time, when the polishing process is performed by the CMP apparatus having the structure as described above, the pressure 6 applied to the inside of the wafer by the retainer ring 5 installed at the outermost side in the polishing head and the outside of the wafer by the flexible membrane 12 When the wafer 3 and the platen pad 1 contacted under the influence of the pressure 9 applied to the side, deformation of the platen pad 1 occurred near the wafer edge due to the difference in the working position of the pressure.
상기 문제점으로 플레이튼 패드 (1)와 웨이퍼 (3)가 닿는 부분 즉, 웨이퍼의 a 부분, b 부분 및 c 부분이 동일하지 않기 때문에, 웨이퍼의 주변 부분, 즉 웨이퍼 에지 쪽의 연마량이 떨어져서, 연마 후 두께가 불균일하게 된다.Because of the above problem, the portions where the platen pad 1 and the wafer 3 come into contact with each other, i.e., the a, b and c portions of the wafer are not the same, so that the polishing amount on the peripheral portion of the wafer, i. The thickness is then uneven.
이는 도 2에 도시한 바와 같이, 상기 웨이퍼의 a, b 및 c 부분의 연마 후 두께는 플레이트 패드가 가장 많은 변형을 일으키는 a 및 b 부분이 각각 5000Å 및 5280Å의 두께를 가지고, 웨이퍼와 플레이튼 패드가 가장 많이 닿는 b 부분이 4650Å두께를 가지며, 그 외의 웨이퍼의 중앙 부분은 평군 4850Å의 두께를 가지기 때문에 웨이퍼 표면에는 심한 단차가 발생되었다.As shown in FIG. 2, the thickness after polishing a, b and c portions of the wafer is 5000 mm and 5280 mm in the a and b portions where plate pads cause the most deformation, respectively. The most b-contacting part has a thickness of 4650 mm 3, and the center portion of the other wafers has a thickness of 4850 mm 3 in the common group, which causes a significant step on the wafer surface.
이러한 단차는 후속 공정에 영향 주어 잔막 형상이 균일하게 형성될 수 없으므로, 집적회로에 이용되는 것이 부적당하고, 반도체 소자의 신뢰성 및 수율을 감소시킨다.Such a step affects subsequent processes so that the residual film shape cannot be formed uniformly, so it is unsuitable for use in integrated circuits, and reduces the reliability and yield of semiconductor devices.
이에 본 발명에서는 상기와 같이 리테이너 링과 플랙시블 멤브레인의 압력으로 플레이튼 패드가 변형되는 문제점을 해결하는 CMP 장치를 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a CMP apparatus that solves the problem that the platen pad is deformed by the pressure of the retainer ring and the flexible membrane as described above.
또한, 본 발명에서는 상기 CMP 장치를 이용하여 균일한 반도체 소자를 제조할 수 있는 방법을 제공하는 것을 목적으로 한다.Moreover, an object of this invention is to provide the method which can manufacture a uniform semiconductor element using the said CMP apparatus.
도 1은 종래 CMP 장치를 이용한 연마 공정도.1 is a polishing process diagram using a conventional CMP apparatus.
도 2는 종래 CMP 장치를 이용한 연마 공정으로 얻어진 웨이퍼의 두께 그래프.2 is a graph of a thickness of a wafer obtained by a polishing process using a conventional CMP apparatus.
도 3은 본 발명의 CMP 장치를 이용한 연마 공정도.3 is a polishing process diagram using the CMP apparatus of the present invention.
< 도면의 주요 부분에 대한 간단한 설명 ><Brief description of the main parts of the drawing>
1, 11 : 플레이튼 패드2, 12 : 플랙시블 멤브레인1, 11: platen pad 2, 12: flexible membrane
3, 13 : 웨이퍼5, 15 : 리테이너 링3, 13 wafer 5, 15 retainer ring
6, 16 : 리테이너 링 압력9, 19 : 멤브레인 압력6, 16: retainer ring pressure 9, 19: membrane pressure
17 : 에어 갭 라인21 : 에어 플로우17: air gap line 21: air flow
14 : 배기구14: exhaust port
상기 목적을 달성하기 위하여 본 발명에서는 리테이너 링과 플랙시블 맴브레인 사이에 에어 갭 라인을 구비한 CMP 장치를 제공한다.In order to achieve the above object, the present invention provides a CMP apparatus having an air gap line between the retainer ring and the flexible membrane.
이하 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail.
본 발명에서는 전체적인 연마 해드 내의 최외곽에 장착된 리테이너 링, 연마할 웨이퍼를 로딩하는 부분에 해드 형식으로 장착된 플랙시블 멤브레인 (12), 상기 멤브레인에 고정 설치된 웨이퍼 및 웨이퍼 하부에 위치한 플레이튼 패드를 포함하는 CMP 장치에 있어서,In the present invention, a retainer ring mounted at the outermost part of the overall polishing head, a flexible membrane 12 mounted in a head shape at a portion for loading a wafer to be polished, a wafer fixed to the membrane, and a platen pad positioned below the wafer In the containing CMP apparatus,
상기 플랙시블 멤브레인과 리테이너 링 사이에 기체가 통과할 수 있는 에어 갭 라인을 구비한 CMP 장치를 제공한다.It provides a CMP apparatus having an air gap line through which gas can pass between the flexible membrane and the retainer ring.
상기 에어 갭 라인을 통과하는 기체는 N2또는 Ar 등의 불활성 기체를 사용하는 것이 바람직하다.As the gas passing through the air gap line, an inert gas such as N 2 or Ar is preferably used.
상기 에어 갭 라인 내 기체 분사량은 100∼200 sccm 이고, 기체 분사 압력은 1∼10 psi 인데 이때, 상기 분사량 및 압력을 멤브레인 및 리테이너 링 압력과 조화되도록 조절하는 것이 바람직하다.The gas injection amount in the air gap line is 100-200 sccm, and the gas injection pressure is 1-10 psi. It is preferable to adjust the injection amount and pressure to match the membrane and retainer ring pressure.
그리고, 상기와 같은 CMP 장치로 연마 공정을 수행할 때, 연마 압력은 1∼10 psi, 연마 테이블 속도는 10∼100 rpm에서 수행되는 것이 바람직하다.When the polishing process is performed with the CMP apparatus as described above, the polishing pressure is preferably 1 to 10 psi, and the polishing table speed is performed at 10 to 100 rpm.
또한, 상기 본 발명의 CMP 장치는 분사된 기체의 원활한 순환을 위하여 리테이너 링 부분에 배기구를 더 구비하는 것이 바람직하다.In addition, the CMP apparatus of the present invention is preferably further provided with an exhaust port in the retainer ring portion for smooth circulation of the injected gas.
상기와 같은 본 발명의 CMP 장치를 이용한 연마 공정은 도 3을 들어 자세히 설명한다.The polishing process using the CMP apparatus of the present invention as described above will be described in detail with reference to FIG. 3.
상기 리테이너 링 (15) 및 플랙시블 멤브레인 (19)으로 이루어진 연마 해드와 상기 연마 해드의 로딩 부분에 장착된 웨이퍼 (13) 및 상기 웨이퍼 (13)의 연마 할 면쪽에는 연마 패드로 사용되는 플레이튼 패드 (11)를 장치한다.The polishing head consisting of the retainer ring 15 and the flexible membrane 19, the wafer 13 mounted on the loading portion of the polishing head, and a platen used as a polishing pad on the side to be polished of the wafer 13 The pad 11 is mounted.
그리고, 상기 리테이너 링 (15)과 플랙시블 멤브레인 (19) 사이에 에어 갭 라인 (17)을 플레이튼 패드 (11) 방향으로 설치한다.Then, the air gap line 17 is installed in the direction of the platen pad 11 between the retainer ring 15 and the flexible membrane 19.
그 후, 리테이너 링 압력 (16) 및 플랙시블 멤브레인 압력 (19)에 의해 플레이튼 패드가 변형되는 위치에 상기 라인 (17)을 통하여 기체를 분사 (air flow) (21)한다. 이때, 상기 분사된 기체는 리테이너 링의 확장 (extension) 부분인 배기구 (14)를 통하여 원활하게 순환될 수 있다.Thereafter, air is blown 21 through the line 17 at a position where the platen pad is deformed by the retainer ring pressure 16 and the flexible membrane pressure 19. At this time, the injected gas can be smoothly circulated through the exhaust port 14 which is an extension part of the retainer ring.
상기와 같이 플레이튼 패드 (1)가 변형하는 위치에 기체를 이용하여 압력을 가해줌으로써, 플레이튼 패드 (1)의 변형을 완화시켜, 웨이퍼 에지의 잔막 형상을 균일하게 조절할 수 있다.By applying a pressure to the position where the platen pad 1 deforms as described above, the deformation of the platen pad 1 can be alleviated, and the remaining film shape of the wafer edge can be uniformly adjusted.
상기 본 발명의 CMP 장치를 이용하는 연마 공정은 트랜치를 형성하거나, 절연막을 이용하여 소자 분리 (isolation)를 수행하는 일반적인 소자 제조 공정의 평탄화 공정에서 상부막을 제거할 때 사용할 수 있으며, 연마용 슬러리의 pH를 유지하면서 소자 분리된 셀 영역의 질화막 상부의 층간 절연막 즉, 산화막을 제거하기 위한 목적으로도 사용될 수 있다.The polishing process using the CMP apparatus of the present invention can be used to form a trench or to remove the top layer in the planarization process of a general device manufacturing process that performs isolation of the device using an insulating film, pH of the polishing slurry It can also be used for the purpose of removing the interlayer insulating film, that is, the oxide film on the upper part of the nitride film of the cell region separated from the element while maintaining the.
또한, 본 발명에서는 상기 본 발명의 CMP 장치와 연마용 슬러리를 이용하여 반도체 소자를 제조하는 방법을 제공할 수 있다.In addition, the present invention can provide a method for manufacturing a semiconductor device using the CMP apparatus and the polishing slurry of the present invention.
이때, 연마되는 막이 산화막인 경우, 상기 슬러리는 pH 1∼7, 바람직하게는 pH 2∼4의 산성 산화막용 슬러리나, pH 7∼14, 바람직하게는 pH 11∼13의 염기성 산화막용 슬러리 모두를 사용할 수 있다.In this case, when the film to be polished is an oxide film, the slurry may contain both an acidic oxide film slurry having a pH of 1 to 7, preferably a pH 2-4, or a slurry for a basic oxide film having a pH of 7 to 14, preferably of a pH of 11 to 13. Can be used.
상기 산화막용 슬러리에 포함되는 연마제는 50nm∼500nm 정도의 입자 크기를 가지는 콜로리달 형태나 퓸드 형태의 실리카 (SiO2), 알루미나 (Al2O3) 또는 세리아 (CeO2)를 사용하며, 슬러리 총 중량에 대해 1∼40 wt%, 바람직하게는 2∼20 wt%로 포함되는 것이 바람직하다.The abrasive included in the oxide film slurry is a colloidal or fumed silica (SiO 2 ), alumina (Al 2 O 3 ) or ceria (CeO 2 ) having a particle size of about 50 nm to 500 nm. It is preferably included in an amount of 1 to 40 wt%, preferably 2 to 20 wt%, based on the total weight.
상기 산화막용 슬러리는 일반적인 질화막이나 실리콘막에 대한 산화막의 연마 선택비가 3∼100, 바람직하게는 30∼50 정도를 가지는 것이 바람직하며, 질산 (HNO3), 인산 (H3PO4) 및 불산 (HF) 등을 포함하여 슬러리의 선택비를 조절 할 수 있다.The slurry for oxide film preferably has a polishing selectivity of oxide film with respect to a general nitride film or silicon film of 3 to 100, preferably about 30 to 50, and includes nitric acid (HNO 3 ), phosphoric acid (H 3 PO 4 ), and hydrofluoric acid ( HF), etc. may be selected to control the selectivity of the slurry.
이상에서 살펴본 바와 같이, 본 발명에서는 연마 공정 시에 플레이튼 패드의변형을 방지함으로써, 웨이퍼 전면이 균일하게 평탄화 될 수 있는 제조 방법을 제공하여 반도체 소자의 신뢰성 및 소자 특성을 개선 시키고, 소자의 수율을 향상시킬 수 있다.As described above, in the present invention, by preventing deformation of the platen pad during the polishing process, it is possible to uniformly planarize the entire surface of the wafer to improve the reliability and device characteristics of the semiconductor device, and to improve the yield of the device. Can improve.
Claims (18)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020040798A KR20040006505A (en) | 2002-07-12 | 2002-07-12 | CMP Device and Method of Forming Semiconductor Device Using the Same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020040798A KR20040006505A (en) | 2002-07-12 | 2002-07-12 | CMP Device and Method of Forming Semiconductor Device Using the Same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20040006505A true KR20040006505A (en) | 2004-01-24 |
Family
ID=37316391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020040798A KR20040006505A (en) | 2002-07-12 | 2002-07-12 | CMP Device and Method of Forming Semiconductor Device Using the Same |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20040006505A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101636254B1 (en) * | 2016-04-01 | 2016-07-07 | 주식회사 엘씨엠에스티 | Chemically polishing liquid and chemically polishing method using the same |
| CN110962037A (en) * | 2019-01-10 | 2020-04-07 | 天津华海清科机电科技有限公司 | Bearing head and chemical mechanical polishing device |
-
2002
- 2002-07-12 KR KR1020020040798A patent/KR20040006505A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101636254B1 (en) * | 2016-04-01 | 2016-07-07 | 주식회사 엘씨엠에스티 | Chemically polishing liquid and chemically polishing method using the same |
| CN110962037A (en) * | 2019-01-10 | 2020-04-07 | 天津华海清科机电科技有限公司 | Bearing head and chemical mechanical polishing device |
| CN110962037B (en) * | 2019-01-10 | 2024-05-24 | 华海清科股份有限公司 | Bearing head and chemical mechanical polishing device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6203404B1 (en) | Chemical mechanical polishing methods | |
| KR100259936B1 (en) | Polishing slurry | |
| KR101718788B1 (en) | Chemical Mechanical Polishing Composition and Methods Relating Thereto | |
| US6555476B1 (en) | Silicon carbide as a stop layer in chemical mechanical polishing for isolation dielectric | |
| KR20000058021A (en) | Chemical mechanical polishing processes and components | |
| EP0926715B1 (en) | Chemical mechanical polishing for isolation dielectric planarization | |
| US7063597B2 (en) | Polishing processes for shallow trench isolation substrates | |
| JP2000301454A5 (en) | ||
| CN100468646C (en) | Chemical-mechanical grinding method | |
| US20080261402A1 (en) | Method of removing insulating layer on substrate | |
| US20070269908A1 (en) | Method for in-line controlling hybrid chemical mechanical polishing process | |
| WO2006047088A1 (en) | Methods and compositions for chemical mechanical polishing substrates | |
| US7125321B2 (en) | Multi-platen multi-slurry chemical mechanical polishing process | |
| KR20040006505A (en) | CMP Device and Method of Forming Semiconductor Device Using the Same | |
| JP3099002B1 (en) | Two-step chemical mechanical polishing method | |
| US6190999B1 (en) | Method for fabricating a shallow trench isolation structure | |
| US20060157450A1 (en) | Method for improving hss cmp performance | |
| US7186655B2 (en) | Method for manufacturing semiconductor device | |
| US7833908B2 (en) | Slurry composition for chemical-mechanical polishing capable of compensating nanotopography effect and method for planarizing surface of semiconductor device using the same | |
| US7109117B2 (en) | Method for chemical mechanical polishing of a shallow trench isolation structure | |
| US20080314872A1 (en) | Chemical-Mechanical Polishing Compositions Containing Aspartame And Methods Of Making And Using The Same | |
| CN112331610B (en) | Method for preparing semiconductor structure | |
| JP2002043257A (en) | Method of polishing work | |
| JP2001210710A (en) | Forming process of shallow trench isolation utilizing sacrificial layer | |
| KR20010038194A (en) | Chemical mechanical polishing method for semiconductor apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |