KR200359926Y1 - The DAC Output Correction Circuit - Google Patents

Abstract

The present invention relates to a circuit for compensating the output error of a digital-analog converter used for producing an analog output in a digital circuit.

For this purpose, a method of partially linearizing the nonlinear output characteristics of a digital-analog converter is presented.

The newly designed method linearizes the nonlinear output section of the digital-analog converter by dividing it into several smaller sections, and improves the output precision by reflecting the equation obtained from the digital-analog converter.

The present invention quantifies the circuit implementation method, linearization method and procedure, dividing linearization section, and evaluation method of output precision for the target digital-to-analog converter output precision. The implementation has that feature.

Description

Output Error Compensation Circuit of Digital-to-Analog Converter

The present invention relates to a method of obtaining a high-precision output by correcting the nonlinear error of a digital-analog converter (hereinafter referred to as DAC) used to output an analog signal in a digital electronic circuit.

In the ideal case, the output characteristic of the DAC is linearly linear as shown in FIG. 1, but the output characteristic of a general DAC does not have linearity as shown in FIG. 2.

If the DAC does not have linearity, as shown in FIG. 31, the error for the DAC input always exists at a constant level.

Since the output error of the DAC is inevitable in the structure of the DAC, it is a general design method to select the DAC in consideration of the required precision for the circuit design using the DAC.

However, since the price of the DAC is expensive in proportion to the precision of the DAC, it may be a cost burden for the circuit configuration to use a DAC that produces a high-precision output to obtain a high-precision output unconditionally.

If a low-precision but low-cost DAC can be used to obtain a high-precision output, this method will work very well.

Conventional error correction method uses a lookup table compensation method that measures the output error over the entire range of the output of the DAC and stores this error in memory to reflect the DAC output.

This method requires excessive memory capacity because all error information is stored in memory over the entire DAC output range.

If, for the n-bit DAC, the required memory capacity can be calculated from Equation 1.

For example, calculating the memory capacity needed to create an error correction table for a 16-bit DAC would yield 2 ¹³ x 16 = 131.072 bytes.

Although this method can achieve a high output accuracy, the larger the number of bits in the DAC, the more memory is required, and the error compensating circuit becomes complicated and the circuit construction cost increases.

The present invention relates to a method that can output a higher output precision than the precision of the DAC using a DAC having an arbitrary output error.

To this end, it is necessary to present a quantitative method for determining the optimal linearization interval and the number of times to linearize the nonlinearity of the DAC output, and to provide a procedure and method for evaluating and validating the selection. being.

Figure 1 Output Characteristic Curves of an Ideal Digital-to-Analog Converter

Figure 2: Output Characteristic Curves of a Typical Digital-to-Analog Converter

Figure 3: Input-to-Error Characteristic Curves of Digital-to-Analog Converters

Figure 4 Error Linearization Process of Digital-to-Analog Converter

Figure 5 Error Correction Diagram of Digital-to-Analog Converter

Fig. 6 Error Compensation Curve of Each Section of Digital-to-Analog Converter

Figure 7 Residual Error Calculation after Error Correction

Figure 8 Error Recalibration

Fig. 9 Target Error vs. Recalibration Graph

Figure 10 Error Correction Flowchart of Digital-to-Analog Converter

11 is a circuit diagram of a DAC output error correction according to the present invention

40-1 of FIG. 4 shows a relationship between a command value (input) and an output error of a general DAC. If the rate of change of the error with respect to the command value is obtained from this curve, it can be displayed as shown in 41-1 of FIG.

From this curve, the point with the largest output error 41-3,41-5,41-7,41-8,41-10 and the point with the minimum sortie error 41-2,41-4,41-6,41-9 , 41-11.

These points can be used to draw a straight line as shown in 42-1, 42-2, 42-3, 42-4, 42-5, 42-6, 42-7, 42-8, 42-9 of FIG. .

If the DAC produces an output according to the characteristics of this straight line, the DAC produces an asymptotic linear output.

The linear equation for each section can be expressed as follows.

In FIG. 4-1 of FIG. 4, an arbitrary value of a section of the setpoint (x-axis) may be referred to as x, and an output error according to the setpoint may be referred to as e and expressed as a function of X.

(E is the error equation of linear section)

From Equation 2, define the magnitude of the error of the points p0 to p9 where the sign of the rate of change of the error is changed as follows (P7 to p9 are omitted).

If the error values e0, e1, e2, e3, e4, e5, e6 are connected in a straight line for the intervals p0, p1, p2, p3, p4, p5, and p6, 42-1, 42-2, 42-3 in FIG. A straight line can be obtained as shown below. The equations of these straight lines can each be expressed as equation (3).

Where k1 to k6 are calculated as Equation 4 as the slope of the first equation.

Therefore, given the setpoint, the error value to be compensated accordingly can be obtained.

In addition, since the value to be compensated is the slope of the linear equation, only one data is needed for one compensation interval.

Using Equation 4 above, the output error of the DAC can be corrected as follows.

The command value of the CPU 50 in Fig. 5 is x, the actual analog output value is A (x), the correction value stored in the table 51 is S (x), and the output value after correction is F (x). Can be written as in Equation 5.

Correction effect can be confirmed by the following method.

First, referring to one correction section as shown in FIG. 6, the output without error correction is a quadratic function as shown in 60 of FIG. 6. It can be expressed as an approximation of. The correction curve for this section p1-p0 is 61 in FIG. Can be represented.

here

Since p0 and s0 are reference values for p1 and s1, respectively, if s0 and p0 are 0, the coefficients a and b can be simplified as follows.

The sum (e) of errors occurring in the entire error compensation interval p0-p1 may be obtained as shown in Equation 6.

The total amount f of errors that can be corrected from FIG. 5 can be obtained as shown in Equation (7).

The remaining residual error E may be calculated as shown in Equation 8 after the error correction. In addition, the mean error Eavr in the interval p0-p1 is expressed by Equation 9.

The correction effect of the error is improved as in Equation 10 compared to before the correction.

That is, when the error correction by the method described in the present invention it can be seen that the average error is reduced by 75% within the calibration interval than before the calibration.

The residual error that exists even after the error correction can be obtained as follows.

The error equation f (x) in the selected section is expressed by Equation 11.

If, in Has a maximum value This becomes

It can be written as Equation 12.

Solving Equation 12 goes through the same process as Equation 13. Can be derived.

That is, the point Pmax at which the maximum value Emax of the residual error occurs after correction indicates that it is the center of the correction section.

In this case, the maximum error may be expressed as shown in Equation 14.

Arbitrary Calibration Section For the maximum error before correction as s1, the maximum residual error after correction as Emax, and the target error after correction as w, the following equation (15) must be satisfied.

If Equation 15 is satisfied, there is no need to recorrect the error.

However, if the above conditions cannot be satisfied, another straight line is drawn between the intervals p0-Pmax and recalibration is required.

If n does not satisfy Equation 15 and needs to be recalibrated n times, the first-order equation to be used can be expressed as Equation 16.

From Equation 15, if the target error is given, the number of times to be corrected can be obtained as in Equation 17.

The output error calibration of the DAC of the present invention is performed by the procedure of FIG.

As shown in FIG. 2, an input is applied to the DAC over the entire range, and the output is measured as shown in the flowchart of FIG. 10 to generate an input-to-output characteristic curve (100).

Based on this characteristic curve, an error rate of change with respect to the input is obtained (101), and an error correction section is set (102).

The coefficient of the equation is calculated for each section (103), and the maximum error for each section is calculated (104). If the maximum error is larger than the target error, the error recalibration 105 is performed until the target error is smaller than the target error.

When the calibration is completed, the coefficients of the equations obtained from the calibration are stored in non-volatile memory such as ROM (Read Only Memory).

Fig. 11 is a circuit for correcting a DAC output error according to the present invention, and a circuit implementation of the quantification method derived by the above-described formula. When the microprocessor transmits data to the DAC to produce an analog output, Data transmitted to the latches 110 and 111 is temporarily stored, and automatically outputs the DAC output error correction data from the nonvolatile memory 114 of FIG. 11 according to the size of the stored data. The output correction data is 8 bits. The MSB (Most Significant Bit) of the data has sign information. The adder 113 adds the calibration data output from the nonvolatile memory and the original data stored in the latches 110 and 111. The subtracted data is then output to the DAC. Therefore, the output calibration of the DAC can be done automatically in one write cycle of the microprocessor. Elements constituting the deulyimyeo in general will be a lot easier to get an affordable price logic elements used, the circuit can be implemented in a single Chip If you are using a PLD (Programmable Logic Device) that is widely used in recent years.

With this design, we can get enough desired accuracy by using DAC that can't produce the desired analog output precision.

By using the present invention, the average accuracy can be improved by at least 75% with respect to the output precision of the existing DAC. In addition, it is possible to predict the output precision of the DAC to be used by the number of recalibrations and the evaluation method proposed in the present invention.

By using the present invention, high-precision output can be produced by low-cost, low-precision DAC, which can reduce the cost and increase the reliability of the system in the field of industrial electronic control devices in which the DAC is used on a large scale.

Claims (2)

The latches temporarily store data output from the microprocessor, the non-volatile memory outputting correction data by referring to the output of the latches, and the subtractor for automatically adding and subtracting the correction data output from the non-volatile memory and the output data of the latches. Wow A digital-to-analog converter output precision circuit comprising a function for automatically outputting the calibration data of the DAC through a subtractor. delete