KR200347625Y1 - Parallel processing encoder - Google Patents

Abstract

The present invention relates to a parallel processing encoder, and in a parallel processing encoder using multiple digital signal processors, a parallel processing encoder capable of efficiently and rapidly performing parallel processing by eliminating data dependency between each processor. In the present invention, when the main processor loads video data from the host and divides and distributes the video data to each subordinate processor, each subordinate processor encodes the video data to generate a bit stream, and the main processor divides each bit stream into one bit. Complete by merging into a stream.

Description

Parallel Processing Encoder {PARALLEL PROCESSING ENCODER}

The present invention relates to a parallel processing encoder, and more particularly, to a parallel processing encoder in which a parallel processing encoder using multiple digital signal processors eliminates data dependencies between processors, thereby enabling efficient and rapid parallel processing for each processor.

Recently, as the field of application of digital video has been expanded, image compression technology required to use digitized video such as MPEG-4 has been developed.

However, in the encoding process of MPEG-4, neighboring blocks are referred to with respect to motion compensation prediction and generation of the motion vector. As a result, data has a dependency.

In particular, when performing the process of MPEG-4 encoding by using a multiple digital signal processor (Multi Digital Signal Processor), each processor only shares some tasks of the entire process, and each processor is assigned to itself. A method of performing only work was used.

1 is a schematic structural diagram of a conventional parallel processing encoder.

The parallel processing encoder 100 using a conventional multiple digital signal processor is usually performed through four processors DSP0 101 to DSP3 104, each of which is assigned a different constant task and overlaps at the same time. Is executed.

That is, in parallel processing, DSP0 101 obtains a source frame from a host (not shown) via PCI bus 105 and distributes it to DSP1 102 and DSP2 103, respectively. A motion vector is generated from the data through an integer motion estimation process and transmitted to the DSP2 103.

The DSP2 103 generates a quantization coefficient through a half-pixel unit motion estimation process, a motion compensation process, a discrete cosine transform process, and a quantization process based on the motion vector, transmits the quantization coefficient to the DSP3 104, and reconstructs the reconstructed frame. Transfer to DSP1 102.

The DSP3 104 transmits the bit stream generated by performing the variable length length process based on the quantization coefficients to the host (not shown) through the PCI bus 105.

However, according to the conventional parallel processing encoder, since each processor is sequentially executed while referring to the processing result of another processor, if the workload of each processor is not the same, each processor processes the processor with a large load. As a result, the result is a bottleneck caused by the idle time that each processor waits and a large amount of I / O between each processor. Therefore, each processor takes more time for excessive data movement and message delivery than for operation, resulting in a decrease in throughput.

Therefore, the present invention was devised to solve the above problems, and an object of the present invention is to remove data dependencies between processors in a parallel processing encoder using multiple digital signal processors, thereby enabling more efficient and faster parallel processing. To provide a processing encoder.

1 is a schematic structural diagram of a conventional parallel processing encoder.

2A is a schematic structural diagram of a parallel processing encoder according to the present invention.

2B is a schematic diagram of data processing of a parallel processing encoder according to the present invention.

3 is a block diagram of a video packet to which a synchronization code is designated in the parallel processing encoder according to the present invention.

4A is an illustration of a bit stream without using a resynchronization code.

4B is an illustration of a bit stream using a resynchronization code.

5 is a schematic flowchart of data processing of each processor in the parallel processing encoder according to the present invention.

6 is a flowchart of parallel processing in the parallel processing encoder according to the present invention.

* Description of the symbols for the main parts of the drawings *

1: parallel encoder 2: DSP0

3: DSP1 4: DSP2

5: DSP3 6: shared memory

7 to 10: internal memory 11: host

12: internal PCI bus 13: external PCI bus

14: VOP 15: video packet

16: Resynchronization code 17: Macroblocks

18: quantization value 19: HEC

20: macro block data

As a feature of the present invention for achieving the above object, the parallel processing encoder according to the present invention, in a parallel processing encoder for parallel processing the encoding of video data using a multiple digital signal processor, the video data from the host A main processor for distributing it to a plurality of subordinate processors and merging the generated bit streams into one bit stream; A plurality of subordinate processors for encoding the distributed video data independently and simultaneously to generate the bit stream, and to exchange data with each other; It characterized in that it comprises a shared memory for storing the generated bit stream.

In addition, as another feature of the present invention, the main processor and the dependent processor is characterized in that each of the internal memory for storing the video data.

In addition, as another feature of the present invention, the main processor is characterized in that the video data is divided equally by the number of the subordinate processor to distribute to the subordinate processor.

In another aspect of the present invention, the main processor and the subordinate processor are synchronized by exchanging interrupt messages.

In addition, as another feature of the present invention, the bit stream is characterized by consisting of a video packet including a resynchronization code (ReSync Marker).

In another aspect of the present invention, the video packet further includes a macroblock number, a quantization value, a header extension code (HEC), and macroblock data of a video object plane (VOP).

In addition, as another feature of the present invention, the main processor is characterized in that for importing the video data in byte (Byte) unit from the host.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

2A is a schematic structural diagram of a parallel processing encoder according to the present invention, and FIG. 2B is a schematic diagram of data processing of a parallel processing encoder according to the present invention.

The parallel processing encoder 1 according to the present invention uses a multi digital signal processor, which is composed of four digital signal processors DSP0 (2) to DSP3 (5), each of which has an SDRAM. Each of the internal memories 7 to 10 and the shared memory 6 commonly used by the four processors are connected.

Among the four processors, DSP0 (2), which is a main processor, takes video data from the host 11 through an external PCI bus 13, and distributes the video data to the slave processors, DSP1 (3) to DSP3 (5). It is responsible for merging the bit streams generated by the processors DSP1 (3) to DSP3 (5).

In addition, the dependent processors DSP1 (3) to DSP3 (5) perform their own tasks independently of each other, and receive the video data distributed by the main processor DSP0 (2) and encode it into MPEG-4 to decode the bit stream. And exchange data between the DSP1 (3) and the DSP3 (5).

First, DSP0 (2) takes the raw video data from the host (11) using the full bandwidth of the external PCI bus (13) and loads it into its internal memory (7).

Then, DSP1 (3) to DSP3 (5) load the video data from DSP0 (2) through the internal PCI bus 12 and copy it to its internal memory (8 to 10). After generating the bit stream by performing the -4 encoding process, the bit streams are stored in the shared memory 6, respectively.

DSP0 2 then merges each bit stream stored in the shared memory 6 into one to produce the final bit stream.

Thus, since the parallel processing encoder 1 according to the present invention distributes data to each processor, data movement occurs basically between the processors. However, in order to prevent the bottleneck caused by the slow speed of the external PCI bus 13, the DSP0 (2) video data from the host 11 once using the external PCI bus 13 as a minimum as described above. After copying to the internal memory 7 of, the distribution is performed so that most operations are performed in the internal memory 7 to 10 of each processor. This increases the speed by four times as fast as each processor pulls data through the external PCI bus 13.

In addition, since the parallelism is possible only when the loads allocated to each processor are the same, in the parallel processing encoder 1 according to the present invention, the processors performing the actual encoding process are DSP1 (3) to DSP3 (5). In consideration of the game, one frame is divided into three parts, which is the number of processors.

3 is a block diagram of a video packet to which a synchronization code is assigned in the parallel processing encoder according to the present invention.

According to the encoding process of MPEG-4, neighboring blocks are referred to with respect to motion compensation prediction and generation of motion vectors. Therefore, in the case of parallel processing by dividing one frame into three parts as in the present invention, since encoding is started at the same time point, each processor may cause a data dependency problem that requires waiting for data of neighboring blocks to be referred to from another processor. do.

In order to solve this problem, in the parallel processing encoder 1 according to the present invention, a video packet 15 includes a resynchronization code 16.

Originally, a resynchronization code provided by MPEG-4 is composed of specific bits, and when decoding a bit stream containing a bit error, the resynchronization code is placed within the bit stream to be distinguished, followed by inputting encoding information. Independent processing is possible by itself, and it has a function of preventing further propagation of bit error and minimizing deterioration of image quality.

The parallel processing encoder 1 according to the present invention utilizes the function of this resynchronization code. That is, a bit stream corresponding to one video object plane (VOP) 14 is divided into a plurality of video packets 15, and the video packet 15 includes a resynchronization code 16 and a current macro block of the VOP. It consists of a number 17, a quantization value 18, HEC (Header Extension Code) 19, which is a flag bit indicating whether additional header information exists, and macro block data 20.

Therefore, in this case, since the VOP information necessary for encoding is already contained in each video packet 15, the video packet 15 divided by the resynchronization code 16 can be processed independently without the need for previous information. It becomes possible. Thus, by using this, one frame is divided into several blocks by the number of processors so that each processor can independently process allocated blocks. The following example will be described in more detail.

4A is an exemplary diagram of a bit stream without using a resynchronization code, and FIG. 4B is an exemplary diagram of a bit stream using a resynchronization code.

When merging bit streams created by each processor into one bit stream, the bit streams generated by DSP1 (3) and DSP2 (4) are not yet byte-aligned unless resynchronization code is used. As a result, DSP0 (2) must eventually read the bit stream of each processor stored in the shared memory 6 by one bit and move by one bit to generate the complete bit stream.

However, when using resynchronization code, one video data is made into a bit stream that is completely aligned with three bytes. Thus, in this case, even though DSP0 (2) uses 32-bit registers to get each data from the host 11 in bytes rather than bits, each DSP1 (3) to DSP3 (5) can create a complete bit stream. do.

If the size of the bit stream of one full frame is 3K bits, if the resynchronization code 16 is not used, a total of 3x1,024 bit operations, or 3,072 times, must be performed. ), DSP0 (2) uses 32-bit register to get each data from the host 11 in byte units, so a total of 3 × 1,024 / 32 times, or 96 circuit byte units, can be performed. The speed is increased by 32 times.

Hereinafter, parallel processing of the parallel processing encoder according to the present invention will be described.

In the parallel processing encoder 1 according to the present invention, each subordinate processor 3 to 5 receives divided video data and processes them independently, but the bit stream generated by each subordinate processor 3 to 5 is constant. The order exists. That is, for example, when a reconstructed image is made through padding, data movement occurs between the subordinate processors 3 to 5, and thus synchronization is required to match a certain order between data. In addition, since all processors 2 to 5 share the shared memory 6, synchronization is necessary to allow each processor 2 to 5 to access the shared memory 6 without colliding with each other during data movement. Do.

Synchronization methods include polling using semaphores, but since this causes a bottleneck in the internal PCI bus, the present invention uses a message that generates an interrupt between each processor (2 to 5). .

5 is a schematic flowchart of data processing of each processor in the parallel processing encoder according to the present invention.

Here, in order to conceptually describe the parallel processing in the parallel processing encoder according to the present invention, the terms main processor and subordinate processor are used instead of the terms DSP0 (2) to DSP3 (5).

First, DSP0 (2) which is a main processor and DSP1 (3) -DSP3 (5) which are dependent processors respectively perform initialization (S101, S201). At this time, the user defines a range of encoding operations of the parallel processing encoder by defining a range of frames to be encoded in advance.

The main processor loads raw video data from the host 11 (S102), and the slave processor waits for a load completion message of the video data (S202).

When the main processor delivers the load completion message of the video data to the subordinate processor as an external interrupt (S103), the subprocessor loads the video data from the main processor (S203) and performs a conventional MPEG-4 encoding process to perform a bit stream. To generate (S204). In this case, the MPEG-4 encoding process includes a discrete cosine transform process, a quantization process, an inverse quantization process, an inverse discrete cosine transform process, a variable length encoding process, a motion estimation and a compensation process, and the like.

Thereafter, the main processor loads video data to be encoded next from the host 11 (S104), and waits for a bit stream storage completion message from the slave processor (S105). At this time, the slave processor stores the generated bit stream in the shared memory 6 and transmits a bit stream storage completion message to the main processor (S205).

The main processor loads each bit stream from the shared memory 6 (S106), merges it into one bit stream, and completes it (S107). Meanwhile, the slave processors copy and exchange data necessary for each other (S206).

Then, the main processor and the subordinate processor check whether the video data to be loaded after encoding has exceeded the encoding execution range predetermined by the user (S108 and S207). That is, it is checked whether the video data to be encoded after being loaded is outside the range of the frame to be encoded. At this time, if it exceeds, the encoding parallel processing ends, and if not, it returns to the original loop (S103, S202).

Hereinafter, the parallel processing in the parallel processing encoder according to the present invention will be described in more detail.

6 is a flowchart of parallel processing in the parallel processing encoder according to the present invention.

First, the main processor DSP0 (2) retrieves and loads raw video data from the host 11 (S301), and transmits a video data load completion message to the subordinate processor DSP1 (3) (S302).

The DSP1 (3) waits for a message from the DSP0 (2) and receives the video data load completion message from the DSP0 (2) (S302), and the allocated video data (1/3 of the entire video data). ) Is loaded from DSP0 (2) (S402), and the video data load complete message is transferred to DSP2 (4), the next dependent processor (S403). In operation S404, a bit stream is generated by performing an encoding process of MPEG-4.

The DSP2 4 waits for a message from the DSP1 3 (S501), and receives the video data load completion message from the DSP1 3 (S403). Similarly, the allocated video data (1 / of all video data) is received. 3) is loaded from DSP0 (2) (S502), and the video data load completion message is transferred to DSP3 (5), the next dependent processor (S503). In operation S504, a bit stream is generated by performing an encoding process of MPEG-4.

The DSP3 (5) also waits for a message from the DSP2 (4) and receives the video data load completion message from the DSP2 (4) (S503). Similarly, the allocated video data (1 / of the entire video data). 3) is loaded from DSP0 (2) (S602), and the video data load completion message is transferred to DSP0 (2) (S603). In operation S604, a bit stream is generated by performing an encoding process of MPEG-4.

The DSP0 (2) waits for a message from the DSP3 (5) (S303), and receives the video data load completion message from the DSP3 (5) (S603), and then receives the next video data to be encoded from the host (11). It is loaded (S304).

Meanwhile, the DSP1 3 stores the generated bit stream in the shared memory 6 (S405), and transmits a bit stream storage completion message to the DSP2 4 (S406).

The DSP2 4 waits for a message from the DSP1 3 (S505), and when the bitstream storage completion message is received from the DSP1 3 (S406), the generated bit stream is transferred to the shared memory 6. In operation S506, the bitstream storage completion message is transmitted to the DSP3 5 (S507).

The DSP3 (5) also waits for a message from the DSP2 (4) (S605). When the bitstream storage completion message is received from the DSP2 (3) (S507), the generated bit stream is transferred to the shared memory (6). In operation S606, the bit stream storage completion message is transmitted to the DSP0 2 (S607).

The DSP0 (3) waits for a message from the DSP3 (5) (S305), and receives the bit stream storage completion message from the DSP3 (5) (S607), respectively, the DSP1 (3) stored in the shared memory (6). The bit stream of the DSP3 (5) is loaded (S306 to S308), merged into one bit stream, and completed and stored in the internal memory 7 (S309).

In addition, each of DSP1 (3) to DSP3 (5) performs VOP padding for texture coding of an object boundary portion (S407, S508, S608).

At this time, the DSP2 4 processes the middle block among the allocation blocks divided into three frames of one frame as shown in FIG. 4B, and therefore, DSP1 (3) processing the upper block and DSP3 (5) processing the lower block. And both will exchange data.

That is, the DSP1 3 stores data to be provided to the DSP2 4 in the shared memory 6 (S408), and then transfers a data storage completion message to the DSP2 4 (S409).

The DSP2 4 stores the data to be provided to the DSP1 3 and the DSP3 5 in the shared memory 6 (S509), and then transfers a data storage completion message to the DSP1 3 and the DSP3 5 ( S510).

The DSP3 5 stores data to be provided to the DSP2 4 in the shared memory 6 (S609), and then transfers a data storage completion message to the DSP2 4 (S610).

The DSP1 3 waits for a message from the DSP2 4 (S410), and receives the data storage completion message from the DSP2 4 (S510), and loads the data from the shared memory 6 (S411). Wait for the next video data load completion message from DSP0 (2) (S401).

The DSP2 (4) waits for a message from the DSP1 (3) and the DSP3 (5) (S511), and receives the data storage completion message from the DSP1 (3) and the DSP3 (5) (S409, S610), sharing The data is loaded from the memory 6 (S512), and the next video data load completion message from the DSP1 (3) is waited for (S501).

The DSP3 (4) also waits for a message from the DSP2 (4). When receiving the data storage completion message from the DSP2 (4) (S510), the data is loaded from the shared memory 6 (S612). Waits for the next video data load completion message from DSP2 (S601).

As described above, the parallel processing encoder according to the present invention eliminates data dependency between processors in a parallel processing encoder using multiple digital signal processors, thereby causing each processor to become a bottleneck due to idle time due to standby or excessive data movement. Parallel processing is possible without a phenomenon, so that parallel processing is more efficient than before.

In addition, the parallel processing encoder according to the present invention implements operations on bit streams generated through encoding processing in byte units instead of bit units, thereby enabling parallel processing having a much improved speed than in the related art.

Claims (7)

In the parallel processing encoder for parallel processing the encoding of video data using multiple digital signal processor, A main processor which takes the video data from the host and distributes the video data to a plurality of subordinate processors and merges the generated bit stream into one bit stream; A plurality of subordinate processors for generating the bit stream by simultaneously encoding the distributed video data independently of each other and exchanging data with each other; And a shared memory for storing the generated bit stream. The parallel processing encoder of claim 1, wherein the main processor and the subordinate processor each include an internal memory that stores the video data. The parallel processing encoder of claim 1, wherein the main processor equally divides the video data by the number of the subordinate processors and distributes the video data to the subordinate processors. 4. The parallel processing encoder according to any one of claims 1 to 3, wherein the main processor and the subprocessor are synchronized by exchanging interrupt messages. 4. The parallel processing encoder according to any one of claims 1 to 3, wherein the bit stream is made of a video packet including a ReSync Marker. 6. The parallel processing encoder of claim 5, wherein the video packet further includes a macroblock number of a video object plane (VOP), a quantization value, a header extension code (HEC), and macroblock data. 4. The parallel processing encoder according to any one of claims 1 to 3, wherein the main processor obtains the video data from the host in units of bytes.