KR200305642Y1 - Single Spread Code Generator - Google Patents

Abstract

The present invention relates to a short spread code generator, and more particularly, to a short spread code generator that is compatible with IS-95 and can be used in various bands.

Such a wideband short spread code generator is a spreading signal generator having a maximum length shift register that repeats 2 ¹⁵ clock cycles, the mask being programmed to have a random value different from the value stored in the maximum length shift register. The register unit includes a parallel mask unit in which a plurality of sequences having different offsets are output in parallel by being masked by the mask unit, and a multiplexing unit for multiplexing and sequentially outputting the plurality of parallel sequences having different offsets.

Description

Broadband short spread code generator

The present invention relates to a short spread code generator, and more particularly, to a short spread code generator that is compatible with IS-95 and can be used in various bands.

In the mobile communication network using the Code Division Multiple Access (CDMA) method, the receiving party can quickly and accurately determine the PN sequence (or PN code) transmitted to the calling party in order to provide a good quality communication service during the mobile terminal period. You must capture and synchronize the two sequences.

In particular, in the next generation mobile communication service, a wireless multimedia communication service in which a plurality of mobile terminal users transmit and receive data such as images and texts by connecting a mobile terminal with a portable data terminal such as a personal digital assistant (PDA) in a given frequency band is provided. Required.

Hereinafter, a conventional short spread code generator will be described with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a transceiver of a general code division multiple access device.

As shown in FIG. 1, a general code division multiple access apparatus includes a transmitter 1 to which audio, video and text data are input, and a receiver 6 to receive and output data transmitted from the transmitter 1.

In this case, the transmitter 1 is a channel encoding unit 2 for assigning and encoding a channel to the input data and a short PN (Pseduo Noise) sequence used in the IS-95 series. A first spreading unit 4 that adds a single spreading code generator 3, data encoded by the channel encoding unit 2, and a short pseudo noise sequence generated by the first short spreading code generator 3; And a modulator 5 for modulating the spread data.

The receiver 6 includes a demodulator 7 for receiving and demodulating data modulated by the transmitter 1, and a second single spread code generator for generating a short pseudo noise sequence used in the IS-95 series. (8), a second spreader (9) that sums the data demodulated by the demodulator (7), a short pseudo noise sequence generated by the second short spread code generator (8), and the despread And a channel decoding unit 10 for decoding the data and outputting the received channel.

The transmitting / receiving feature of the code division multiple access device is that a plurality of users share a time and frequency with respect to one channel 11, and a pseudo noise sequence having a low cross-correlation is assigned to each user so that each user is assigned a pseudo random sequence. It spreads and transmits the signal to be transmitted, and the receiving side synchronizes to generate the pseudorandom sequence same as that used by the transmitting side, and de-spreads the received signal and restores the received signal to the desired signal.

2 is a block diagram illustrating in detail a short spread code generator of a conventional code division multiple access device.

Looking at the short-spread code generator of the conventional code division multiple access device in detail, as shown in Figure 2, the maximum length shift register (2) to generate a 2 ¹⁵ chip rate by receiving a 1.2288MHz clock ( 21, a mask register 22 for outputting contents programmed in the central processing unit (CPU), and a mask unit 23 for masking contents of the maximum length shift register 21 and the mask register 22. ) To generate a wide bandwidth spread sequence of 1.2288 MHz. At this time, the 1.2288 MHz wideband spreading sequence has a 1.26 MHz bandwidth through filtering.

In this case, the value of the mask register 22 is a value for moving the short spread signal to the time axis as much as desired, and may generate a short spread signal having various offsets.

The maximum length shift register 21 is a 15-bit shift register with a feedback circuit that allows the sequence to repeat after 2 ¹⁵ , i.e., 2, ¹⁵ clocks, and the mask register 22 is a central processing unit. As a 15-bit register whose contents can be changed, the contents of the maximum length shift register 21 and the contents of the mask register are masked by the mask section 23.

At this time, the mask unit 23 is modulo-2 added with 15 bits logically ANDed for each bit of the maximum length shift register 21 and the mask register 22. In other words, 0 is outputted evenly and 1 is outputted oddly, by adding the value from the maximum length shift register 21 and the value from the mask register 22.

That is, the result is the same as the result of the calculation using the XOR (Exclusive OR) gate.

In this case, the maximum length shift register 21 generates a spread signal having a period of 2 ¹⁵ chip rates, that is, 26.67 msec through insertion of zero (0), and a polynomial that generates a spread signal of 1.2288 MHz is an IS-95 series. It is defined in the standard.

In other words, dividing the chip rate of 2 ¹⁵ by 1.2288 MHz, which is a standard of the IS-95 series, generates a spread signal having a period of 26.67 msec.

In this case, the spread signal of 26.67 msec represents a period of one short PN sequence.

In the operation of the conventional short spread code generator, when a 1.2288 MHz clock signal is input to the maximum length shift register 21, the contents of the maximum length shift register 21 are changed by the polynomial defined in the standard. Must receive 2 ¹⁵ clocks and the same thing will repeat.

When using the direct spread method to transmit a wideband signal, the single spreading code generator maintains one frame of 80 msec, and one frame of 80 msec is divided into 20 msec or 26,67 msec.

In the IS-95C, it is possible to use a frequency of several bandwidths. There are a direct spreading method using only one 1.2288MHz × N signal and a multicarrier method using several 1.2288MHz signals.

However, the standard of the short spread code for the 1.2288 MHz x N times the spread to use the direct spread has not been determined yet.

The conventional short spread code generator as described above has the following problems.

Currently, the short-spread signal defined in IS-95 has a bandwidth of 1.25 MHz, and it is not defined to generate a wideband CDMA signal that is N times 1.25 MHz. The clock rate of the short-spread signal to generate a wideband CDMA signal is not defined. If N is increased by N times, it is inevitable to change the frame and modulation symbol boundary points of existing channels.

The present invention solves the problems of the conventional single spreading code generator as described above, while configuring a plurality of mask registers and mask units, and a multiplexing unit to maintain existing system timing through parallel masking and sequential output. An object of the present invention is to provide a wideband short spread code generator capable of improving transmission speed.

A wideband short spread code generator for achieving the above object is a spreading signal generator having a maximum length shift register that repeats 2 ¹⁵ clock cycles, wherein the wideband short spread code generator has a random length different from the value stored in the maximum length shift register. The mask register portion programmed to have a value of is masked in the mask portion, and a plurality of sequences having different offsets are output in parallel, and a plurality of parallel sequences having different offsets are multiplexed and sequentially output. It includes a multiplexing unit.

Preferably, the parallel mask unit includes a plurality of mask register units programmed to have different random values, different random register values output from the plurality of mask register units, and clock signals output from the maximum length shift register. It is composed of a plurality of mask parts which are input and output in parallel a sequence having different offsets.

1 is a block diagram schematically illustrating a transceiver of a general code division multiple access (CDMA) device;

2 is a block diagram illustrating in detail a short spread code generator of a conventional code division multiple access device;

3 is a detailed block diagram of a wideband short spread code generator of a code division multiple access device according to a first embodiment of the present invention;

4 is a detailed block diagram of a wideband short spread code generator of a code division multiple access device according to a second embodiment of the present invention;

Explanation of symbols for main parts of the drawings

31, 41: maximum length shift register 32: parallel mask portion

33, 42: mask registers 34, 44: mask portion

35, 43: MUX

As described above, the inventive broadband short spread code generator will be described with reference to the accompanying drawings.

3 is a detailed block diagram of a wideband short spread code generator of a code division multiple access device according to a first embodiment of the present invention.

As shown in FIG. 3, the wideband short spread code generator of the code division multiple access device according to the first embodiment of the present invention receives a 1.2288 MHz clock signal and a maximum length shift register 31 for repeating 2 ¹⁵ clock cycles. The mask register unit 33 is programmed to have an arbitrary value different from the value stored in the maximum length shift register 31, and the plurality of sequences having different offsets in parallel are masked in the mask unit 34. The parallel mask unit 32 outputs a multiplexer (MUX) (multiplexer) 35 which multiplexes and sequentially outputs a parallel sequence having different offsets.

The parallel mask section 32 includes a mask register 33 composed of first, second ... nth mask registers 33a, 33b, 33n, which store n different mask values. ) And a mask portion 34 for masking the contents of the first and second n-th mask registers 33a and 33b and the contents of the maximum length shift register 31. The mask portion 34 is also composed of a plurality of first, second ... n-th mask portions 34a, 34b, ... 34n. That is, the mask register 33 and the mask portion 34 are configured in the same number.

The mux 35 receives n-bit inputs having different values generated by the parallel mask unit 32 and sequentially outputs one bit at a time.

The broadband short spread code generator according to the first embodiment of the present invention drives the maximum length shift register 31 at the same speed, that is, 1.2288 MHz while maintaining the frame structure of the existing channel and the modulation symbol boundary. In the first and second n-th mask registers 33a, 33b, 33n, which are 15-bit registers in which the device CPU can change its contents, n different mask values are selected. It outputs to the 1st, 2nd ... n-th mask part 34a, 34b ... 34n.

At this time, the mask value of each of the first and second n-th mask registers 33a, 33b, 33n is programmed to have a different value while generating a PN sequence having a unique offset. .

The relative value of each mask value is fixed for the initial sequence. The mask value of the mask register 33 determined in this way is input to the mask unit 34, n bits are output from the mask unit 34 to the mux 35, and n bits are received from the mux 35. Output bit by bit sequentially.

4 is a detailed block diagram of a wideband short spread code generator of a code division multiple access device according to a second embodiment of the present invention.

As shown in FIG. 4, the wideband short spread code generator of the code division multiple access apparatus according to the second embodiment of the present invention receives a clock signal of 1.2288 MHz and a maximum length shift register 41 for repeating 2 ¹⁵ clock cycles. A mask register 42 composed of a plurality of first and second n-th mask registers 42a, 42b, and 42n, each of which stores n different mask values; A mux 43 for receiving n x 15-bit inputs of the second ... n-th mask registers 42a, 42b ... 42n and outputting them sequentially by 15 bits, and the mux (multiplexer) And a mask section 44 which receives and masks the mask values sequentially output in step 43 and the values stored in the maximum length shift register 41 and outputs a wideband spread signal of n x 1.2288 MHz.

The wideband short spread code generator according to the second embodiment of the present invention is programmed so as to have a unique offset value, and the mask register 42 having a sequence having a unique offset is preferentially multiplexed. Same as the first embodiment.

The wideband short spread code generator according to the present invention has the following effects.

The frame structure and modulation symbol boundary of each channel, which are determined by the contents of the maximum length shift register and the driving speed, generate a wideband spread signal of n × 1.2288MHz while using the same method as the conventional method. Since a pilot signal is generated as a short spread signal having a band of, multiple types of offsets (n times larger than conventional ones) are transmitted during a unit time, thereby making it easy for the receiving side to synchronize the calling party.

Claims (4)

A spreading signal generator having a maximum length shift register for repeating 2 ¹⁵ clock cycles, A parallel mask unit in which a value of a mask register unit programmed to have an arbitrary value different from a value stored in the maximum length shift register is masked in the mask unit, and a plurality of sequences having different offsets are output in parallel; And a multiplexer configured to multiplex and output the plurality of parallel sequences having different offsets sequentially. 2. The apparatus of claim 1, wherein the parallel mask portion is output from a plurality of mask register portions programmed to have different random values, different random register values output from the plurality of mask register portions, and the maximum length shift register. A wideband short spread code generator comprising: a plurality of mask parts configured to receive a clock signal and output a sequence having different offsets in parallel. 2. The wideband short spread code generator of claim 1, wherein the multiplexer outputs a wideband spread sequence of N x 1.2288 MHz. A spreading signal generator having a maximum length shift register for repeating 2 ¹⁵ clock cycles, A plurality of mask registers storing n different mask values; A multiplexer which sequentially receives a mask value of the mask register and sequentially outputs the mask value; And a mask unit configured to receive a mask value sequentially output from the multiplexer and a clock signal generated from a maximum length shift register, and output a wideband spread signal by masking the mask signal.