KR20030087672A - Method for producing Nonvolatile semiconductor memory device - Google Patents
Method for producing Nonvolatile semiconductor memory device Download PDFInfo
- Publication number
- KR20030087672A KR20030087672A KR1020020025511A KR20020025511A KR20030087672A KR 20030087672 A KR20030087672 A KR 20030087672A KR 1020020025511 A KR1020020025511 A KR 1020020025511A KR 20020025511 A KR20020025511 A KR 20020025511A KR 20030087672 A KR20030087672 A KR 20030087672A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor substrate
- region
- silicon
- oxide film
- gate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000206 photolithography Methods 0.000 claims description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 150000004767 nitrides Chemical class 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000015654 memory Effects 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- XUIMIQQOPSSXEZ-NJFSPNSNSA-N silicon-30 atom Chemical compound [30Si] XUIMIQQOPSSXEZ-NJFSPNSNSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 비휘발성 메모리소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a nonvolatile memory device.
현재, 공정 기술 측면에서 비휘발성 반도체 메모리소자(NVM : Nonvolatile semiconductor memories)는 크게 부유 게이트(Floating gate)계열과 두 종류 이상의 유전막이 2중, 혹은 3중으로 적층된 MIS(Metal insulator Semiconductor)계열로구분된다. 부유 게이트 계열은 전위 우물을 이용하여 프로그램/지우기(program/erase)를 구현하고, MIS 계열은 유전막 벌크, 유전막 - 유전막 및 유전막- 반도체 계면에 존재하는 트랩을 이용하여 프로그램/지우기를 구현한다.At present, in terms of process technology, nonvolatile semiconductor memories (NVMs) are largely divided into floating gate series and two or triple dielectric insulator semiconductor (MIS) series. do. The floating gate series implements program / erase using potential wells, and the MIS series implements program / erase using traps present at the dielectric bulk, dielectric layer-dielectric and dielectric-semiconductor interfaces.
현재는 MIS 계열에서 주로 응용되고 있는 플래시 메모리에는 MONOS(metal -ono-silicon)/SONOS(silicon-ono-silicon) 구조를 대표적으로 사용되고 있다.Currently, MONOS (metal-ono-silicon) / SONOS (silicon-ono-silicon) structures are used for the flash memory mainly applied in the MIS series.
상술한 바와 같은 SONOS구조의 비휘발성 메모리소자의 제조방법을 도시한 공정순서도가 도 1 내지 도 4 이고 이를 살펴보면 다음과 같다.A process flowchart illustrating a method of manufacturing a nonvolatile memory device having a SONOS structure as described above is shown in FIGS. 1 to 4.
우선, 실리콘(Si)으로 이루어진 반도체 기판(10)상에 절연층으로 제1 산화막(12)을 형성하고, 그 상부에 플로팅 게이트용 실리콘 질화막(14)을 형성한 후, 절연층으로 제2 산화막(16)을 차례대로 적층하여 오엔오(ONO:oxide-SiN-oxide)구조를 형성한다.First, a first oxide film 12 is formed as an insulating layer on a semiconductor substrate 10 made of silicon (Si), and a silicon nitride film 14 for floating gate is formed thereon, followed by a second oxide film as an insulating layer. (16) is sequentially stacked to form an ONO: oxide-SiN-oxide structure.
이렇게 형성된 오엔오 구조에 사진 및 식각공정을 수행하여 상기 반도체 기판이 노출된 게이트 전극이 형성될 영역을 정의하고, 게이트 산화공정을 실시하여 측벽 게이트전극가 형성될 영역에 산화막(20)을 형성하여 정의하고, 그 상부에 콘트롤 게이트가 형성될 게이트 폴리실리콘(22)을 형성하여 SONOS 구조의 측벽 게이트를 형성한다.The photo-etching process is performed on the oho structure thus formed to define a region where the gate electrode exposed to the semiconductor substrate is to be formed, and the oxide film 20 is formed on the region where the sidewall gate electrode is to be formed by performing a gate oxidation process. The gate polysilicon 22 on which the control gate is to be formed is formed thereon to form sidewall gates of the SONOS structure.
상기와 같이 반도체 장치의 플로닝 게이트로 실리콘 질화막(14)을 사용하게 되는데, 이는 도 4와 같이 게이트 폴리실리콘(22)과 접촉하게 된다. 그러나 게이트 폴리실리콘 - 제2 산화막 - 질화막 - 제1 산화막으로 순차적으로 전자가 이동하여플래시 메모리의 소거 등이 진행되는데, 상기 접촉으로 인해 제2 산화막(16)을 거치지 않고 바로 실리콘 질화막(14)으로 이동하게 된다.As described above, the silicon nitride layer 14 is used as the floating gate of the semiconductor device, which contacts the gate polysilicon 22 as shown in FIG. 4. However, electrons move sequentially to the gate polysilicon, the second oxide film, the nitride film, and the first oxide film, thereby erasing the flash memory. The contact causes the silicon nitride film 14 to directly pass through the second oxide film 16. Will move.
따라서 이는 메모리의 소거를 진행할 때 지우기 특성이 저하될 수 있는 문제점이 있다.Therefore, there is a problem that the erase characteristic may be degraded when the memory is erased.
상술한 바와 같은 문제점을 해결하기 위한 본 발명의 목적은 SONOS 구조에서 ONO 막의 질화막과 게이트 폴리실리콘이 접촉하는 것을 방지할 수 있도록 하는 비휘발성 메모리소자 및 제조방법에 관한 것이다.SUMMARY OF THE INVENTION An object of the present invention for solving the above-described problems relates to a nonvolatile memory device and a manufacturing method for preventing contact between a nitride film of an ONO film and a gate polysilicon in a SONOS structure.
도 1 내지 도 4는 종래의 비휘발성 메모리소자의 제조방법을 순차적으로 도시한 공정순서도1 to 4 are process flowcharts sequentially showing a conventional method of manufacturing a nonvolatile memory device.
도 5 내지 도 9는 본 발명의 일실시예에 따른 비휘발성 메모리소자의 제조방법을 순차적으로 도시한 공정순서도5 through 9 are flowcharts sequentially showing a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.
도 10 내지 도 14는 본 발명의 또 다른 일실시예에 따른 비휘발성 메모리소자의 제조방법을 순차적으로 도시한 공정순서도10 to 14 are flowcharts sequentially showing a method of manufacturing a nonvolatile memory device according to another embodiment of the present invention.
상기 목적을 달성하기 위한 본 발명은, 실리콘으로 이루어진 반도체 기판상에 제1 절연층, 도전층, 제2 절연층을 형성하여 ONO구조를 형성하는 단계; 상기 ONO구조를 사진 및 식각공정을 수행하여 게이트 전극이 형성될 영역을 정의하는 단계; 상기 반도체 기판이 노출된 게이트 전극이 형성될 영역에 실리콘 질화막과 접촉되지 않도록 하는 높이로 실리콘을 선택적으로 성장하는 단계; 게이트 산화공정을 실시하여 산화막을 형성하는 단계; 상기 산화막 상부에 게이트 폴리실리콘을 형성하는 단계로 이루어진다. 상기 실리콘을 선택적으로 성장시킬 때는 DCS와 HCL을 동시에 사용하는 것이 바람직하다.The present invention for achieving the above object comprises the steps of forming an ONO structure by forming a first insulating layer, a conductive layer, a second insulating layer on a semiconductor substrate made of silicon; Performing a photolithography and etching process on the ONO structure to define a region where a gate electrode is to be formed; Selectively growing silicon to a height such that the semiconductor substrate is not in contact with the silicon nitride film in a region where the gate electrode is exposed; Performing a gate oxidation process to form an oxide film; Forming a gate polysilicon on the oxide layer. When selectively growing the silicon, it is preferable to use DCS and HCL simultaneously.
또 본 발명은 실리콘으로 이루어진 반도체 기판상에 제1 산화막, 실리콘 질화막을 형성하여 이를 사진 및 식각공정을 수행하여 상기 반도체 기판이 노출된 게이트 전극이 형성될 영역을 정의하는 단계; 상기 반도체 기판이 노출된 게이트 전극이 형성될 영역 및 상기 제1 산화막과 실리콘 질화막이 적층된 영역에 성장가스를 이용하여 반도체 기판이 노출된 게이트전극이 형성될 영역에는 반도체 기판의 실리콘을 성장하고, 상기 제1 산화막과 실리콘 질화막이 적층된 영역에는 폴리실리콘을 성장하는 단계; 게이트 산화공정을 실시하여 산화막을 형성하는 단계; 상기 산화막 상부에 게이트 폴리실리콘을 형성하는 단계로 이루어진다. 상기 반도체 기판이 노출된 게이트 전극이 형성될 영역 및 상기 제1 산화막과 실리콘 질화막이 적층된 영역을 선택적으로 성장시킬 때는 SiH4를 사용하는 것이 바람직하다.The present invention also includes forming a first oxide film and a silicon nitride film on a semiconductor substrate made of silicon, and performing a photolithography and etching process to define a region where a gate electrode to which the semiconductor substrate is exposed is formed; Growing silicon on the semiconductor substrate in a region where the gate electrode, to which the semiconductor substrate is exposed, is formed, and a region where the gate electrode, where the semiconductor substrate is exposed, is formed using a growth gas in a region where the first oxide film and the silicon nitride film are stacked; Growing polysilicon in a region where the first oxide film and the silicon nitride film are stacked; Performing a gate oxidation process to form an oxide film; Forming a gate polysilicon on the oxide layer. It is preferable to use SiH 4 to selectively grow a region where the gate electrode exposed to the semiconductor substrate is to be formed and a region where the first oxide film and the silicon nitride film are stacked.
본 발명은 SNONS 구조의 ONO막에 질화막과 게이트 폴리실리콘이 접촉하는 것을 방지하기 위해 게이트 폴리실리콘이 형성되는 영역을 정의하는 것에 관한 것이다.The present invention relates to defining an area where a gate polysilicon is formed in order to prevent the nitride film and the gate polysilicon from contacting the ONO film of the SNONS structure.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 일실시 예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 5 내지 도 9는 본 발명의 일실시예에 따른 비휘발성 메모리소자 및 그 제조방법을 순차적으로 도시한 공정순서도5 to 9 are process flowcharts sequentially illustrating a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention.
우선, 실리콘(Si)으로 이루어진 반도체 기판(10)상에 절연층으로 제1 산화막(12)을 형성하고, 그 상부에 플로팅 게이트용 실리콘 질화막(14)을 형성한 후, 절연층으로 제2 산화막(16)을 차례대로 적층하여 오엔오(ONO:oxide-SiN-oxide)구조를 형성한다.First, a first oxide film 12 is formed as an insulating layer on a semiconductor substrate 10 made of silicon (Si), and a silicon nitride film 14 for floating gate is formed thereon, followed by a second oxide film as an insulating layer. (16) is sequentially stacked to form an ONO: oxide-SiN-oxide structure.
이렇게 형성된 오엔오 구조에 사진 및 식각공정을 수행하여 게이트 전극이 형성될 영역을 정의하고, 상기 반도체 기판이 노출된 게이트 전극이 형성될 영역에 실리콘 질화막과 접촉되지 않도록 하는 높이로 실리콘(30)을 선택적으로 성장시킨다. 그 상부에 게이트 산화공정을 실시하여 산화막(32)이 형성하고, 그 상부에 콘트롤 게이트가 형성될 게이트 폴리실리콘(34)을 형성하여 SONOS 구조의 측벽 게이트가 형성된다.The photo-etching process is performed on the formed ohmic structure to define a region where the gate electrode is to be formed, and the silicon 30 is raised to a height such that the semiconductor substrate is not in contact with the silicon nitride film in the region where the gate electrode is to be formed. Grow selectively. The oxide film 32 is formed by performing a gate oxidation process on the upper portion thereof, and the gate polysilicon 34 on which the control gate is to be formed is formed on the upper portion thereof to form sidewall gates of the SONOS structure.
이때, 실리콘을 선택적으로 성장시킬 때는 성장가스를 사용하게 되는 데, 본 발명은 DCS와 HCL을 동시에 사용하게 된다.In this case, when the silicon is selectively grown, a growth gas is used, and the present invention uses DCS and HCL simultaneously.
도 10 내지 도 14는 본 발명의 또 다른 일실시예에 따른 비휘발성 메모리소자 및 그 제조방법을 순차적으로 도시한 공정순서도이고 이를 설명하면 다음과 같다.10 to 14 are flowcharts sequentially showing a nonvolatile memory device and a method of manufacturing the same according to another embodiment of the present invention.
우선, 실리콘(Si)으로 이루어진 반도체 기판(10)상에 절연층으로 제1 산화막(12)을 형성하고, 그 상부에 플로팅 게이트용 실리콘 질화막(14)을 형성한다. 이 제1 산화막(12) 및 실리콘 질화막(14)에 사진 및 식각공정을 수행하여 상기 반도체 기판이 노출된 게이트 전극이 형성될 영역을 정의한다. 이어서 상기 반도체 기판이 노출된 게이트 전극이 형성될 영역 및 상기 제1 산화막과 실리콘 질화막이 적층된 영역에 SiH4인 성장가스를 이용하여 반도체 기판이 노출된 게이트전극이 형성될 영역에는 반도체 기판의 실리콘(44)을 성장하고, 상기 제1 산화막과 실리콘 질화막이 적층된 영역에는 폴리실리콘(42)을 성장하게 된다. 그 상부에 게이트 산화공정을 실시하여 산화막(32)이 형성하고, 그 상부에 콘트롤 게이트가 형성될 게이트 폴리실리콘(34)을 형성하여 SONOS 구조의 측벽 게이트가 형성된다.First, a first oxide film 12 is formed as an insulating layer on a semiconductor substrate 10 made of silicon (Si), and a silicon nitride film 14 for floating gate is formed thereon. A photolithography and an etching process are performed on the first oxide layer 12 and the silicon nitride layer 14 to define a region in which the gate electrode to which the semiconductor substrate is exposed is to be formed. Subsequently, silicon of the semiconductor substrate may be formed in a region where the gate electrode on which the semiconductor substrate is exposed is formed and a region where the gate electrode on which the semiconductor substrate is exposed is formed using a growth gas of SiH 4 in a region where the first oxide film and the silicon nitride film are stacked. 44), and polysilicon 42 is grown in the region where the first oxide film and the silicon nitride film are stacked. The oxide film 32 is formed by performing a gate oxidation process on the upper portion thereof, and the gate polysilicon 34 on which the control gate is to be formed is formed on the upper portion thereof to form sidewall gates of the SONOS structure.
이상에서 살펴본 바와 같이 본 발명은 SONOS 구조에서 실리콘을 성장 또는 산화시켜 측벽게이트구조가 형성될 영역을 정의함으로써 실리콘 질화막과 게이트 폴리실리콘이 접촉하는 것을 방지할 수 있도록 하는 효과가 있다.As described above, the present invention has an effect of preventing the silicon nitride film from contacting the gate polysilicon by defining a region in which the sidewall gate structure is to be formed by growing or oxidizing silicon in the SONOS structure.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020025511A KR20030087672A (en) | 2002-05-09 | 2002-05-09 | Method for producing Nonvolatile semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020025511A KR20030087672A (en) | 2002-05-09 | 2002-05-09 | Method for producing Nonvolatile semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030087672A true KR20030087672A (en) | 2003-11-15 |
Family
ID=32382133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020025511A KR20030087672A (en) | 2002-05-09 | 2002-05-09 | Method for producing Nonvolatile semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030087672A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111883536A (en) * | 2020-08-31 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Process method of embedded mirror image position SONOS memory |
-
2002
- 2002-05-09 KR KR1020020025511A patent/KR20030087672A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111883536A (en) * | 2020-08-31 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Process method of embedded mirror image position SONOS memory |
| CN111883536B (en) * | 2020-08-31 | 2023-10-24 | 上海华虹宏力半导体制造有限公司 | Technological method of embedded mirror image bit SONOS memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5879992A (en) | Method of fabricating step poly to improve program speed in split gate flash | |
| US6117733A (en) | Poly tip formation and self-align source process for split-gate flash cell | |
| US6225162B1 (en) | Step-shaped floating poly-si gate to improve gate coupling ratio for flash memory application | |
| US6358796B1 (en) | Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation | |
| US6746920B1 (en) | Fabrication method of flash memory device with L-shaped floating gate | |
| KR100771808B1 (en) | Flash memory device having sonos structure and method for fabrication thereof | |
| US6844587B2 (en) | Non-volatile memory device having improved programming and erasing characteristics and method of fabricating the same | |
| US6046086A (en) | Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash | |
| US6380030B1 (en) | Implant method for forming Si3N4 spacer | |
| US6888193B2 (en) | Split gate flash memory and formation method thereof | |
| US20050090059A1 (en) | Method for manufacturing a non-volatile memory device | |
| KR100439025B1 (en) | A method for forming a floating electrode of flash memory | |
| US6174772B1 (en) | Optimal process flow of fabricating nitride spacer without inter-poly oxide damage in split gate flash | |
| US6624028B1 (en) | Method of fabricating poly spacer gate structure | |
| KR100611079B1 (en) | Method of forming gate spacer in non-volatile memory device | |
| KR20030087672A (en) | Method for producing Nonvolatile semiconductor memory device | |
| US6869843B2 (en) | Non-volatile memory cell with dielectric spacers along sidewalls of a component stack, and method for forming same | |
| KR100559523B1 (en) | Method for manufacturing flash memory cell | |
| TW594982B (en) | Manufacturing method of flash memory | |
| US6943119B2 (en) | Flash process for stacking poly etching | |
| KR20050069114A (en) | Memory device with one poly split gate structure and fabricating method thereof | |
| KR20070014410A (en) | Method of manufacturing a non-volatile memory device | |
| KR20080002030A (en) | Method of forming a gate structure of non-volatile memory device | |
| KR100800957B1 (en) | Method for fabricating flash memory with split gate structure | |
| KR100542497B1 (en) | Method For Manufacturing Semiconductor Devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |