KR20030085237A - Power on reset circuit - Google Patents

Abstract

PURPOSE: A power on reset circuit is provided, which detects the supply of an external power supply voltage(EXTVDD) accurately without regard to an increase rate of the external power supply voltage. CONSTITUTION: A differential amplifier(120) senses a voltage difference between the first input port and the second input port, and generates an output signal. The first voltage generator supplies the first voltage to the first input port of the above differential amplifier. The second voltage generator supplies the second voltage to the second input port of the differential amplifier. The first voltage generator generates the first voltage using a power supply voltage supplied from the external, and the second voltage generator generates the second voltage using an internal power supply voltage, converted from the power supply voltage supplied from the external.

Description

Power On Reset Circuit {POWER ON RESET CIRCUIT}

TECHNICAL FIELD The present invention relates to semiconductor integrated circuits, and more particularly, to a power on reset circuit that activates a reset signal when power is supplied to a semiconductor integrated circuit.

1 is a view showing a conventional power-on reset circuit. Referring to FIG. 1, a conventional power-on reset circuit detects an input of a reference voltage generator 10 generating a reference voltage VREF and an external voltage EXTVDD and generates a detector voltage VPWRIN. ), The differential amplifier 20 which detects the difference between the reference voltage VREF and the detection voltage VPWRIN and outputs the output signal PWRSET_OUT and the reset signal in response to the output signal PWRSET_OUT of the differential amplifier 20. And a driver 40 for activating.

The reference voltage generator 10 includes resistors R1-R4, NMOS transistors N1 and N2, and a PMOS transistor P1. The resistors R1 and R2 are sequentially connected in series between a power supply voltage supplied from the outside (hereinafter, external power supply voltage EXTVDD) and a ground voltage. The resistors R3 and R4 are sequentially connected in series between the external power supply voltage EXTVDD and the drain of the NMOS transistor. The NMOS transistor N1 has a drain connected to one end of the resistor R4, a source, and a gate connected to a connection node of the resistors R3 and R4. The NMOS transistor N2 has a drain connected to the source of the NMOS transistor N1, a source connected to the ground voltage, and a gate connected to the connection node of the resistors R1 and R2. The PMOS transistor P1 has a source connected to a connection node of the resistors R3 and R4, a drain connected to a ground voltage, and a gate connected to one end of the resistor R4. The voltage of the source terminal of the PMOS transistor P1 in the reference voltage generator 10 is output as the reference voltage VREF.

The detector 30 includes resistors R5 and R6 sequentially connected in series between the external power supply voltage EXTVDD and the ground voltage. The voltage at the connection node of the resistors R5 and R6 is output as the detection voltage VPWRIN.

The differential amplifier 20 includes PMOS transistors P2 and P3 and NMOS transistors N3, N4 and N5. The PMOS transistor P2 has a source connected to the external power supply voltage EXTVDD, a drain for outputting the output signal PWRSEL_OUT, and a gate. The PMOS transistor P3 has a source connected to the external power supply voltage EXTVDD, a drain connected to the gate of the PMOS transistor P2, and a gate. The NMOS transistor N3 has a drain connected to the drain of the PMOS transistor P2, a source, and a gate connected to the reference voltage VREF from the reference voltage generator 10. The NMOS transistor N4 has a drain connected to the drain of the PMOS transistor P3, a source, and a gate connected to the detection voltage VPWRIN output from the detector 30. The NMOS transistor N5 has a source connected to the source of the NMOS transistor N3 and the source of the NMOS transistor N4, a source connected to the ground voltage, and a gate connected to the reference voltage VREF from the reference voltage generator 10. .

The driver 40 includes inverters I 1-I 7 sequentially connected in series. The output PWRSET_OUT of the differential amplifier 20 is provided as an input of the inverter I1, and the output of the inverter I7 is output as a power on reset signal PWRON. The inverters I1-I7 accept the internal power supply voltage IVC, converted from the external power supply voltage EXTVDD, as the power supply voltage.

FIG. 2 is a diagram illustrating changes of respective voltages according to the operation of the power-on reset circuit shown in FIG. 1 when the external power supply voltage EXTVDD starts to be supplied.

Referring to FIG. 2, as the level of the external power supply voltage EXTVDD increases, the reference voltage VREF from the reference voltage generator 10 and the detection voltage VPWRIN from the detector 30 also increase. The differential amplifier 20 outputs the high level output signal PWRSET_OUT when the reference voltage VREF and the detection voltage VPWRIN coincide with each other. However, as shown in FIG. 2, when the rate of increase of the external power supply voltage EXTVDD is fast (that is, when fast power up), the high level output signal PWRSET_OUT from the differential amplifier 20 is generated. The internal power supply voltage IVC is lower than the threshold voltage Vth of the transistors (not shown) configured in the inverters I1-I7 at the time of outputting. This is because the response time of the internal power supply voltage IVC is slowed by RC-loading of the internal power supply voltage generator (not shown) that generates the internal power supply voltage IVC. In FIG. 2, V1 is the voltage level of the internal power supply voltage IVC when the reference voltage VREF and the detection voltage VPWRIN are equal, and V2 is the threshold voltage Vth of the inverters I1-I7.

Therefore, in the conventional power-on reset circuit, when the increase rate of the external power supply voltage EXTVDD is fast, the power-on reset signal PWRON is not activated to a low level even when the external power supply voltage EXTVDD is normally supplied above the detection level. May occur.

Therefore, a power-on reset circuit is required that can accurately detect the start of supply of the external power supply voltage EXTVDD regardless of whether the increase rate of the external power supply voltage EXTVDD is fast or slow.

Accordingly, an object of the present invention is to solve the above-described problem, and to provide a power-on reset circuit capable of accurately detecting the start of supply of the external power supply voltage EXTVDD regardless of an increase rate of the external power supply voltage EXTVDD. have.

1 shows a conventional power on reset circuit;

FIG. 2 is a view showing changes in respective voltages according to the operation of the power-on reset circuit shown in FIG. 1 when an external power supply voltage starts to be supplied;

3 shows a configuration of a power-on reset circuit according to a preferred embodiment of the present invention; And

4A and 4B are diagrams illustrating changes in voltages according to an operation of a power-on reset circuit according to a preferred embodiment of the present invention shown in FIG. 3.

* Description of the main parts of the drawings *

110: reference voltage generator 120: differential amplifier

130: internal voltage detector 140: driver

According to a feature of the invention for achieving the above object, a power-on reset circuit of a semiconductor integrated circuit comprises: a differential amplifier for detecting a voltage difference between a first input terminal and a second input terminal and generating an output signal; And a first voltage generator for supplying a first voltage to the first input terminal of the differential amplifier and a second voltage generator for supplying a second voltage to the second input terminal of the differential amplifier. The first voltage generator generates the first voltage using a power supply voltage supplied from the outside, and the second voltage generator converts the second voltage using an internal power supply voltage, converted from the power supply voltage supplied from the outside. Occurs.

In a preferred embodiment, the second voltage generator comprises two resistors sequentially connected in series between the internal power supply voltage and the ground voltage, wherein the voltage at the connection node of the resistors is the second voltage, To the second input terminal of the differential amplifier. The second voltage generated by the second voltage generator is a reference voltage.

In this embodiment, the differential amplifier, the sense amplifier for sensing and amplifying the voltage difference between the first input terminal of the differential amplifier and the second input terminals of the differential amplifier and controls the current of the sense amplifier section And a current controller. The sensing amplifier may include a first transistor including a source, a drain connected to a power voltage provided from the outside, and a gate connected to an enable signal provided from the outside, a source connected to a drain of the first transistor, and a drain and a gate connected to each other. A third transistor comprising a second transistor comprising: a source connected to a drain of the first transistor; a drain connected to an output terminal of the differential amplifier; and a gate connected to a gate of the second transistor; a source connected to the current controller; A fourth transistor including a drain connected to an output terminal of the differential amplifier, a gate connected to an output terminal of the first voltage generator, a source connected to the current controller, a drain connected to a drain of the second amplifier, and the second voltage Occur And a fifth transistor including a gate connected to the output terminal of the device. The enable signal provided from the outside is disabled when the semiconductor integrated circuit is in an inoperative state. The current controller includes a sixth transistor including a source connected to a ground voltage, a drain connected to a source of the third transistor and a source of the fourth transistor, and a gate connected to an output terminal of the first voltage generator.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a diagram illustrating a configuration of a power-on reset circuit according to a preferred embodiment of the present invention. Referring to FIG. 3, the power on reset circuit includes a reference voltage generator 110, a differential amplifier 120, an internal voltage detector 130, and a driver 140.

The reference voltage generator 110 includes resistors R11-R14, NMOS transistors N11 and N12, and a PMOS transistor P11. The resistors R11 and R12 are sequentially connected in series between a power supply voltage supplied from the outside (hereinafter, external power supply voltage EXTVDD) and a ground voltage. The resistors R13 and R14 are sequentially connected in series between the external power supply voltage EXTVDD and the drain of the NMOS transistor. The NMOS transistor N11 has a drain, a source connected to one end of the resistor R14, and a gate connected to a connection node of the resistors R13 and R14. The NMOS transistor N12 has a drain connected to the source of the NMOS transistor N11, a source connected to the ground voltage, and a gate connected to the connection node of the resistors R11 and R12. The PMOS transistor P11 has a source connected to a connection node of the resistors R13 and R14, a drain connected to a ground voltage, and a gate connected to one end of the resistor R14. The reference voltage generator 110 having such a configuration generates the reference voltage VREF through the source terminal of the PMOS transistor P11.

The internal voltage detector 130 includes resistors R15 and R16 sequentially connected in series between the internal power supply voltage IVC and the ground voltage. The voltage of the connection node of the resistors R15 and R16 is output as the detection voltage VPWRIN. The internal power supply voltage IVC is obtained by converting the external power supply voltage EXTVDD by an internal power supply voltage generator (not shown) configured in a semiconductor integrated circuit.

The differential amplifier 120 includes a sense amplifier composed of PMOS transistors P12, P13, and P14 and NMOS transistors N13 and N14, and a current controller composed of an NMOS transistor N15. The PMOS transistor P12 has a source, a drain connected to the external power supply voltage EXTVDD, and a gate connected to the enable signal EN provided from the outside. The PMOS transistor P13 has a source connected to the drain of the PMOS transistor P12, a drain for outputting the output signal PWRSEL_OUT, and a gate. The PMOS transistor P14 has a source connected to the drain of the PMOS transistor P12, a drain and a gate connected to the gate of the PMOS transistor P13. The NMOS transistor N13 has a drain connected to the drain of the PMOS transistor P13, a source, and a gate connected to the reference voltage VREF from the reference voltage generator 110. The NMOS transistor N14 has a drain, a source connected to the drain of the PMOS transistor P14, and a gate connected to the detection voltage VPWRIN output from the internal voltage detector 130. The NMOS transistor N15 has a drain connected to the source of the NMOS transistor N13 and the source of the NMOS transistor N14, a source connected to the ground voltage, and a gate connected to the reference voltage VREF from the reference voltage generator 10. .

The driver 140 includes inverters I21, I22, I23, I24, I25 and I26, a NOR gate NOR11, and a delay unit 142. The delay unit 142 includes inverters I11-I14 sequentially connected in series. The delay unit 142 receives the enable signal EN provided from the outside and delays the enable signal EN for a predetermined time and outputs the delayed signal. The NOR gate NOR11 receives an output PWRSET_OUT of the differential amplifier 120 delayed by the inverters I21 and I22 and an enable signal EN delayed by the delay unit 142 to perform an NOR operation. Do this. The inverters I23-I26 are sequentially connected to the output terminal of the NOR gate NOR11. The output of the inverter I26 is output as the power on reset signal PWRON. The inverters I11-I14 and I21-I26 accept the internal power supply voltage IVC, converted from the external power supply voltage EXTVDD, as the power supply voltage.

The operation of the power-on reset circuit of the present invention including the configuration as described above is as follows.

The reference voltage generator 110 is designed to generate a specific level of the reference voltage VREF regardless of the change in the external power supply voltage EXTVDD or the ambient temperature. In this embodiment, the reference voltage VREF may be represented by Equation 1.

Here, Rtr is the sum of the equivalent resistance of the NMOS transistor N11 and the equivalent resistance of the NMOS transistor N12. Vgsp1 is the gate-source voltage of the PMOS transistor P11.

As can be seen in Equation 1, Vgsp1 is proportional to the reference voltage VREF. Therefore, when the reference voltage VREF is increased, the voltage Vgsp1 is also increased and the current flowing through the PMOS transistor P1 is also increased. As a result, the reference voltage VREF is reduced. On the contrary, when the reference voltage VREF is reduced, the voltage Vgsp1 is decreased to decrease the current flowing through the PMOS transistor P11. As a result, the reference voltage VREF is increased. The voltage level of the reference voltage VREF may be changed by adjusting the equivalent resistance Rtr and the bias resistor R14 of the NMOS transistors N11 and N12.

The internal voltage detector 130 divides the internal voltage IVC using the resistors R15 and R16. The detection voltage VPWRIN divided by the resistors R15 and R16 is expressed by Equation 2 below.

For example, if the internal power supply voltage IVC is 1.2V, the resistor R15 is 20 kV and the resistor R16 is 30 kV, the detection voltage VPWRIN is 1.2 * (30k / 50k) = 0.72V.

The differential amplifier 120 detects a difference between the reference voltage VREF generated by the reference voltage generator 110 and the detection voltage VPWRIN from the internal voltage detector 130 and outputs an output signal PWRSET_OUT. For example, if the reference voltage VREF is higher than the detection voltage VPWRIN, the output signal PWRSET_OUT is at a low level (ie, logic '0'), and if the reference voltage VREF is lower than or equal to the detection voltage VPWRIN, the output signal. (PWRSET_OUT) is at a high level (ie logic '1').

The enable signal EN provided from the outside is activated to a low level when the external power supply voltage EXTVDD starts to be supplied. When the enable signal EN is at the low level, the PMOS transistor P12 supplies power to the differential amplifier 120.

The PMOS transistor P12 is turned off in an inactive state in which the enable signal EN is at a high level. Therefore, the differential amplifier 120 is inoperative in the standby mode, thereby preventing unnecessary current consumption. On the other hand, the driver 140 receiving the enable signal EN receives a power-on reset signal in response to the output signal PWERSET_OUT of the differential amplifier 120 when the enable signal EN is in a low level active state. PWRON) and do not output the power-on reset signal PWRON when the enable signal EN is in a high level inactive state.

The driver 140 detects that the output signal PWERSET_OUT of the differential amplifier 120 transitions from the low level to the high level when the enable signal EN is in the low level active state, and generates a power-on reset signal PWRON. Output from high level to low level. Since the driver 140 uses the internal power supply voltage IVC as the power supply voltage, the output signal PWRSET_OUT of the differential amplifier 120 is at the external power supply voltage EXTVDD level, but the power-on reset signal output from the driver 140 ( PWRON) is the internal supply voltage level.

4A and 4B are diagrams illustrating changes in voltages according to an operation of a power-on reset circuit according to a preferred embodiment of the present invention shown in FIG. 3. First, FIG. 4A is a view showing changes in voltages according to the operation of the power-on reset circuit of the present invention when the time when the external power supply voltage EXTVDD reaches a preset level is 50 ms. In FIG. 4A, V1 represents a threshold voltage Vth of inverters provided in the driver 140, T1 represents a time when the internal power supply voltage IVC reaches the voltage V1, and V2 represents a reference voltage VREF and a detection voltage. The internal power supply voltage IVC level at the time when VPWRIN is the same and T2 represents the time until V2 is the same as the reference voltage VREF and the detection voltage VPWRIN.

The reference voltage VREF is increased to the target level until the internal power supply voltage IVC reaches V1 (T1). At this time, the internal power supply voltage IVC is gradually increased by RC loading. After T1, the internal power supply voltage IVC is sufficiently increased to drive the driver 140 until the reference voltage VREF and the detection voltage VPWRIN become equal. This is because the detection voltage VPWRIN is a voltage obtained by dividing the internal power supply voltage IVC.

At the time point T2 at which the reference voltage VREF and the detection voltage VPWRIN become equal, the level of the internal power supply voltage IVC is high enough to drive the driver 140, so that the driver is driven from the differential amplifier 120. The low level power-on reset signal PWRON is output in response to the high level output signal PWRSET_OUT.

FIG. 4B is a view showing changes in voltages according to the operation of the power-on reset circuit of the present invention when the time when the external power supply voltage EXTVDD reaches a preset level is 100 ms. In FIG. 4B, as in FIG. 4A, V1 is the threshold voltage Vth of the inverters provided in the driver 140, T1 is the time when the internal power supply voltage IVC reaches the voltage V1, and V2 is a reference voltage. The internal power supply voltage IVC level at the time when VREF and the detection voltage VPWRIN become equal, and T2 represents the time until the reference voltage VREF and the detection voltage VPWRIN become equal.

When the time when the external power supply voltage EXTVDD reaches the preset level is 100 ms, the level V2 of the internal power supply voltage IVC at the time T2 at which the reference voltage VREF and the detection voltage VPWRIN become equal to each other. Since is high enough to drive the driver 140, the driver outputs a low-level power-on reset signal (PWRON) in response to the high-level output signal (PWRSET_OUT) output from the differential amplifier (120).

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to cover all such modifications and similar constructions.

According to the present invention as described above, in the power on reset circuit of the present invention, the voltage detector 130 uses the internal power supply voltage IVC as the power supply voltage. Therefore, the internal power supply voltage IVC is increased enough to operate the driver 140 at the time when the reference voltage VREF and the detection voltage VPWRIN become equal. Therefore, the power-on reset circuit operates normally regardless of the increase rate of the external power supply voltage EXTVDD.

In addition, the differential amplifier 120 of the power-on reset circuit of the present invention further includes a PMOS transistor P12. Therefore, unnecessary current consumption can be prevented in the standby mode.

Claims (7)

In a power on reset circuit of a semiconductor integrated circuit: A differential amplifier detecting a voltage difference between the first input terminal and the second input terminal and generating an output signal; A first voltage generator for supplying a first voltage to the first input terminal of the differential amplifier; And A second voltage generator for supplying a second voltage to the second input terminal of the differential amplifier; The first voltage generator generates the first voltage using a power supply voltage supplied from the outside; And the second voltage generator generates the second voltage using an internal power supply voltage converted from a power supply voltage supplied from the outside. The method of claim 1, The second voltage generator, Two resistors sequentially connected in series between the internal power supply voltage and a ground voltage; And the voltage at the connection node of the resistors is provided as the first voltage to the first input terminal of the differential amplifier. The method of claim 1, And the first voltage generated by the first voltage generator is a reference voltage. The method of claim 1, The differential amplifier, A sense amplifier for sensing and amplifying a voltage difference between the first input terminal of the differential amplifier and the second input terminals of the differential amplifier; And And a current controller for controlling the current of the sense amplifier. The method of claim 4, wherein The detection amplifier, A first transistor including a source, a drain, and a gate connected to an enable signal provided from an external source; A second transistor comprising a source connected to the drain of the first transistor and a drain and a gate connected to each other; A third transistor comprising a source connected to the drain of the first transistor, a drain connected to the output terminal of the differential amplifier, and a gate connected to the gate of the second transistor; A fourth transistor including a source connected to the current controller, a drain connected to an output terminal of the differential amplifier, and a gate connected to an output terminal of the first voltage generator; And And a fifth transistor including a source connected to the current controller, a drain connected to the drain of the second amplifier, and a gate connected to an output terminal of the second voltage generator. The method of claim 5, And the enable signal provided from the outside is disabled when the semiconductor integrated circuit is in an inoperative state. The method of claim 4, wherein The current control unit, And a sixth transistor comprising a source connected to a ground voltage, a drain connected to a source of the third transistor and a source of the fourth transistor, and a gate connected to an output terminal of the first voltage generator. Circuit.