KR20030081442A - Scalable motion image system - Google Patents

Abstract

The present invention relates to a scalable video compression system for a digital video signal having a corresponding transmission rate. A scalable video compression system includes a decomposition module that receives a digital video signal, decomposes the digital video signal into components, and transmits the components. The decomposition module can also perform color rotation, spatial decomposition and temporary decomposition. The system of the present invention also includes a compression module that receives respective components from the decomposition module, compresses the components and sends the compressed components to a memory location. The compression module may perform sub-band wavelet compression and also includes the functions of quantization and entropy encoding.

Description

Scalable movie system {SCALABLE MOTION IMAGE SYSTEM}

Over the past half century, single-format professional and consumer video recording devices have evolved into sophisticated systems with the special features that film makers and videographers have been expecting. With the advent of high-definition digital imaging, the number of moving picture formats has increased significantly without being standardized. As digital imaging has evolved, techniques have been devised to compress digital data so that higher resolution images, and thus more information, is stored in the same memory space as uncompressed lower resolution images. In order to provide higher resolution image storage, manufacturers of recording and storage devices have added compression techniques to their systems. In general, current compression techniques are based on the spatial coding of each picture of a video sequence using Discrete Cosine Transform (DCT). In this process, spatial coding is essentially block-based. Such block-based systems are not easy to scale due to the fact that the compressed data size also increases in proportion to increasing resolution. The block transformation system cannot find correlation on the block boundary or at frequencies lower than the block size. Due to the low frequency bias of conventional power distribution, more and more information cannot be block converted as the image size increases. Thus, the block conversion method for spatial image compression produces a data size of a given quality proportional to the image size. In addition, as the resolution increases, the tilting effect due to block-based encoding is greater, resulting in substantial picture loss, including artifacts and discontinuities. Because of these constraints, manufacturers have designed their compression systems to have a limited range of resolutions. For each resolution desired in the film industry, manufacturers have been required to develop resolution specific applications to address these shortcomings and to compensate for spatial coding problems. As a result, development of a scalable image representation system for moving picture streams with different throughputs has not been achieved.

The present invention relates to digital moving images, and more particularly, to an architecture for scaling a digital moving image system into various digital moving image formats.

The foregoing features of the present invention will be more readily understood from the following detailed description with reference to the accompanying drawings.

1 is a block diagram illustrating one embodiment of the present invention for a scalable video system.

2 is a block diagram illustrating a number of digital video system chips coupled together to yield a scalable digital video system.

2A is a flow diagram illustrating the flow of a digital video stream through a digital video system.

2B illustrates one module grouping.

3 is a block diagram illustrating various modules that may be found on a digital video chip.

4 is a block diagram illustrating a synchronous communication scheme between a DMR and a CODEC.

5 is a block diagram of a global control module capable of providing a synchronization signal to each DMR and CODEC in a single chip and providing a synchronization signal to all chips in the array through a bus interface module (not shown) when connected to the array.

6 is a block diagram showing an example of a digital video system chip before configuration.

7A and 7B are block diagrams showing functional components of the digital video system chip of FIG. 6 after construction.

8 is a block diagram illustrating devices and buses found within a CODEC.

9 is a block diagram showing an example of spatial polyphase processing;

Fig. 10 is a block diagram showing an example of spatial sub-band division using DMR and CODEC.

A scalable video compression system of a digital video signal having an associated transmission rate is disclosed. A scalable video compression system includes a decomposition module that receives a digital video signal, decomposes the digital video signal into component parts, and transmits the components. The decomposition module can also perform color rotation, spatial decomposition and time decomposition. The system further includes a compression module that receives each of the components from the decomposition module, compresses the components and sends the compressed components to a memory location. The compression module may perform sub-band wavelet compression and may include functionality for quantization and entropy encoding.

Each disassembly module may include one or more disassembly units, which may be ASIC chips. Likewise, each compression module may include one or more compression units, which may be CODEC ASIC chips.

The system can compress the input digital video stream in real time at the transmission rate. The system may further include a programmable module for routing the decomposed digital video signal between the decomposition module and the compression module. The programmable module may be a field programmable gate array that acts like a router. In this embodiment the disassembly module has one or more disassembly units, and the compression module has one or more compression units.

In other embodiments, the field gate programmable array can be reprogrammed. In another embodiment, the decomposition units are arranged in parallel, each unit receiving a portion of the input digital video signal stream, such that the total throughput of the decomposition unit is greater than the transmission speed of the digital video stream. In certain embodiments the decomposition module is configured to decompose the digital video stream by color, frame or field. The disassembly module may also perform color decorrelation. Both the decomposition module and the compression module are reprogrammable and have a memory for receiving coefficient values used for encoding and filtering. Those skilled in the art will appreciate that the system can equally be used to decompress a compressed digital video stream. Each module can receive a new set of coefficients and thus an invert filter can be implemented.

Justice. The following terms used in this specification and the accompanying drawings have the following meanings unless otherwise required by context.

The pixel is an image element and is typically the minimum controllable color element on the display device. Pixels are associated with color information in a particular color space. For example, a digital image may have a pixel resolution of 640 × 480 in RGB (Red, Green, Blue) color space. This image has 640 pixels in 480 rows, each pixel having an associated red color value, green color value, and blue color value. A moving picture stream may consist of a stream of digital data that may be divided into fields or frames representing moving pictures, where a frame is a complete digital data picture displayed on a display device for one period. Frames of moving pictures can be broken down into fields. Fields are usually displayed as odd or even, meaning that all odd lines or all even lines of the picture are displayed for a given period. The indication of odd and even fields for other periods is known in the art as interlacing. Those skilled in the art will appreciate that a frame or pair of fields represents a complete picture. The term "picture" as used herein refers to both field and frame. In addition, the term "digital signal processing" as used herein means processing the digital data stream in an organized manner for alteration and / or segmentation of the data stream.

1 is a block diagram illustrating one embodiment of the present invention for a scalable video system 10. The system includes a digital video system chip 15 that receives a digital video stream as input 16. The digital video system chip 15 is preferably implemented as an application specific integrated circuit (ASIC). A processor 17 controlling the digital video system chip provides instructions to the digital video system chip, which includes routing, compression level setting, encoding including spatial and temporal encoding, color decorrelation, color space conversion, interlacing. And various instructions such as encryption. The digital video system chip 15 compresses the digital video stream 16, which generates the digital data stream 18 in approximately real time, and transmits the information to a memory for subsequent retrieval. A request for a digital video system chip to retrieve a digital data stream and invert the process to output a digital video stream can be made by the processor. From the output, the digital video stream passes through the digital display device 20.

FIG. 2 is a block diagram illustrating a number of digital video system chips 15 coupled together to create a scalable digital video system that can accommodate various digital video streams, each having an associated resolution and associated throughput. For example, a digital video stream can have a resolution of 1600 × 1200 pixels per video, each with pixels represented by 24 bits of information (8 bits red, 8 bits green, 8 bits blue), 30 frames per second. Can have a speed of Such video streams require devices capable of throughput of 1.38 gigabit / second peak rate. The system can accommodate a variety of resolutions including, for example, 640 × 480, 1280 × 768, and 4080 × 2040 through various configurations.

The method of doing this is shown in FIG. 2A. First, a digital video stream is received in the system. Depending on the throughput, the stream is separated at a definable point, such as a frame or line point in the picture, and distributed to one of the plurality of chips such that the chip provides a buffer to accommodate the throughput of the digital video stream. The chips then perform decomposition of the picture stream by color components or fields, respectively. The chips will then decorrelate the digital picture stream based on the decomposition (step 202A). For example, color components may be decorrelated to separate luminance or each picture (field / frame) of the stream may be converted to a subframe code. The system then performs incubation of the stream through quantization and entropy encoding to further compress the amount of data representing the digital moving picture (step 203A). The steps will be described further below.

If the components on the digital video system chip can provide such peak throughput individually, the chips are progressively connected in parallel and / or serially to buffer the digital video stream, then decompose the digital video stream into picture components and other video systems. Redistributing the components between the chips can provide the required throughput. This decomposition can be accomplished with a register input buffer. For example, if the required throughput was twice the capacity of a digital video chip, two registers with the word length of the video stream would be from the register at half the frequency or two word lengths per cycle, although the data would be placed in the register at the appropriate frequency. Provided to be read. In addition, multiple digital video system chips may be linked to form such a buffer. Assuming a switch capable of operating at the speed of a digital video stream, each digital video system chip can receive and buffer a portion of the stream. For example, suppose a digital video stream is composed of 4000 x 4000 pixel monochrome images at 30 frames per second. The required throughput is 480 million components per second. If the digital video system chip only has a maximum throughput of 60 million components per second, the system can be configured so that a switch operating at 480 million components per second switches sequentially between any of the eight chips. The digital video system chips then each act as a buffer. As a result, the digital video stream can then be processed in-chip. For example, frame ordering may be changed or the system may add or remove frames of pixels, fields, or data.

After buffering, the digital video stream is decomposed. For example, a digital moving picture system chip can provide color separation such that each moving picture is separated into its respective color component, such as an RGB or YUV color component. During decomposition, the signal can also be decorrelated. The color can be decorrelated by coordinate rotation to separate the luminance information from the color information. Other color decomposition and decorrelation are also possible. For example, a 36 component Earth Resource representation can be decorrelated and decomposed, with each component representing a frequency band, thus correlating both spatial and color information. In general, the components share common luminance information and also have a significant correlation to approximate the color component. In this case, wavelet transform can be used to decorrelate the components.

In many digital picture stream formats, color information is mixed with spatial and frequency information, for example a color masked imager, in which only one color component is sampled at each pixel location. Color decorrelation requires both spatial and frequency decorrelation in this situation. For example, suppose a 4000 × 2000 pixel camera uses three color masks (blue, green, green, red in a 2 × 2 repeating grid) and operates at frame rates up to 72 Hz. The camera will then deliver up to 576 million single-component pixels per second. Assuming a system chip inputs 600 million components per second and processes 300 million components, two system chips can be used as a multiphase frame buffer and a four phase convolver can pass through the data at 300 mega components per second. Can be. Each phase of the convolver corresponds to one of the phases of the color mask, and as outputs four independent components: two-dimensional half-band low frequency luminance component, two-dimensional half-band high frequency diagonal luminance component, two-dimensional half-band Cb color difference Components, and two-dimensional half-band Cr color difference components. The information bandwidth of the process is preserved, four independent equal bandwidth components are created and the color space is decorrelated. The two-dimensional convolver described herein incorporates interpolation, color space decorrelation, bandlimiting, and subband decorrelation into a single multiphase convolution. Those skilled in the art should understand that other decompositions are possible. Due to the modularity of the digital video system, various types of decorrelation and decomposition are possible. As will be described further below, each element of the chip is externally controlled and configurable. For example, a separate element exists in the chip that performs color decomposition, spatial coding, and temporal coding, and each transformation therein is designed to be a multi-tap filter defined by its coefficient value. The external processor can input different coefficient values for a particular device, depending on the application. In addition, the external processor can select the relevant specific device to be used for processing. For example, a digital video system chip may be used alone for buffering and color decomposition, which is used only for spatial encoding or used for spatial and temporal encoding. This modular approach in the chip is provided in part by the bus to which each device is coupled.

Motion pictures can also be decomposed by dividing the frame into fields. The frame or field may be further decomposed based on the frequency structure of the image, such that, for example, low, medium, and high frequency components of the image are grouped together. Those skilled in the art should understand that frequency segmentation is also possible. In addition, the referenced decomposition does not exist in space, eliminating discontinuities in the reconstructed digital video stream upon decompression, which is prevalent in blocks based on compression techniques. As described, all throughputs can be increased by a factor N by parallel processing as a result of the decorrelation of the digital video stream. For example, N is 27: 1 days in the following example where an image is divided into fields (2: 1 gain) and then divided into color component (3: 1) gain and then divided into frequency component (3: 1) gain. will be. Therefore, the total increase in throughput is 27: 1 so that the final processing where actual compression and encoding occurs can be achieved at a rate that is 1/27 of the speed of the input video stream. Therefore, the throughput related to the resolution of the image can be scaled. In the example, the video chip has an I / O capacity of 1.3 Gcomponents / s for simple interlaced resolution, so that a pair of video chips can be connected at the output port of the first video chip, and color component decomposition Can be performed on a second moving picture chip pair in which the total throughput is not exceeded 650 Mbits / sec. Another decomposition can be accomplished on a frame-by-frame basis, commonly referred to in the art as polyphase.

The digital video stream itself is input to the video chip through multiple channels. For example, a quad-HD signal may be segmented through eight channels. In this configuration, eight separate digital video chips can be employed to compress the digital video strips for each channel.

Each moving picture has an input / output (I / O) port for providing data between chips or a data communication port for providing messages between pins and chips. It is to be understood that a processor controls an array of chips that provides instructions regarding digital signal processing operations to be performed on digital video data for each chip of the array of chips. It should also be understood that memory input / output ports are provided on each chip that communicates memory locations and memory coordinators.

In one embodiment, each digital video system chip includes an input / output port, with a number of modules including a disassembly module 25, a field gate programmable array (FPGA) 30, and a compression module 35. . 2B shows a group of modules. In a practical embodiment, several such groups may be included on a single chip. As such, the FPGA allows the chip to be programmed to form a coupling between the compression module and the decomposition module.

For example, an input moving picture data stream may be decomposed within a decomposition module by dividing each frame of the moving picture stream into respective color components. An FPGA, which may be a dynamically reprogrammable FPGA, may be programmed as a multiplexer / router that receives three moving picture information streams (in this example, one each for red, green, and blue) and passes that information to a compression module. Can be. Although a field gate programmable array is described, other signal / data dividers can also be used. The distributor may distribute the signal on a peer-to-peer basis using token passing, may be centrally controlled to distribute the signal separately, and the module may process The entire moving picture input signal may be provided to each module masking a portion that is not supposed to be estimated. The compression module, which consists of a plurality of compression units, each of which can compress the incoming stream, compresses the stream and then outputs the compressed data to the memory. The compression module of the preferred embodiment uses wavelet compression that uses subband coding for the stream in both space and time. In addition, the compression module is configured to provide a guaranteed level of signal quality for varying degrees of compression based on control signals transmitted from the processor to the compression module. As such, the compression module generates a compressed signal that, upon decomposition, maintains the set resolution across all frequencies for the picture sequence in the digital video stream.

When n is an independent component velocity, a Roof [n / m] system chip is used when the component processing speed of system chip m is less than n. Each system chip receives all Roof [n / m] pixels or Roof [n / m] frames. Normally, the choice is determined by the convenience of I / O buffering. In the case of pixel polyphase where Roof [n / m] is not a multiple of the line length of the video image being processed, line padding is used to maintain vertical correlation. In the case of multiple phases by component multiplexing, the vertical correlation is preserved, and in order to cause two or more orthogonal subdivisions of the vertical components, the subband transform can be applied independently to the columns of the picture of each part. In the case of multi-phase by frame multiplexing, both vertical and horizontal correlations are maintained, so that two-dimensional subband transformation can be applied to the frame to generate two or more orthogonal subdivisions of the two-dimensional information. The system chip is designed to support the same peak speeds at the input and output ports. The Roof [n / m] process outputs a non-polyphase subband representation of the input signal in a transposed polyphase fashion, where more components are present, with each independent component at a reduced speed. have.

3 shows various modules that can be found on a digital moving picture chip 15 that includes a disassembly module 300, which may include one or more disassembly units 305. These units allow for color compensation, color space rotation, color decomposition, spatial and temporal conversion, format conversion, and other moving picture digital signal processing functions. This disassembly unit 305 may also be referred to as a digital mastering refomatter ("DMR"). In addition, the DMR 305 typically includes one- or two-tap filters, bit scaling through color rotation, interpolation, and 1/10 rejection, 3: 2 pulldown, and line doubling. It has a "smart" I / O port that provides simplified space, time and color decorrelation. The smart I / O port is preferably bidirectional and has a dedicated processor for receiving a sequence of instructions. For example, the input port and the output port operate independently of each other such that the input port performs temporal decorrelation of the color components while the output port performs interlaced shuffling of the lines of each picture. It is configured to. Commands for an I / O port may be passed as META data in a digital video stream, or may be sent to an I / O port processor through a system processor, where the system processor is not part of the digital video chip and is a chip function. It is a processor that provides a command to control the chip. In addition, the I / O port can operate as a standard I / O port and deliver digital data to a digital signal processor dedicated to internal applications that perform upper filtering. Upon completion of the specified sync time interval, under normal circumstances, the I / O processor may enter a system clock such that the I / O port preferably delivers the complete frame of processed data to subsequent modules and receives data representing another frame. Are synchronized. Even if the sync time interval is complete and the data in the module has not been fully processed, the output port will still clear semi-processed data and the input port will receive the subsequent data set. For example, if the throughput of a digital video stream exceeds the throughput of a single DMR 305 or compression module, the DMR 305 can be used in parallel and employed as a buffer. In this configuration, when the switch / signal partitioner inputs digital data into each DMR, the DMR may perform other decomposition and / or decorrelation.

Compression module 350 includes one or more compression / decompression units (“CODECs”) 355. CODEC 355 provides encoding and decoding functions (wavelet transform, quantization / dequantization, and entropy encoder / decoder), as well as temporal transform (time / frequency) of the signal, as well as spatial wavelet transform (spatial / Frequency domain).

In certain embodiments, the CODEC includes an interlace process and the ability to perform encryption. In addition, the CODEC can perform simplified decorrelation using simple filters, such as one-tap or two-tap filters, and also operate in the same manner as the smart I / O ports described above with respect to DMR. O has port Both the DMR and CODEC have a storage location for receiving a digital moving picture stream or data from another DMR or CODEC, and a location for storing data after the process is performed and before being transmitted to the DMR or CODEC. In the preferred embodiment, the input and output ports have the same bandwidth for both the DMR and CODEC, but do not necessarily have to be the same bandwidth to support the modularity scheme. For example, to support multiphase buffering, the DMR preferably has a higher I / O rate than the CODEC. Since each CODEC has the same bandwidth at the input port and the output port, the CODECs can easily be connected through a common bus pin and can be controlled with a common clock.

In addition, the CODEC may be configured to operate in a quality priority mode as described in US patent application Ser. No. 09 / 498,924, the entire contents of which are incorporated herein by reference. In quality priority, each frequency band of a frame of video that is decorrelated using subband wavelet transform may have a quantization level that is mapped to a sampling theory curve within the information plane. These curves have axes of resolution and frequency, and each time one octave decreases from the Nyquist frequency, an additional 1.0 bit is needed to represent the two-dimensional picture. Thus, the resolution for the video stream, such as represented by the Nyquist frequency, is preserved at all frequencies. Based on the sampling theory, every one octave reduction requires an additional 1/2 bit for resolution per dimension. Thus, to represent the same resolution as at Nyquist at lower frequencies, more information bits are required. As such, the peak rate for quantization can approach the data rate within the sample region, and the input and output ports of the CODEC should have approximately the same throughput.

For high-resolution images, such as homomorphic filtering and grain reduction, can be broken down into smaller units that are compatible with the throughput of the CODEC and can be broken down into smaller units that do not affect the quality of the image. The digital signal process of can be done. Quantization can be changed based on, for example, human perception, sensor resolution, and device characteristics.

Thus, the system is preferably configured in a multiplexed form that employs modules with a fixed throughput to accommodate varying image sizes. Since compression is based on full image conversion with local support, the system can achieve this without loss due to horizon effects or block artifacts. In addition, the system may perform a pyramid transformation so that very low frequency components can be further subband coded.

Those skilled in the art should appreciate that various configurations of CODECs and DMRs can be placed on a single moving picture chip. For example, the chip may consist of multiplexed CODECs, multiplexed DMRs, or a combination of DMRs and CODECs. In addition, the digital video chip may be a single CODEC or a single DMR. The digital video system chip can provide control instructions that allow the chip to perform N component color coding, variable frame rate coding (e.g., 30 frames per second or 70 frames per second), and high resolution coding using multiple CODECs. have.

3 also illustrates a coupling between the DMR 305 and the compression module 350 that transmits the decomposed DMR information to each of the plurality of CODECs 335 for parallel processing. It will be appreciated that the FPGA / signal divider is not shown in this figure. Once the FPGA is programmed, the FPGA acts as a signal divider by providing a signal path between the appropriate decomposition and compression modules.

4 is a block diagram illustrating a synchronous communication method between the DMR 400 and the CODEC 410. Messaging between the two units is provided by a signaling channel. The DMR 400 informs the CODEC 410 that it wants to write information to the CODEC with the READY command 420. The DMR then waits for the CODEC to respond to the WRITE command 430. When the WRITE command 430 is received, the DMR transfers the next data unit for the CODEC from the DMR output buffer to the CODEC input buffer. The CODEC may also respond with a NOT READY 440, after which the DMR holds the data in the DMR output buffer, waiting for the CODEC to respond to the READY signal 420. In a preferred implementation, if the input buffer of the CODEC is full of 32 words, the CODEC will send a NOT READY response 440. If NOT READY 440 is received by the DMR, the DMR will stop processing the current data unit. Handshaking between these modules is standardized so that each disassembly module and each extrusion module can understand the signal.

5 provides a synchronization signal 501 to each DMR 510 and CODEC 520 within a single chip, and the synchronization signal to all chips in the array through a bus interface module (not shown) when connected within the array. Shows a block diagram of a global control module 500 that can provide. In the preferred embodiment, the synchronization signal occurs at the speed of the moving picture frame but may occur at the speed of the image information unit. For example, if an input digital video stream is taken at a rate of 24 frames per second, a sync signal will occur every 1/24 second. Thus, in each sync signal, information is transferred between the modules, so that the DMR delivers a complete frame of the digital video in decorrelation to the compression module of the CODEC. Similarly, new digital moving picture frames are transferred to the DMR. The global sync signal takes precedence over all other signals, including the READ and WRITE instructions passed between the DMR and CODEC. Therefore, the READ and WRITE commands are classified into internal frame sections. Since the synchronization signal transmits the unit (frame in the preferred embodiment) of the image information, the frame is kept in synchronization. If the CODEC takes longer than the period between synchronization signals to process the picture information unit, the unit is discarded and all partially processed data is erased in the DMR or CODEC. Global synchronization signals are carried along the global control bus shared together by all DMRs or CODECs on the chip or in an array. The global control further includes a global direction signal. The global direction signal indicates to the I / O port of the DMR and CODEC whether the port should transmit or receive data. By providing a synchronous signal timing scheme, the throughput of the system is maintained, and therefore the scalable system can operate synchronously to recover from external errors such as soft errors or faulty data such as transient noise inside any component. .

6 is a block diagram illustrating an example of the digital video system chip 600. The chip is provided with a DMR 630A-B pair coupled to the first DMR 610, the FPGA 620, and the second FPGA 640A-B, respectively. The FPGA is in turn coupled to four CODECs (650A-H). As mentioned above, the FPGA can be programmed based on the desired throughput. For example, in FIG. 7A, the first FPGA 620 is set to be coupled between the first DMR 610 and the second DMR 630A. The second FPGA 630A is coupled to the FPGA 640A which is coupled to three CODECs 650A, 650B and 650C. This configuration can be used to divide the incoming digital picture stream into frames in the first DMR and then to correlate the color components for each frame in the second DMR. In this implementation, the CODEC compresses data for monochrome components in each moving picture frame. FIG. 7B is another configuration of the digital video system chip of FIG. 6. In the configuration of FIG. 7B, the first FPGA 620 is set to couple to each of the two DMRs 630A, 630B at the output. Each DMR 630A, 630B then sends data to a single CODEC 650A, E. This configuration is first used to interlace moving picture frames, so that the second DMR receives odd or even fields. The second DMR may then perform color correction or color space conversion for the interlaced digital video frame, which data is passed to a single CODEC that compresses and encodes the color correction interlaced digital video.

8 is a block diagram illustrating devices and buses found within CODEC 800. The DMR element may be the same as the CODEC element. Preferably, the DMR has a faster data rate for receiving higher component / second digital video streams, and more memory for buffering the received data of the digital video streams. The DMR may simply be configured to implement color space and spatial decomposition, so that the DMR has a data I / O port and a picture I / O port, in which the I / O port contains a programmable filter for decomposition. Combined.

CODEC 800 is coupled to a global control bus 810 in control communication with each device. The device may be a data I / O port 820, an encryption device 830, an encoder 840, a space conversion device 850, a time conversion device 860, an interlace processing device 870, and an image I / O port 880. ). All these devices are coupled through a common multiplexer (mux) 890 that is coupled to memory 895. In a preferred embodiment, the memory is a double data rate (DDR) memory. Each device operates independently from all the others. The global control module sends a command signal to the device to implement digital signal processing for the data stream. For example, the global control module only communicates with the spatial transform elements, so only spatial changes are implemented on the digital data stream. All other devices will bypass this configuration. If more than one device is implemented, the system operates in the following manner. The data stream is input to the CODEC through the data I / O port or the picture I / O port. The data stream is then delivered to a buffer and then to the mux. From the mux, data is transferred to the allocated memory location or segment of the location. The next device, for example an encryption device, requests data stored at a memory location that is sent to the encryption device via a multiplexer. The encryption element can then implement any of many encryption techniques. Once the daily data is processed, the data is delivered to a buffer, which is then passed back into memory and through a multiplexer to a particular memory location / segment. This processing continues for all devices that receive control commands and operate on the digital data stream. It should be noted that each device is provided with an address space of memory to read, based on an initial command sent from the system processor to the global control processor and then with modulation in the moving picture chip. As a result, the digital data stream is read from the memory and passed through the picture I / O port or data port. Data transmission from the port occurs upon reception by the CODEC of the synchronization signal or using a write command.

The elements in the CODEC are described in more detail below. The picture I / O port is a bidirectional sample port. The port transmits and receives data in synchronization with a synchronization signal. Interlaced processing elements provide a number of methods known to those skilled in the art for preprocessing frames of digital video streams. Preprocessing correlates spatial vertical redundancy with time field versus field redundancy. The time conversion element provides a 9-tap filter that provides for wavelet conversion over a space frame. The filter can be configured to implement a convolution in which the temporal filter window slides across multiple frames. The temporal transformation may include inductive computations allowed for multi-band temporal wavelet transforms, space-time combinations, and noise reduction filters. Although the time conversion element may be implemented in a hardware format as a digital signal processing integrated circuit, the element may be configured to receive and store a constant value from metadata in the digital video stream or for a filter by a system processor. Spatial transform elements, such as temporal transform elements, may be implemented as digital signal processors that correlate memory locations to downloadable constant values. The spatial transformation in the preferred embodiment is a symmetric two dimensional convolver. The convolver has N tap positions, where each tap has an L-factor that is cycled by sample / word basis (sample or word can be defined as a grouping of bits). Spatial transformations may be performed inductively on input image data to implement multi-band spatial wavelet transformations, or may be used for spatial filtering such as bandpass or noise reduction. The entropy encoder / decoder element temporarily implements encryption over the entire picture or over multiple correlated time blocks. Entropy encoders use adaptive encoders that represent data that occurs frequently as the minimum bit length symbol and less frequent values as the longer bit length symbol. Zero long run lengths are represented as single-bit symbols representing multiple zero values within a few bytes of information. For more information on entropy encoders, see US Pat. No. 6,298,160, which is assigned to the same assignee and is hereby incorporated by reference in its entirety. The CODEC also includes an encryptor element that performs both encryption and decryption of the stream. CODEC may be implemented using an improved encryption standard (AES) or other encryption technology.

9 is provided a block diagram illustrating an example of spatial polyphase processing. In this embodiment, the average data rate of the digital video stream is 266 MHz (4.23 giga-component / second). Each CODEC 920 can be processed at 66 MHz, so the moving picture stream is polyphased because the required throughput is greater than that of the CODEC. The digital video stream is split into spatial segments by passing it to a DMR 910 that identifies each frame. To accommodate the 266MHz bandwidth of the picture stream, this process is performed through the smart I / O port without using the digital signal processing elements inside the DMR. The smart I / O port of the exemplary DMR may be performed at a frequency rate of 533 MHz, while the digital signal processing element is performed at 133 MHz, the maximum rate. When each frame is divided, the smart I / O port of the DMR transfers the image data stream divided into spaces to the frame buffer. The CODEC sends a signal to the DMR that it is ready to retrieve data as described above with respect to FIG. 4. The DMR retrieves the image data frame and passes the frame to the first CODEC through the smart I / O port. The process for each of the four CODECs continues such that the second CODEC retrieves the second frame, the third CODEC retrieves the third frame and the fourth CODEC retrieves the fourth frame. The process returns to the first CODEC until the entire stream has been processed and passed from the CODEC to the memory location. In such an embodiment, the CODEC may perform wavelet coding, compression of frames, and other video signal processing techniques (which define video signal processing).

FIG. 10 is a block diagram illustrating an embodiment of spatial sub-band division using DMR 1010 and CODEC 1020. In this embodiment a quad HD picture stream (3840 × 2160 × 30 frames / sec or 248 MHz) is processed. The input video stream is divided into color components by frames at the beginning of the configuration shown. The color component of the frame is in Y, Cb, Cr format 1030. The DMR 1110 performs spatial processing on the frames of the picture stream and passes each frequency band to the appropriate CODEC for temporal processing. Since the chrominance components are only half-bands (Cb, Cr), each component is processed using only one DMR and two CODECs. The luminance component (Y) is first multiplexed (1040) via a fast multiplexer operating at 248 MHz, the even components are passed to the first DMR 1110A and the odd components are passed to the second DMR 1110B. Delivered. Next, the DMR uses a two-dimensional convolver that outputs four frequency components L, H, V, and D (low, high, vertical, and diagonal). DMR performs this task at a rate of 64 MHz for the average frame. DMR (1010C, 1010D) processing Cb and Cr can also be used to obtain two-dimensional convolvers (two-dimensional convolvers for Y components) to obtain frequency divisions of LH (low high) and VD (vertical diagonal) for each component. Filter coefficients different from the filter coefficients). Next, CODEC 1020 processes the components of the frame to be divided into spaces. In this embodiment, the CODEC performs temporal transformation for multiple frames. (Additional initiation of the temporal transformation process is required.) It should be understood that the DMR and CODEC are fully symmetric and can be used to encode and decode the picture. .

Although the above technique has been described for compression, it should be understood by those skilled in the art that digital moving picture system chips can be used for the decomposition process. This function is possible because the elements inside both the DMR and CODEC can be changed by receiving different coefficient values and in the case of the decomposition process, can receive inverse coefficients.

In alternative embodiments, the disclosed scalable digital moving picture compression system and method may be implemented as a computer program product using a computer system as described above. This implementation may be secured on a tangible medium, such as a computer readable medium (eg, diskette, CD-ROM, ROM, or fixed disk), or through another interface device, such as a communication adapter connected to the network for a modem or medium. It may include a series of computer instructions that can be transmitted to a computer system. The medium may be a tangible medium (eg, optical or analog communication line) or a medium running on wireless technology (eg, microwave, infrared or other transmission technology). The series of computer instructions implements all or part of the functionality described herein above for the system. Those skilled in the art should understand that such computer instructions may be written in multiple programming languages using multiple computer structures or operating systems. In addition, such instructions may be stored in any memory device, such as a semiconductor, magnetic, optical, or other memory device, and may be transmitted using any communication technology, such as optical, infrared, microwave, or other transmission technology. Such computer program products may be distributed as removable media with printed or electronic documents (e.g., packaged software), preloaded on a computer system (e.g., on a system ROM or fixed disk), or on a server Or from an electronic billboard on the network (eg, the Internet or the World Wide Web). Of course, some embodiments of the invention may be practiced as a combination of both software (eg, computer program product) and hardware. Another embodiment of the invention is implemented entirely as hardware or completely as software (eg, a computer program product).

While various embodiments of the invention have been disclosed, it should be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the scope of the invention. Such and other obvious modifications are intended to be protected by the appended claims.

Claims (19)

In a scalable video compression system of a digital video signal having an associated transmission rate, A decomposition module which receives the digital video signal at the transmission rate, decomposes the digital video signal into components and transmits the components at the transmission rate; And A compression module that receives each of the components from the decomposition module, compresses the components and sends the compressed components to a memory location Scalable video compression system comprising a. The scalable moving picture compression system of claim 1, wherein the decomposition module includes one or more decomposition units. 2. The scalable video compression system as claimed in claim 1, wherein the digital video signal is compressed at the transmission rate. 2. The scalable video compression system of claim 1, further comprising a programmable module for routing the decomposed digital video signal between the decomposition module and the compression module. 5. The scalable moving picture compression system of claim 4, wherein the programmable module is a field programmable gate array. 6. The scalable video compression system of claim 5, wherein the field programmable gate array is reprogrammable. The scalable moving picture compression system of claim 1, wherein the compression module includes one or more compression units. 8. A scalable video compression system according to claim 7, wherein a throughput of the compression unit multiplied by the number of compression units is equal to or greater than a transmission speed of the digital video signal. 8. A scalable moving picture compression system as claimed in claim 7, wherein each compression unit operates in parallel. The scalable moving picture compression system of claim 1, wherein the decomposition module includes one or more decomposition units. The scalable moving picture compression system of claim 1, wherein each decomposition unit operates in parallel. The scalable moving picture compression system of claim 1, wherein the decomposition module performs color decorrelation. The scalable moving picture compression system of claim 1, wherein the decomposition module performs color rotation. The scalable moving picture compression system of claim 1, wherein the decomposition module performs time decomposition. The scalable moving picture compression system of claim 1, wherein the decomposition module performs spatial decomposition. The scalable video compression system of claim 1, wherein the compression module uses sub-band coding. 14. The scalable video compression system of claim 13, wherein the sub-band coding uses wavelets. The scalable moving picture compression system of claim 1, wherein the spatial decomposition is spatial polyphase decomposition. A scalable system for performing video compression of a digital video input signal having a corresponding transmission rate, A plurality of compression blocks each comprising a decomposition module and a compression module; A signal divider coupled to the compression block to divide the digital video input signal into a plurality of segments and provide each component of the input signal to a respective compression unit-the decomposition module decomposes one segment into components Transmitting components-; And A compression module that receives components from a corresponding decomposition module, compresses the components and sends the compressed components to a memory location Scalable system comprising a.