KR20030080958A - Global elimination algorithm for motion estimation and the hardware architecture thereof - Google Patents

Abstract

The present invention relates to a global erasing algorithm for motion estimation and its hardware structure, which makes it possible to effectively cancel a branch in a calculation data flow, thereby making the calculation data flow smooth and more suitable for hardware implementation. . Since the processing time for each motion vector is fixed, it is not necessary to perform preliminary prediction. The erase rate of the search place does not change with time, and thus the erase rate can be increased. The global cancellation algorithm can produce a search result with the same high accuracy as the entire search block matching algorithm. The maximum value of the signal-to-noise ratio of the global cancellation algorithm is sometimes greater than the maximum value of the entire search block matching algorithm. Compared with other hardware structures based on the full search block matching algorithm, the hardware structure of the present invention can provide the best computational power to each logic gate, while the power consumption of the logic gate is minimal when the motion vector throughput is the same. .

Description

GLOBAL ELIMINATION ALGORITHM FOR MOTION ESTIMATION AND THE HARDWARE ARCHITECTURE THEREOF

The present invention relates to a block-matched motion prediction algorithm for use in a multimedia video compression system, and more particularly for high efficiency motion prediction that can reduce the temporal redundancy inherent in video sequences to achieve the purpose of video compression. A global erase algorithm and its hardware structure.

In the rapid advancement in video compression technology developed by the high-technology industry, the amount of computational data flow and transmission quality in video sequence transmission has become increasingly important. As far as the video sequence is concerned, it is highly desirable to reduce the storage space occupied by the video sequence, since the required storage space is very large. As a result, the video sequence has to be compressed, and therefore, it is necessary to use video compression techniques as a basic element in the image processing system. Video compression techniques generally involve inherent reductions in redundancy within video sequences to achieve the purpose of video compression. Motion prediction algorithms are known as video compression techniques based on the need to reduce inherent redundancy in video sequences.

The motion prediction algorithm generally describes a method for finding candidate blocks in a reference frame that best matches the current block in the current frame. Of the many motion prediction algorithms, one of the most widely used algorithms is called a full-search block matching algorithm. The full search block matching algorithm has a large amount of operations that cannot be handled by current general purpose microprocessors for real time applications. Due to the regular operational data flow in the entire search block matching algorithm, various parallel or pipelined hardware structures address. Unfortunately, among these structures, the computational speed of the 1-D array structure is too slow in terms of the required clock cycles. Thus, for large frames and a wide range of search applications, the operating frequency of the 1-D array structure must be greatly increased. Although the computational speed of the 2-D array structure is faster than the computational speed of the 1-D array structure in terms of the required clock cycles, the amount of logic gates is too large and therefore the cost of the array structure is excessive. Although the tree structure exhibits good performance in terms of computational speed and area, this tree structure requires a larger memory bit width, thus reducing flexibility.

In order to reduce the bulk operation of the full search block matching algorithm, a successive elimination algorithm (sea) is proposed which can achieve the same result as the full search block matching algorithm. The continuous cancellation algorithm provides a better computational effect than other fast search algorithms that perform block search at the cost of maximum signal-to-noise ratio (PSNR), for example, three-step search, diamond search or 2-D log search. 1 illustrates the operational flow of a continuous cancellation algorithm. First, in step S10, the successive erasing algorithm value [sea (m, n)] of each search position is calculated. Subsequently, in step S12, the continuous erasure algorithm value sea (m, n) is compared with the minimum value SAD _min of the sum of the absolute differences of the differences to obtain the continuous erase algorithm value sea (m, n). It is determined whether the difference is greater than the minimum SAD _min of the absolute value of the difference. If sea (m, n) &gt; SAD _min , the algorithm proceeds to step S14 to skip the search position (m, n) and proceed directly to step S22. If sea (m, n) <SAD _min , the algorithm proceeds to step S16 to continuously calculate the sum of absolute values [SAD (m, n)] of the differences of the respective search positions. After generating the sum of the absolute values of the difference [SAD (m, n)], the algorithm proceeds to step S18 to compare SAD (m, n) with SAD _min . If SAD (m, n) &gt; SAD _min , the algorithm proceeds to step S22, and if SAD (m, n) &lt; SAD _min , the algorithm proceeds to step S20 to determine the minimum value of the sum of the absolute values of the differences (SAD _min). ), And the process proceeds to step S22. In step S22, it is determined whether the current search position (m, n) is the last search position. If yes, this means that the position where the minimum SAD value is present is found, and the algorithm proceeds to step S26 to generate the predicted motion vector MV and terminate all processing. If no, this means that no other position has been searched, and the algorithm proceeds to step S24 to update the next search position (m, n) and proceeds to step S10 to repeat the above steps.

After calculating the sea value corresponding to each search position, the computational data flow becomes very irregular and a branch that is not predictable in advance may occur in the computational flow. As a result, a systolic array structure cannot be used when designing a hardware structure. After this, a multilevel continuous erasure algorithm was developed, but still cannot solve the same problem as described above.

In addition, the continuous cancellation algorithm must perform preliminary prediction of the motion vector (MV) in order to effectively reduce the amount of computation. Nevertheless, preliminary predictions of motion vectors within regions that are in irregular motion are very difficult. In addition, when the actual motion vector is out of the search range, the erase rate of the search position for the continuous erase algorithm is so low that the operation time of the continuous erase algorithm is longer than that of the entire search block matching algorithm. Also, in order to increase the number of times of canceling the operation of the sum of the difference absolute values, the continuous erasure algorithm typically uses a spiral scanning technique to determine the priority of the search position. Under this condition, hardware circuitry normally has to cost more than using conventional raster scan techniques.

Therefore, it would be desirable to propose a global erase algorithm and its hardware structure that can efficiently eliminate the disadvantages caused by conventional continuous erase algorithms.

SUMMARY OF THE INVENTION An object of the present invention is to provide a motion cancellation global erasing algorithm and a hardware structure thereof that appropriately remove branches of computational data flow so that data flow is more regular, smoother, and more adaptable for hardware implementation. .

Another object of the present invention is to provide a global cancellation algorithm with high reliability and sometimes better maximum signal-to-noise ratio (PSNR), which is a search result of the global cancellation algorithm and a full search block matching algorithm. There is a high degree of similarity between the results.

It is another object of the present invention to provide a hardware structure of the global cancellation algorithm for motion prediction, wherein the computational power for each logic gate is the best compared to other structures based on the entire search block matching algorithm, while Under the same throughput, the power consumption of the logic gate is lowest.

It is still another object of the present invention to provide a global cancellation algorithm for motion prediction that supports an advanced prediction mode and a hardware structure thereof.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing the operation flow of a conventional continuous cancellation algorithm.

2 is a flow chart illustrating a global erase algorithm in accordance with the present invention.

3 shows the percentage of the same motion vector of the global erasure algorithm and the global search block matching algorithm in the mobile calendar CIF video sequence.

4 illustrates the maximum signal-to-noise ratio pattern curve of the global cancellation algorithm and the global search block matching algorithm in a mobile calendar CIF video sequence.

5 is a diagram showing a hardware structure of the present invention.

6 illustrates the structure of a systolic module in accordance with the present invention.

7 illustrates the structure of a parallel adder tree in accordance with the present invention.

8 illustrates the structure of a parallel comparator tree according to the present invention.

9 illustrates how a hardware architecture in accordance with the present invention may support advanced prediction mode.

<Explanation of symbols for the main parts of the drawings>

10: systolic module

12: SAD tree

14: Parallel Comparator Tree

18: control unit

20: Multiplexer (MUX)

22, 24: MUX network

In order to realize these objects, the present invention provides a global erasure algorithm for motion prediction, comprising: presenting, in a coarse pattern, current blocks in a current frame among candidate blocks in a reference frame at each search location, Comparing the rough patterns in a current block and the candidate blocks, searching for M candidate blocks having a rough pattern similar to the current block, fine patterns of the M candidate blocks and the current Comparing the fine patterns of the blocks, and selecting a candidate block having a minimum value of the differences of the fine patterns of the M candidate blocks.

Another embodiment of the present invention is a hardware structure for performing a global erasure algorithm for motion prediction, comprising: (1) a systolic module that computes a coarse pattern of each sub-block in parallel; and (2) each coarse pattern and a candidate block of current blocks. An adder tree that compares each coarse pattern of the plurality of coarse patterns, which can be reused to compare each fine pattern of each of the current blocks with each fine pattern of the candidate blocks; At least one comparator tree for retrieving M candidate blocks having: a control device for controlling the operation of the systolic module, the adder tree, and the comparator tree; and storing data of the current block and the candidate blocks. It relates to a hardware architecture that includes at least one memory.

The present invention will be more apparent from the following detailed description with reference to the accompanying drawings.

(Detailed Description of the Preferred Embodiments)

Those skilled in the art already understand that motion prediction methods are an important component in the field of video compression technology and are applicable to multimedia electronic products such as digital camcorders. The present invention allows the flow of operational data to be more regular and more adaptive for the implementation of hardware, to have the characteristics of high reliability, high speed of computation and high efficiency, while eliminating the disadvantages caused by the conventional multilevel continuous erase algorithm. A novel global prediction algorithm for motion prediction and its hardware structure capable of appropriately reducing branches in the flow of operational data.

2 is a flow chart illustrating a global erase algorithm in accordance with the present invention. As can be seen from FIG. 2, the global erasure algorithm according to the present invention first includes calculating a multilevel continuous erase algorithm msea (m, n) value for each search position in step S30. In step S32, it is determined whether or not the search position (m, n) is the last search position. If the search position (m, n) is not the last search position, the algorithm proceeds to step S34 to update the next search position (m, n), and returns to step S30 to repeat the above-described steps. In step S34, the priority of the update to the search position can be set randomly and does not affect the final search result. In this case, therefore, conventional raster scanning techniques can be used. If the search position (m, n) is the final search position, the algorithm proceeds directly to step S36 to set a search range such as -p to p-1. In step S36, (2p), whereas to find the M number of search locations for holding the minimum value of the total msea search positions of the search position of the ^second, different [(2p) ² - M] deletes the search-position. After completing execution of step S36, the algorithm proceeds to step S38 to calculate the sum SAD (m, n) of the absolute values of the differences for each search position. Finally, the algorithm proceeds to step S40 to select the minimum value of the sum SAD (m, n) of the absolute values of the differences among the SAD values of the M search positions. The search position that maintains the minimum SAD value accurately predicts the motion vector by the global cancellation algorithm.

The reason for using the term called global erasure in this algorithm may be understood by step S32 of FIG. Unlike a multilevel continuous erase algorithm that checks search positions one by one to determine whether or not a search position can be erased, the global erase algorithm has an msea value corresponding to the entirety of the search position (multilevel continuous erase algorithm). Value), then it is determined whether or not the search position can be erased. During the calculation processing period for the msea value corresponding to each search position, the calculation is performed according to the right branch, and the flow of the calculation data is continuous and regular. Thus, the systolic array structure can be used to implement hardware structure design.

The choice of the value of M is a trade off between computation speed and encoding efficiency. The value of M is preferably placed between multiple levels of continuous erase algorithm values, for example 1 to 63. However, in general, the larger the value of M, i.e., the slower the computation speed, the higher the encoding efficiency. Conversely, the smaller the value of M, i.e., the faster the operation speed, the lower the encoding efficiency. Regardless of the value of M, the processing time required by each motion vector can be fixed and predictable. This is more beneficial for job scheduling of the hardware embodiment encoding system.

Although the global cancellation algorithm cannot guarantee that the search results are 100% identical to the search results of the entire search block matching algorithm, such as a multilevel continuous cancellation algorithm, the global cancellation algorithm is still very reliable. The present invention provides a number of tests for two common conditions. The first condition is a 16 × 16 block, a search range of -16 to +15, a msea value of the third level, M = 7, and a ratio of 99.31% of search positions for skipping the calculation of the SAD. QCIF (176 x 144) frames. The second condition is a 16 × 16 block, a search range of -32 to +31, a msea value of the third level, and not only M = 7, but also a ratio of 99.83% of search positions for skipping the calculation of the SAD. CIF (352 x 288) frames. The remaining results are shown in Table 1. The verification process of the test is tested by a number of standard test video sequences, and it can be seen that the average PNSR of the frame compensated by using the global erasure algorithm is very close to the result of the entire search block matching algorithm. The biggest but still minor difference is that the Hall monitor item of the CIF frame compensated by using the global erase algorithm is 0.08 dB lower than the Hall monitor item of the CIF frame compensated by the full search block matching algorithm. In addition, the average PNSR of the frame compensated by using the global erasure algorithm is the average of the frame compensated by using full search block matching algorithms such as Foreman QCIF, Silent QCIF, and Table Tennis QCIF. Often higher than PNSR. It is wrong to determine that the average PNSR of the entire search block matching algorithm is the maximum. This is because the minimum mean square error of, for example, 1 + 9 <5 + 6 and 1 ² +9 ² > 5 ² +6 ² can not be guaranteed. In most cases, the result of the global cancellation algorithm is very close to the result of the overall search block matching algorithm, which can be best understood from FIGS. 3 and 4. Figure 3 shows the percentage of the same motion coefficients of the global cancellation algorithm and the full search block matching algorithm in the Mobile Calendar CIF video sequence. It can be seen from FIG. 3 that 98.1% of the motion vectors are identical on average in 300 frames. 4 shows the pattern curve of the maximum signal-to-noise ratio of the global cancellation algorithm and the full search block matching algorithm in the mobile calendar CIF video sequence. Since these two curves are very close to each other, there is some difficulty in distinguishing between these two curves. As a result, the global elimination algorithm according to the present invention is found to have high reliability according to the statistics listed in the statistical table and the statistical diagram.

Unit: dB Standard video sequence (a) (b) Global Search Block Matching Algorithm Global elimination algorithm Global Search Block Matching Algorithm Global elimination algorithm Cost guard 32.93 32.93 31.59 31.55 Container 43.11 43.11 38.53 38.53 Foreman 32.21 32.22 32.85 32.82 Hall monitor 32.98 32.97 34.90 34.82 Mobile calendar 26.15 26.15 25.20 25.16 Silent 35.14 35.16 36.12 36.11 Stephan 24.71 24.67 25.73 25.71 Table tennis 32.10 32.11 33.03 32.96 Weather 38.42 38.42 37.45 37.45

After describing the global erase algorithm according to the present invention, the corresponding hardware structure will be described in more detail. A block having a size of 16 × 16, a msea value of a third level, and m = 7 will be described below with reference to FIG. 5, which is understood enough to enable those skilled in the art to practice the present invention with reference to the embodiments disclosed herein. The present invention will be described. As shown in FIG. 5, a hardware structure suitable for the motion prediction algorithm is referred to as a systolic module 10, a parallel adder tree 12, a parallel comparator tree 14, a control device for controlling the operation of each element, and the like. Memory 16 for storing candidate blocks in the frame and memory 16 'for storing the current blocks in the current frame. The control device comprises a control unit 18 and a control circuit composed of a multiplexer (MUX) 20, MUX network 1 22 and MUX network 2 24.

As shown in FIG. 5, the systolic module 10 calculates a sum of pixel intensities in 16 sub-blocks of a block having a size of 16 × 16, that is, a rough pattern, and outputs the result of the calculation in parallel in the same cycle. Used. 6 shows the computational data flow in the systolic module 10, where C _{1, k} and S _{1, k} represent the current block data c (k, 1) and search area data s (k, 1), respectively. . The rectangle shown in FIG. 6 is a shift register 26, and the search range is set, for example, between -16 and +15. Block data is loaded in parallel to the systolic module 10 in units of columns. If t = 0 to 15, the current block data is loaded into the systolic module 10, and if t = 15 the sum of the pixel intensities in each of the 16 4 x 4 sub-blocks of the current block of 16 x 16 (Indicated by sum ₀₀ -sum ₃₃ and csum ₀₀ -csum ₃₃ in Fig. 6) are computed and stored in 16 12-bit registers on the rising edge of the clock when t = 16. The search block data is then loaded into the systolic module 10. If t = 16 to 62, the candidate blocks in the search positions (-16, -16) to (+ 15, -16) are loaded, and if t = 31 to 62, the search positions of the candidate blocks (-16, The sum of the pixel intensities in each of the 16 sub-blocks within -16) to (+ 15, -16) (indicated by sum ₀₀ -sum ₃₃ and rsum ₀₀ -rsum ₃₃ in FIG. 6) is calculated. The search block data of the next row is calculated in the same way. If t = 63 ~ 109, the candidate block data in the search positions (-16, -15) to (+ 15, -15) is loaded; if t = 31 ~ 62, the search position of the candidate block (-16, The sum of pixel intensities in each of the sixteen sub-blocks within -15) to (+ 15, -15) is calculated. It can be seen from the foregoing that each row of search positions requires N clock cycles for loading the current block data along with (2p + N-1) clock cycles to calculate the sum of pixel intensities. Thus, the systolic module 10 requires N + 2p (2p + N-1) clock cycles to calculate the sum (rough pattern) of the pixel intensities in the lower blocks of every block.

The pixel intensity of the lower block and the same result computed by the systolic module 10 are sent to the parallel adder tree 12. 6 and 7, the parallel adder tree 12 is used to calculate the msea value according to Equation 1 below.

In Equation 1, K represents the sum of the pixels in the current block, and SB (m, n) represents the sum of the pixels in the candidate block at the search position (m, n). The absolute value of the difference between K and SB is exactly the sea value called the first order msea value. When one block is divided into L subblocks, K _q represents the sum of the pixels of the q th subblock of the current block, and SB _q (m, n) is the number of candidate blocks at the search position (m, n). It represents the sum of the pixels of the q-th lower block, the msea value can be obtained by summing the absolute value of the difference between a total of L K _q and SB _q . When one block is divided into 4 ^Level-1 lower blocks of the same size, this is called continuous erasure of the Level-th level. For example, the third level of continuous erasing is to divide a 16 × 16 block into 16 4 × 4 subblocks. As shown in Fig. 7, the element denoted ADXX is used to calculate the absolute value of the difference between the sum csum _xx of the pixel intensities of the lower blocks of the current block and the sum rsum _xx of the pixel intensities of the lower blocks of the candidate block. The parallel adder tree 12 is used to add up the results of AD00 to AD33 to obtain the msea value.

After the msea values of each block are obtained sequentially, the msea values are input to the parallel comparator tree 14 to find M search positions corresponding to the minimum msea values. Parallel comparator tree 14 is used to store the current minimum msea values as well as the corresponding motion vectors into registers. If the entered msea value is less than or equal to one or more msea values among M msea values, the maximum msea value is replaced with the entered msea value. If more than one msea value among M msea values is the maximum value, only one msea value should be replaced with the input msea value.

Figure 8 shows a circuit diagram of a parallel comparator tree according to the present invention, wherein the device labeled "_reg" represents a shift register and the device labeled "MAX" represents a comparator. In Fig. 8A, before a valid msea value is input from the parallel adder tree 12, part of the parallel comparator tree circuit sets the initial value of the registers msea1_reg to msea7_reg to 0xFFFF65535. A part of this parallel comparator tree circuit calculates the maximum value msea_max of the registers msea_in_reg and msea1_reg to msea7_reg, and the comparator MAX outputs the maximum value of the two inputs. The circuit shown in FIG. 8B is used to calculate the maximum value msea_max between the register msea_in_reg value and the register msea_in_reg value, and the comparator MAX outputs the maximum value between the two inputs. . The device EQU _X is used to compare between registers mseax_reg (x = 1 to 7), and the CHECK circuit is used to select one of two or more registers (mseax_reg), while the entirety of these registers is at most Value (msea_max). In other words, while activating the replace signal replace _x , registers mseax_reg and register mvx_reg must be replaced with registers msea_in_reg and register mv_in_reg, respectively, and only one replace signal replace _x is active. It shows. The parallel adder tree circuit as shown in Fig. 8C is used to perform the replacement operation, where the element MUX is a multiplexer in the control of the replacement signal replace _x .

In this way, at least M msea values and corresponding motion vectors can be stored in a register at any time. Msea until the value of the total of the search position (candidate blocks) is entered into a parallel adder tree 14 and register (2p) ² of search positions of the M include msea minimum value and a corresponding motion vector. Subsequently, a minimum value is found by calculating SAD values at M search positions, and a motion vector is output to complete prediction of the motion vector. It should be noted that when field data is entered into the systolic module 10 at the search position of each row, the msea value is generated by the parallel adder tree 12 while the previous (N-1) clock cycles are invalid. do. Hereinafter, the msea value to be input into the parallel adder tree 12 must be replaced with a value of 0xFFFF 65535 to produce a corrected result.

In order to output the column data of the candidate blocks in parallel, the operation of the hardware structure must be performed in a manner described below. The data within the search range has a total of (2p + N-1) rows. According to the present invention, the row data is numbered from 0 to (2p + N-2), and as shown in Fig. 5, the row data having zero remainder generated by dividing the number of the row data by N is stored in memory. While the data is stored in RAM00 of (16), the row data having a remainder of 1 generated by dividing the number of row data by N is stored in RAM01. Thus, column data can be output in parallel by N RAM modules controlled by N appropriate addresses. As with the current block data, the column data of the current block data is stored in another 128-bit (assuming N = 16) memory 16 'to be output in parallel. While the column data of the candidate blocks are output, these candidate blocks must pass through multiplexer network 1 (22) in order for these candidate blocks to be entered in the correct lower blocks before being input to the systolic module 10. Under the condition of N = 16 and Level = 3, multiplexer network 1 22 includes sixteen four-to-one eight-bit multiplexers. For different row search positions, the control signal used to control multiplexer network 1 22 must be adjusted accordingly.

Similarly, while computing the SAD values of the M search positions, the data of the candidate block passes through multiplexer network 2 (24) and then to parallel adder tree (12) consisting of 16 16 to 1 8-bit multiplexers. It must be entered. The control signal for controlling the multiplexer network 2 24 must be modulated for the search position of different rows. Therefore, the present invention requires N + 2p (2p + N-1) clock cycles to find M search positions where the minimum sea value is maintained. The resources of parallel adder tree 12 can be reused. Each search position requires N clock cycles to compute the SAD value of that search position, and the M search positions require (M × N) clock cycles to compute the entirety of the SAD value. In conclusion, taking N = 16 and Level = 3 as an example, the hardware structure according to the present invention requires N + 2p (2p + N-1) + (M × N) clock cycles to compute the motion vector. Shall be.

As such, the spirit and principles of the present invention have been described. Specific experimental embodiments are presented immediately below to verify the principles and effects described above. In order to analyze the performance of the hardware structure according to the present invention, the hardware structure of the present invention is compared with the hardware structure based on the entire search block matching algorithm, where the hardware structure to be compared is referred to [1] listed later in this specification. ] To [7]. The comparison results are shown in Tables 2 and 3, where Table 2 shows a comparison between the different structures under the conditions of 16 × 16 blocks, a search range of -16 to +15, Level = 3 and M = 7. Table 3 shows a comparison between the different structures under conditions of 16 × 16 blocks, a search range of -32 to +31, Level = 3 and M = 7.

This comparison occurs with respect to the array of processing elements, while the control circuitry performs insignificant parts of these hardware structures and therefore is not implemented in the form of hardware. The processing element array is AVANT! Synthesized by SYNOPSYS design analyzer with 0.35 μm cell library, Critical Path Constraint is set to 20 μs. That is, the operating frequency of the circuit can reach at least 50 MHz. In addition to the processing elements, structures marked with an asterisk (*) are shown in Tables 2 and 3, and a large amount of additional logic circuits, mostly composed of shift registers, are required to increase the reusability of data. As a result, the actual gate coefficients and power consumption of the logic gates of these hardware structures are much higher than the simulations. In Tables 2 and 3, note that the memory, multiplexer network 2 and control unit cannot be run in a simulation, while other devices can consider the simulation. Also, the three stage pipeline is not suitable for simulation.

In order to compare these hardware structures fairly, these hardware structures of motion vectors must be compared based on the same throughput (motion vectors / second). Therefore, "normalized processing capability per gate" (NPCPG) and normalized power (NP) are defined by the following equations (2) and (3), respectively.

In general, the computational speed of the 1-D array structure with respect to the required clock cycles is not fast enough, and the operating frequency of the 1-D array structure must be increased for large-frame and wide search applications. On the other hand, although the computational speed of the 2-D array structure is faster than that of the 1-D array structure, the amount of logic gates is large, and the cost is high. Although the structure of Ref. [6] is a kind of 1-D array structure, this structure takes the same problem as the 2-D array structure, i.e. a large amount of logic gates, because it takes the reuse of data-interlacing and 2-D structures. Has the necessary problem. Although the tree structure performs a good performance in terms of computation speed and area, the practical memory bit width is very large, thus making it less practical. Although the computational speed of the hardware structure according to the present invention is substantially slower than the 2-D array structure and the tree structure (the computational speed of the structure of Ref. [3] is slower than the present invention), the logic gate of the present invention The amount is much less than other structures. Considering the 1-D array structure, the computational speed of the 1-D array structure is much slower than the computational speed of the present invention, and the amount of logic gates of the 1-D array structure is much larger than the amount of logic gates of the present invention in the extensive search. more. In fact, the performance of the present invention is superior to other structures in terms of "normalized processing power per gate" and "normalized power".

rescue Explanation PE water Cycle per MV Required Memory I / O Frequency Required for CIF 30fps Gate Factor @ 50 MHz NPCPG Gate-Level Power @ 50MHz NP [1] Yang 1-D semi-systolic 32 8192 24-bit 97.32 MHz 28.0K 0.13 26.0 mW 2.99 [2] AB1 1-D systolic 16 24064 256 bit 285.88 MHz 3.8K 0.32 11.7 mW 3.95 [2] AB2 2-D systolic 256 1504 128 bit 17.87 MHz 95.1K 0.20 227.8mW 4.82 [3] Hsieh ＊ 2-D systolic 256 2209 8 bit 26.24 MHz 100.6K 0.13 147.2 mW 4.57 [4] Tree Tree structure 256 1024 2048 bit 12.17 MHz 56.1K 0.51 179.5 mW 2.59 [5] Yeo 2-D semi-systolic 1024 256 24-bit 3.04 MHz 447.4K 0.26 1052.6 mW 3.79 [6] Lai 1-D semi-systolic 1024 256 24-bit 3.04 MHz 387.6K 0.30 845.6mW 3.04 [7] SA ＊ 2-D systolic 256 1024 16 bit 12.17 MHz 126.5K 0.23 258.0 mW 3.72 [7] SSA ＊ 2-D semi-systolic 256 1024 16 bit 12.17 MHz 106.0K 0.27 280.1mW 4.04 The present invention GEA-based 16 1635 256 bit 19.42 MHz 17.9K 1.00 43.4mW 1.00

rescue Explanation PE water Cycle per MV Required Memory I / O Frequency Required for CIF 30fps Gate Count @ 50 MHz NPCPG Gate-Level Power @ 50MHz NP [1] Yang 1-D semi-systolic 32 16384 24-bit 194.64 MHz 56.0K 0.10 52.0 mW 3.78 [2] AB1 1-D systolic 16 80896 256 bit 961.04 MHz 3.8K 0.30 11.7 mW 4.20 [2] AB2 2-D systolic 256 5056 128 bit 60.07 MHz 95.1K 0.19 227.8mW 5.12 [3] Hsieh ＊ 2-D systolic 256 6241 8 bit 74.14 MHz 100.6K 0.15 147.2 mW 4.08 [4] Tree Tree structure 256 4096 2048 bit 48.66 MHz 56.1K 0.40 179.5 mW 3.27 [5] Yeo 2-D semi-systolic 1024 256 24-bit 3.04 MHz 1790.0K 0.20 4210.3 mW 4.79 [6] Lai 1-D semi-systolic 1024 256 24-bit 3.04 MHz 1550.4K 0.23 3382.4 mW 3.84 [7] SA ＊ 2-D systolic 256 4096 16 bit 48.66 MHz 126.5K 0.18 258.0 mW 4.69 [7] SSA ＊ 2-D semi-systolic 256 4096 16 bit 48.66 MHz 106.0K 0.21 280.1mW 5.09 The present invention GEA-based 16 5187 256 bit 61.62 MHz 17.9K 1.00 43.4mW 1.00

In the next generation of video compression standards, for example video compression standards such as H.263 + and MPEG-4, other types of motion prediction modes may be provided. The blocks used in the motion prediction algorithms of the next generation of video compression standards are not limited to the normal block size of 16 × 16, but can generate four motion vectors of four 8 × 8 subconvexs within a 16 × 16 pixel block. Can be. If the video compression algorithm can properly determine the motion vectors that must be used first, the encoding efficiency can be significantly improved. This motion prediction mode is called "advanced prediction mode". The hardware structure according to the present invention can easily support the advanced prediction mode in addition to the four parallel comparator trees, as shown in FIG. If the structure of the present invention is capable of supporting advanced prediction modes, better encoding efficiency can be obtained by designing the circuit topology with level = 4.

Thus, the present invention makes the computational data flow more regular, smooth and more suitable for hardware implementation, and it is possible to solve the disadvantages faced by conventional multi-level successive erase algorithms. In addition, the present invention provides high reliability, high computing power and minimally reduced power consumption for its logic gates under conditions of the same throughput of motion vectors.

Although the invention has been described and illustrated in detail, it is to be understood that this is merely illustrative and not for the purpose of limitation, and the spirit and scope of the invention is limited only by the appended claims.

[references]

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[2] "Array architectures for block matching algorithms," by T. Kaomarek and P. Pirsch (IEEE Trans. On Circuits and Systems, vol. 36, no. 2, pp. 1301-1308, Oct. 1989).

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Claims (15)

As a global cancellation algorithm for motion prediction, Displaying the current blocks in the current frame among the candidate blocks in the reference frame at each search place in a coarse pattern; Comparing the rough patterns in the current block and the candidate blocks; Searching for M candidate blocks having a rough pattern similar to the current block; Comparing the fine patterns of the M candidate blocks with the fine patterns of the current blocks; Selecting a candidate block having a minimum value among differences of the fine patterns of the M candidate blocks Global erasing algorithm comprising a. 2. The global erase algorithm of claim 1, wherein M has a value in the range of 1 to 63. The global cancellation algorithm of claim 1, wherein the motion vector corresponding to the minimum value of the differences of the fine patterns of the candidate blocks is a predicted motion vector. 2. The global erase algorithm of claim 1, wherein the coarse pattern is one of a continuous erase algorithm value and a multilevel continuous erase algorithm value. The global erase algorithm of claim 1, wherein the differences of the fine patterns of the candidate blocks are a sum of absolute values of the differences. The global erase algorithm of claim 1, wherein the M candidate blocks are located at M search locations having a minimum value among fine patterns. In a hardware structure for performing a global cancellation algorithm for motion prediction, A systolic module that computes rough patterns of the respective lower blocks in parallel; An adder tree that compares each coarse pattern of the current blocks with each coarse pattern of the candidate blocks, the adder tree reusable for comparing each fine pattern of the current blocks with each fine pattern of the candidate blocks; ; At least one comparator tree for searching M candidate blocks having a rough pattern similar to the current block; A control device for controlling the operation of the systolic module, the adder tree and the comparator tree; At least one memory for storing data of the current block and the candidate blocks Hardware structure comprising a. 8. The hardware structure of claim 7, wherein the systolic module includes a processing unit for computing a coarse pattern in the current block and the candidate block. 8. The method of claim 7, wherein the comparator tree stores the similarity of the M candidate blocks and their corresponding motion vectors in a register and compares the similarity of the M candidate blocks to the similarity of an input candidate block. Search for candidate blocks that are not the most similar to the current block among candidate blocks and the input candidate blocks, and convert the input candidate blocks into one candidate block that is not similar to the current block but is part of candidate blocks in the register; And replace the input candidate block with a candidate block of any one of the candidate blocks that are not similar to the current block and are part of the candidate blocks in the register. 8. The hardware structure of claim 7, wherein M has a value within the range of 1 to 63. 10. The hardware structure of claim 9, wherein M has a value in the range of 1 to 63. 8. The hardware structure of claim 7, further comprising four additional adder trees coupled to the adder tree and capable of supporting a pre-prediction mode by slightly modifying the configuration of the control unit. 8. The hardware structure of claim 7, wherein the rough pattern is one of a continuous erase algorithm value and a multilevel continuous erase algorithm value. 8. The hardware structure of claim 7, wherein the differences of the fine patterns of the candidate blocks are a sum of absolute values of the differences. 8. The hardware structure of claim 7, wherein the M candidate blocks are located in M search locations with a minimum fine pattern.