KR20030077123A - Versatile ISP device - Google Patents

Abstract

PURPOSE: A multi-function ISP device is provided to reduce a board size for loading an FPGA(File Programmable Gate Array) or a CPLD(Complex Programmable Logic Device), reduce a use of a passive element, flexibly change a board configuration according to kinds of an applied FPGA or a CPLD, and apply the board configuration in the case that a system is developed using a programmable logic chip such as the FPGA or the CPLD. CONSTITUTION: The first connector(211) is connected to a system(for example, a computer). A device setting unit(212) adjusts a board setting according to kinds of programmable logic chips being connected in an exterior. The second connector(213) is connected to the programmable logic chip. A target board(220) includes the programmable logic chip(for example, an FPGA(221) and the third connector(222) for a connection to the second connector(213) of the multi-function ISP board(210)). An ISP cable(230) connects the second connector(213) of the multi-function ISP board(210) to the third connector(222) of the target board(220).

Description

Versatile ISP device

The present invention relates to an In System Programmability (ISP) device, and in particular, when developing a system using a programmable logic chip such as a Field Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD), an FPGA or CPLD is mounted. The present invention relates to a multifunctional ISP device that can reduce the board size and the use of passive devices.

In general, application specific ICs (ASICs) are commonly used for all types of integrated circuits designed and manufactured for specific purposes. This is changing the TTL circuit on the board to CAD Programmable Logic Device (CPLD) / Field Programmable Gate Array (FPGA) using Computer Aided Design (CAD) to reduce the number of parts, PCB area, and cost by mass production. This results in an improvement in processing speed.

The CPLD is equipped with logic blocks having the same function as a single PLD, switches, matrix circuits, etc. connecting them, and do not require separate timing and simulation.

The FPGA has logic functions inside the chip and has wiring areas for connecting with logic modules such as cells and blocks. This provides a high degree of design freedom but requires timing simulation after wiring is complete.

They are different in structure and cross each other's strengths and weaknesses. CPLDs are advantageous for address decoders and sequence circuits that require simple signal processing. FPGAs are advantageous for circuits that require complex signal processing such as computation. .

CPLD / FPGA is composed of anti-fuse type, EPROM type, EEPROM type, SRAM type, and a combination of these types. CPLD / FPGA itself does not have any executable program. When inserted, it functions as an ASIC.

In the production of such an ASIC, a program for a specific purpose is designed and the designed program is written in CPLD / FPGA. Before mass production of the AJ, it is necessary to check whether the custom IC works normally.

Meanwhile, in order to perform such a task, an ISP device is frequently used. An example thereof is illustrated in FIG. 1 is a diagram schematically showing a configuration of a conventional ISP device.

Referring to FIG. 1, a conventional ISP device includes an ISP connector 120 to which an FPGA 110, which is one of programmable logic chips, and an ISP cable (not shown) for connection with a system (for example, a computer) are connected. It includes. In this design method, the connection of passive devices (pull-up resistors, pull-down resistors, and capacitors) for ISP devices is recommended differently for each FPGA vendor and each FPGA device. Accordingly, the ISP device user must additionally make suitable configurations (R1, R2, R3, R4, C1) in the ISP device for the FPGA device employed.

However, in general, the ISP device thus formed is usually used only once to several tens of times. Therefore, when using an ISP device as in the related art, each time the ISP device is designed, a passive element needs to be additionally formed according to the type of FPGA or CPLD device employed.

The present invention was created in view of the above conditions, and when the system is developed using a programmable logic chip such as an FPGA or CPLD, the board size on which the FPGA or CPLD is mounted can be reduced, and the use of passive elements can be reduced. It is also an object of the present invention to provide a multifunctional ISP device that can be flexibly modified by applying a board configuration according to the type of FPGA or CPLD employed.

1 is a diagram schematically showing the configuration of a conventional ISP device.

Figure 2 is a block diagram schematically showing the configuration of a multi-function ISP device according to the present invention.

3 is a diagram showing an example of the configuration of a multi-function ISP board employed in the multi-function ISP device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

110 ... FPGA120 ... ISP Connector

210 ... Multifunction ISP Board 211 ... 1st Connector

212 ... Device setting section 213 ... 2nd connector

220 ... Target Board 221 ... FPGA

222 ... 3rd Connector 230 ... ISP Cable

311 ... 1st input connector 312 ... 2nd input connector

321 ... first switch 322 ... second switch

323 ... third switch 324 ... fourth switch

325 ... fifth switch 331 ... pull-down array resistor

332 ... Pull-Up Array Resistor333 ... Capacitor

340 ... Output connector

In order to achieve the above object, the multifunction ISP device according to the present invention,

A multifunction ISP having a first connector for connecting to a system, a device setting unit for adjusting board settings according to a type of programmable logic chip connected externally, and a second connector for connecting to the programmable logic chip. With the board;

A target board having a third connector for connecting the programmable logic chip and a second connector of the multifunction ISP board; And

An ISP cable connecting the second connector of the multifunction ISP board and the third connector of the target board; Its features are to include.

Here, the device setting unit of the multifunction ISP board,

A pull down array resistor providing a pull down resistance value;

A first switch for adjusting a connection state of the pull-down array resistor according to a type of the programmable logic chip connected externally;

A pull up array resistor providing a pull up resistance value;

A second switch for adjusting a connection state of the pull-up array resistor according to a type of the programmable logic chip connected externally;

A capacitor providing capacitance;

A third switch for adjusting a connection state of the capacitor according to a type of the programmable logic chip connected externally;

A fourth switch for adjusting a connection state of ground according to the type of the programmable logic chip connected externally; And

A fifth switch for adjusting a connection state with the second connector according to a type of the programmable logic chip connected externally; Its features are that it has a.

In addition, the programmable logic chip is characterized in that the field programmable gate array (FPGA).

In addition, the programmable logic chip is characterized in that the CPLD (Complex Programmable Logic Device).

According to the present invention, when developing a system using a programmable logic chip such as an FPGA or CPLD, the board size on which the FPGA or CPLD is mounted can be reduced, the use of passive elements can be reduced, and the FPGA or CPLD employed According to the type of the board configuration can be flexibly modified and applied.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram schematically showing the configuration of a multi-function ISP device according to the present invention.

Referring to FIG. 2, the multi-function ISP device according to the present invention may be configured with a first connector 211 for connecting to a system (for example, a computer) and a board setting according to a type of programmable logic chip connected externally. A multifunction ISP board 210 having a device setting section 212 for adjusting and a second connector 213 for connection with the programmable logic chip; A target board (220) having a third connector (222) for connection with the programmable logic chip, for example, the FPGA (221) and the second connector (213) of the multifunction ISP board (210); And an ISP cable 230 connecting the second connector 213 of the multifunction ISP board 210 and the third connector 222 of the target board 220. It includes.

On the other hand, the multi-function ISP board 210 may be configured as shown in FIG. 3 is a diagram showing an example of the configuration of a multi-function ISP board employed in the multi-function ISP device according to the present invention.

Referring to FIG. 3, the multi-function ISP board 210 is a port for connecting with a system, and a plurality of 311 (312) according to the type of the connected connector, such as a commonly used input connector, such as JTAG ) Can be provided.

The device setting unit 212 of the multifunction ISP board 210 includes: a pulldown array resistor 331 providing a pulldown resistance value; A first switch (321) for adjusting a connection state of the pull-down array resistor (331) according to the type of the programmable logic chip, for example, the FPGA (221) connected to the outside; A pull-up array resistor 332 which provides a pull-up resistor value; A second switch (322) for adjusting a connection state of the pull-up array resistor (332) according to the type of the programmable logic chip, eg, the FPGA (221), which is connected externally; A capacitor 333 providing a capacitance; A third switch (323) for adjusting a connection state of the capacitor (333) according to the type of the programmable logic chip, for example, the FPGA (221) connected to the outside; A fourth switch 324 for adjusting a connection state of the ground according to the type of the programmable logic chip connected to the outside, for example, the FPGA 221; And a fifth switch 325 for adjusting a connection state with the second connector 213, which is an output connector 340, according to the type of the programmable logic chip connected to the outside, for example, the FPGA 221.

Here, the connection setting for the pull-down array resistor 331, the pull-up array resistor 332, the capacitor 333, the ground, the output connector 340, the externally connected programmable logic chip, for example, the FPGA 221 The setting is completed by adjusting the switches 321, 322, 323, 324 and 325 according to the type recommended by the manufacturer according to the type.

In addition, although the description has been made of the case where the FPGA 221 is used as a programmable logic chip, it is apparent that other programmable logic chips such as CPLD can be used.

Through such a configuration, passive elements such as pull-down resistors, pull-up resistors, and capacitors are removed from the target board 220, so that only the third connector 222 and the FPGA 221 which are ISP connectors can be formed. Accordingly, the target board 220 can reduce the space by disappearing the passive elements, and assuming that the target board 220 mass-produces 10,000, there is an advantage of saving 50,000 passive elements. .

In addition, the multifunction ISP board 210 includes five small switches 321, 322, 323, 324 and 325, pull-up / pull-down array resistors 331, 332, capacitors 333 and inputs. It can be implemented in a small size (5cm * 5cm) by using the / output connectors (311, 312, 340).

As described above, according to the multifunction ISP device according to the present invention, when developing a system using a programmable logic chip such as an FPGA or CPLD, the board size on which the FPGA or CPLD is mounted is reduced, and the use of passive elements is reduced. The board configuration can be flexibly modified according to the type of FPGA or CPLD employed.

Claims (4)

A multifunction ISP having a first connector for connecting to a system, a device setting unit for adjusting board settings according to a type of programmable logic chip connected externally, and a second connector for connecting to the programmable logic chip. With the board; A target board having a third connector for connecting the programmable logic chip and a second connector of the multifunction ISP board; And An ISP cable connecting the second connector of the multifunction ISP board and the third connector of the target board; Multifunctional ISP device comprising a. The method of claim 1, The device setting unit of the multifunction ISP board, A pull down array resistor providing a pull down resistance value; A first switch for adjusting a connection state of the pull-down array resistor according to a type of the programmable logic chip connected externally; A pull up array resistor providing a pull up resistance value; A second switch for adjusting a connection state of the pull-up array resistor according to a type of the programmable logic chip connected externally; A capacitor providing capacitance; A third switch for adjusting a connection state of the capacitor according to a type of the programmable logic chip connected externally; A fourth switch for adjusting a connection state of ground according to the type of the programmable logic chip connected externally; And A fifth switch for adjusting a connection state with the second connector according to a type of the programmable logic chip connected externally; Multifunctional ISP device characterized in that it comprises a. The method of claim 1, And said programmable logic chip is a field programmable gate array (FPGA). The method of claim 1, And wherein said programmable logic chip is a complex programmable logic device (CPLD).