KR20030075631A - A method for etch of semiconductor device by using plasma - Google Patents

A method for etch of semiconductor device by using plasma Download PDF

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KR20030075631A
KR20030075631A KR1020020014957A KR20020014957A KR20030075631A KR 20030075631 A KR20030075631 A KR 20030075631A KR 1020020014957 A KR1020020014957 A KR 1020020014957A KR 20020014957 A KR20020014957 A KR 20020014957A KR 20030075631 A KR20030075631 A KR 20030075631A
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South Korea
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plasma
etching
semiconductor device
chamber
barc
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KR1020020014957A
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Korean (ko)
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문성열
김갑철
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주식회사 하이닉스반도체
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • H01L21/31138Etching organic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: A method for etching a semiconductor device using plasma is provided to be capable of improving the quality of the semiconductor device and the capacity of a TCP(Transformer Coupled Plasma) equipment by removing particles generated when carrying out an etching process at a BARC(Bottom Anti-Reflective Coating), using SF6 and O2 plasma. CONSTITUTION: A plasma etching process is carried out at a BARC by using a TCP method. At this time, particles are generated and attached on the inner wall of a chamber(100) and many kinds of parts. Then, the particles are removed by using SF6 and O2 plasma. Then, a wafer(110) is loaded in the chamber for carrying out an etching process. The BARC and an etch object layer are selectively etched. Preferably, the particle removing process is carried out by using the SF6 plasma of 100-300 sccm and the O2 plasma of 10-100 sccm.

Description

플라즈마를 이용한 반도체 소자의 식각방법{A METHOD FOR ETCH OF SEMICONDUCTOR DEVICE BY USING PLASMA}A method for etching semiconductor devices using plasma {A METHOD FOR ETCH OF SEMICONDUCTOR DEVICE BY USING PLASMA}

본 발명은 플라즈마를 이용한 반도체 소자 식각방법에 관한 것으로, 특히 TCP(Transformer Coupled Plasma) 장비에서 BARC(Bottom Anti Reflect Coating) 식각시 발생하는 이물을 제어할 수 있는 플라즈마를 이용한 반도체 소자의 식각방법에 관한 것이다.The present invention relates to a method of etching a semiconductor device using plasma, and more particularly, to an etching method of a semiconductor device using a plasma that can control foreign substances generated during BARC (Bottom Anti Reflect Coating) etching in Transformer Coupled Plasma (TCP) equipment. will be.

플라즈마를 이용한 반도체 소자의 식각방법은 공정의 조건 등에 따라 다양한 형태의 플라즈마 소오스에서 에너지원으로서 RF 제너레이터를 이용하여 발생시킨다. 이러한 플라즈마 소오스 및 그에 적용되는 RF 제너레이터로서는 애노드(anode)에 RF 전력을 인가하여 플라즈마를 생성시키는 플래너(Planar)방식과, 웨이퍼가 위치하는 캐소드에 RF 전력을 인가하여 플라즈마를 발생시키는 RIE(Reactive Ion Etching)방식 그리고 공급가스를 미리 마이크로웨이브 전력으로 플라즈마화하여 공급하는 CDE(Chemical Downstream Etching)방식, 전자의 사이클론 운동을 유발하여 플라즈마화하는 ECR(Electron Cyclotron Resonance)방식, 코일에 의해 전자에 파동에너지를 부가함으로써 고밀도의 플라즈마를 형성시키는 헬리콘(Helicon)방식, 코일에 흐르는 전류에 의해 플라즈마내에서 유기된 인덕턴스 성분에 의해 고밀도 플라즈마를 형성시키는 TCP(Transformer Coupled Plasma)방식 및 코일에 의한 자계에 의해 플라즈마 내부에 전계를 유발하여 전자를 가속시키는 ICP(Inductivity Coupled Plasma)방식 등이 있다.The etching method of a semiconductor device using plasma is generated by using an RF generator as an energy source in various types of plasma sources depending on the process conditions. Such a plasma source and an RF generator applied thereto include a planar method for generating a plasma by applying RF power to an anode, and a reactive ion for generating a plasma by applying RF power to a cathode where a wafer is located. Etching) method and CDE (Chemical Downstream Etching) method to supply the supply gas into microwave power in advance by microwave power, and ECR (Electron Cyclotron Resonance) method to induce plasma by inducing electron cyclone movement. Helicon method for forming a high density plasma by adding a high density plasma, TCP (Transformer Coupled Plasma) method for forming a high density plasma by an inductance component induced in the plasma by a current flowing through the coil and a magnetic field by the coil ICP accelerates electrons by causing an electric field inside the plasma (Inductivity Coupled Plasma) method.

한편, 반도체 제조 공정에 있어서 선폭이 작아짐에 따라 포토 노광 공정시 빛의 반사로 인한 불안정한 패턴 형성을 억제하기 위해 BARC막이 필요하다. 따라서, 상기 BARC막은 식각공정시 별도의 진행 공정이 요구되며, 노광시 선폭의 흔들림이나 불안정의 해결을 위해 도입된 만큼 식각시에도 그 부분에서 특히 안정적인 공정 특성이 요구된다.On the other hand, as the line width decreases in the semiconductor manufacturing process, a BARC film is required to suppress unstable pattern formation due to reflection of light during the photoexposure process. Therefore, the BARC film requires a separate process in the etching process, and since it is introduced to solve the shaking or instability of the line width during exposure, particularly stable process characteristics are required in the portion during etching.

도 1은 종래의 플라즈마를 이용한 반도체 소자의 식각장치를 나타낸 개략도이다.1 is a schematic view showing an etching apparatus of a semiconductor device using a conventional plasma.

도 1에 도시한 바와 같이 플라즈마를 이용한 반도체 소자의 식각공정을 수행할 챔버(10)에 있어서, 상기 챔버(10)내에 식각공정이 수행될 피처리 기판인 웨이퍼(1)와, 상기 웨이퍼(1)를 로딩하여 고정하는 정전척(2) 및 하부전극(3) 그리고 상기 하부전극(3)의 외측 하부에 설치되어 배기펌프(4)에 의해 상기 웨이퍼(1)의 외측으로 플라즈마가 흐르는 것을 방지하기 위한 셰도우링(5)을 구비한다.As shown in FIG. 1, in a chamber 10 to perform an etching process of a semiconductor device using plasma, a wafer 1, which is a substrate to be subjected to an etching process, and the wafer 1 in the chamber 10 are performed. ) Is installed on the electrostatic chuck (2) and the lower electrode (3) and the outer lower portion of the lower electrode (3) to prevent the plasma from flowing out of the wafer (1) by the exhaust pump (4) The shadow ring 5 for this is provided.

그러나 상기와 같이 구성된 식각장치중 TCP 방식을 이용한 식각방법에 의하면, BARC막(도면에 도시하지 않았음) 자체가 카본 성분이기 때문에 식각중에 많은 카본 성분과 결합된 다량의 생성물(6)이 발생할 수 있고, 이들은 상기 챔버(10)의 벽과 부품(parts)에 부착된다.However, according to the etching method using the TCP method among the etching apparatus configured as described above, since the BARC film (not shown) is itself a carbon component, a large amount of product 6 combined with many carbon components during etching may occur. And they are attached to the walls and parts of the chamber 10.

따라서, 종래의 플라즈마를 이용한 반도체 소자의 식각방법에 있어서는 다음과 같은 문제점이 있었다.Therefore, the conventional etching method of a semiconductor device using plasma has the following problems.

챔버내에 부착된 카본 성분과 결합된 다량의 생성물이 웨이퍼 식각 공정시 낙하되거나 와류에 의해 웨이퍼상에 떨어져 이물 소오스가 된다. 즉, 도 2와 같은 원형이물이 발생한다.A large amount of product combined with the carbon component deposited in the chamber is dropped during the wafer etching process or dropped on the wafer by the vortex to become a foreign material source. That is, the circular foreign material as shown in FIG.

한편, 원형이물의 성분은 도 3과 같이 반응 챔버내 부품 성분인 알루미늄(Al)과 포토레지스트 및 BARC의 주성분인 카본(C)으로 일정한 맵(Map)을 갖고 있다.On the other hand, as shown in Fig. 3, the circular foreign material has a constant map as aluminum (Al), a component component in the reaction chamber, and carbon (C), a main component of BARC.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 SF6과 O2플라즈마를 이용하여 종래 TCP 방식의 식각 공정시 발생하는 원형이물의 성분을 제거해줌으로써 반도체 소자의 품질향상 및 장비 용량을 향상시킬 수 있는 플라즈마를 이용한 반도체 소자의 식각방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems by using the SF 6 and O 2 plasma to improve the quality of semiconductor devices and equipment capacity by removing the components of the circular foreign substances generated during the conventional TCP etching process An object of the present invention is to provide an etching method of a semiconductor device using plasma.

도 1은 종래의 플라즈마를 이용한 반도체 소자의 식각장치를 나타낸 개략도1 is a schematic view showing an etching apparatus of a semiconductor device using a conventional plasma

도 2는 종래의 반도체 소자 식각시 발생하는 원형이물을 나타낸 도면2 is a view illustrating a circular foreign material generated when etching a conventional semiconductor device

도 3은 도 2의 원형이물의 성분을 나타낸 도면3 is a view showing the components of the circular foreign material of FIG.

도 4a 및 도 4b는 본 발명의 플라즈마를 이용한 반도체 소자의 식각방법을 나타낸 도면4A and 4B illustrate an etching method of a semiconductor device using a plasma of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100 : 챔버 110 : 웨이퍼100 chamber 110 wafer

120 : 정전척 130 : 하부전극120: electrostatic chuck 130: lower electrode

140 : 배기펌프 150 : 셰도우링140: exhaust pump 150: shadow ring

160 : 생성물160: product

상기와 같은 목적을 달성하기 위한 본 발명의 플라즈마를 이용한 반도체 소자의 식각방법은 TCP 방식을 이용한 플라즈마 식각방법에 있어서, 상기 TCP 방식에 의해 BARC막 식각 공정시 발생하여 챔버의 벽 및 각종 부품에 부착된 생성물을 SF6과 O2플라즈마 혼합가스로 상기 생성물을 제거하는 단계와, 상기 챔버내에 식각공정이 수행될 웨이퍼를 정착한 후, BARC 및 피식각층을 선택적으로 식각하는 단계를 포함하는 것을 특징으로 한다.The etching method of the semiconductor device using the plasma of the present invention for achieving the above object is a plasma etching method using the TCP method, generated during the BARC film etching process by the TCP method and attached to the walls of the chamber and various components Removing the product with the SF 6 and O 2 plasma mixed gas; and fixing the wafer to be etched in the chamber, and selectively etching the BARC and the etching layer. do.

또한, 상기 SF6플라즈마는 100∼300sccm이고, 상기 O2플라즈마는 10∼100sccm인 것이 바람직하다.In addition, the SF 6 plasma is preferably 100 to 300 sccm, and the O 2 plasma is preferably 10 to 100 sccm.

이하, 첨부된 도면을 참조하여 본 발명의 플라즈마를 이용한 반도체 소자의 식각방법에 대하여 보다 상세히 설명하기로 한다.Hereinafter, an etching method of a semiconductor device using a plasma of the present invention will be described in detail with reference to the accompanying drawings.

도 4a 및 도 4b는 본 발명의 플라즈마를 이용한 반도체 소자의 식각방법을 나타낸 도면이다.4A and 4B illustrate an etching method of a semiconductor device using a plasma of the present invention.

도 4a에 도시한 바와 같이 플라즈마를 이용한 반도체 소자의 식각공정을 수행할 챔버(100)에 있어서, 상기 챔버(100)내에 식각공정이 수행될 피처리 기판인웨이퍼(110)와, 상기 웨이퍼(110)를 로딩하여 고정하는 정전척(120) 및 하부전극(130) 그리고 상기 하부전극(130)의 외측 하부에 설치되어 배기펌프(140)에 의해 상기 웨이퍼(110)의 외측으로 플라즈마가 흐르는 것을 방지하기 위한 셰도우링(150)을 구비한다.As shown in FIG. 4A, in a chamber 100 to perform an etching process of a semiconductor device using plasma, a wafer 110, which is a substrate to be etched, and a wafer 110 in which the etching process is performed in the chamber 100. ) Is installed on the electrostatic chuck 120, the lower electrode 130, and the outer lower portion of the lower electrode 130 to prevent the plasma from flowing out of the wafer 110 by the exhaust pump 140. A shadow ring 150 is provided for the purpose.

그러나 상기와 같이 구성된 식각장치중 TCP 방식을 이용한 식각방법에 의하면, 상기 웨이퍼(110)상의 식각공정이 처리될 BARC막(도면에 도시하지 않았음) 자체가 카본 성분이기 때문에 식각중에 많은 카본 성분과 결합된 다량의 생성물(160)이 발생하여 상기 챔버(100)의 벽과 부품에 부착된다.However, according to the etching method using the TCP method among the etching apparatus configured as described above, since the BARC film (not shown in the drawing) itself is a carbon component to be etched on the wafer 110, a large amount of carbon component and A combined amount of product 160 is generated and attached to the walls and components of the chamber 100.

도 4b에 도시한 바와 같이 식각 처리된 상기 웨이퍼(110)가 상기 챔버(100)로부터 나간 후, SF6과 O2플라즈마 혼합가스를 이용하여 상기 챔버(100)내에 부착된 생성물(160)을 식각하여 상기 배기펌프(140)로 배출한다. 이때, 상기 SF6플라즈마는 100∼300sccm이고, 상기 O2플라즈마는 10∼100sccm이다.After the etched wafer 110 exits the chamber 100 as shown in FIG. 4B, the product 160 attached to the chamber 100 is etched using SF 6 and O 2 plasma mixed gas. To be discharged to the exhaust pump 140. In this case, the SF 6 plasma is 100 to 300 sccm, the O 2 plasma is 10 to 100 sccm.

이어, 도면에는 도시하지 않았지만 생성물이 부착되지 않는 챔버(100)내에 피식각층을 갖는 웨이퍼(110)를 장착시킨 후, 식각공정을 실시한다.Subsequently, the wafer 110 having the layer to be etched is mounted in the chamber 100 to which the product is not attached although not shown in the drawing, and then an etching process is performed.

이상에서 설명한 바와 같이 본 발명의 플라즈마를 이용한 반도체 소자의 식각방법에 의하면, 포토 노광공정시 빛의 반사로 인한 불안정한 패턴 형성을 억제하기 위한 BARC막 식각 공정시 종래와 같은 원형이물이 발생하지 않는다.As described above, according to the etching method of the semiconductor device using the plasma of the present invention, the conventional circular foreign material does not occur in the BARC film etching process to suppress the unstable pattern formation due to the reflection of light during the photo exposure process. .

Claims (2)

TCP 방식을 이용한 플라즈마 식각방법에 있어서,In the plasma etching method using the TCP method, 상기 TCP 방식에 의해 BARC막 식각 공정시 발생하여 챔버의 벽 및 각종 부품에 부착된 생성물을 SF6과 O2플라즈마 혼합가스로 상기 생성물을 제거하는 단계와;Removing the product generated in the BARC film etching process by the TCP method and attached to the walls of the chamber and various components with a mixture of SF 6 and O 2 plasma; 상기 챔버내에 식각공정이 수행될 웨이퍼를 정착한 후, BARC 및 피식각층을 선택적으로 식각하는 단계를 포함하는 것을 특징으로 하는 플라즈마를 이용한 반도체 소자의 식각방법.And fixing the wafer to be etched in the chamber, and then selectively etching the BARC and the layer to be etched. 제 1 항에 있어서,The method of claim 1, 상기 SF6플라즈마는 100∼300sccm이고, 상기 O2플라즈마는 10∼100sccm인 것을 특징으로 하는 플라즈마를 이용한 반도체 소자의 식각방법.The SF 6 plasma is 100 to 300 sccm, the O 2 plasma is an etching method of a semiconductor device using a plasma, characterized in that.
KR1020020014957A 2002-03-20 2002-03-20 A method for etch of semiconductor device by using plasma KR20030075631A (en)

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