KR20030069775A - Semiconductor memory device capable of reading at high speed - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device capable of high-speed reading, and equalizes bit line pairs of a memory cell array MA # 00 to a sense amplifier band SAB # 0 disposed between two memory cell arrays MA # 00 and MA # 11. In addition to the equalizing circuits 20 and 21 for rising and the equalizing circuits 24 and 25 for equalizing the bit line pairs of the memory cell array MA # 11, the equalizing circuits 22 and 23 for initializing the sense amplifiers. It further includes. In the sense amplifier, any one of the word lines of the memory cell arrays MA # 00 and MA # 11 is initialized with a pulse-like equalization signal in response to an activation instruction. Therefore, the previously read data is held in the sense amplifiers 62 and 63, so that the data held in the sense amplifiers 62 and 63 can be read at high speed regardless of the activation of the word lines.

Description

Semiconductor memory capable of high-speed reading {SEMICONDUCTOR MEMORY DEVICE CAPABLE OF READING AT HIGH SPEED}

The present invention relates to a semiconductor memory device capable of high speed operation.

BACKGROUND OF THE INVENTION A semiconductor memory device mainly used in modern computers, for example, a synchronous dynamic random access memory (SDRAM) or the like, an active command (ACT command) for activating a word line and a read command (RD command) for reading a value stored in a sense amplifier. Is performed in combination with the " Since a burst operation for continuously outputting data of a plurality of column addresses is performed, the SDRAM can output data without interruption even if an RD command is continuously input to the same word line.

However, when writing and reading a memory cell connected to a separate word line, the desired word line must be activated after deactivating the currently active word line. Since the operation requires time, the data to be read is cut off midway, and the effective value of the transfer rate is lowered.

In order to prevent a drop in the transfer rate, in the SDRAM, a memory area is divided into parts that can be operated independently called a memory bank. However, when accessing memory cells of a plurality of row addresses in the same memory bank, the effect of dividing the memory area into memory banks has not been obtained.

Fig. 21 is a circuit diagram showing a configuration around a sense amplifier stage of a conventional SDRAM.

Referring to Fig. 21, memory cell arrays MA # 00 and MA # 11 sharing this sense amplifier stage are arranged on both sides of the sense amplifier stage SABX in which a plurality of sense amplifiers are arranged in a band shape. The memory cell array MA # 00 includes a plurality of memory cells Cel100, Cel110, Cel101, Cel111,... Arranged in a matrix shape. It includes. Each memory cell has a capacitor 16 having one end fixed to the cell plate potential Vcp at a constant potential, and a transistor 18 having a gate connected to the corresponding bit line and the other end of the capacitor 16 to a corresponding word line. It includes.

The sense amplifier band SABX includes a sense amplifier 962, an equalizing circuit 922, and a connection circuit 964, which correspond to bit line pairs BL0 and / BL0. The sense amplifier band SABX further includes a sense amplifier 963, an equalization circuit 923, and a connection circuit 965, corresponding to the bit line pairs BL1 and / BL1.

The sense amplifier band SABX conducts upon activation of the signal BLTG0, and connects the bit line pairs BL0, / BL0 to the equalizing circuit 922 and the sense amplifier 962, and deactivates the sense amplifier 962 and equalization upon deactivation of the signal BLTG0. A separation gate 960 that separates the rise circuit 922 from the bit line pairs BL0 and / BL0, and the bit line pairs BL1 and / BL1 are connected to the sense amplifier 963 and the equalizing circuit 923 in response to the activation of the signal BLTG0. And a separation gate 961 that separates the sense amplifier 963 and the equalizing circuit 923 from the bit line pairs BL1 and / BL1 according to the deactivation of the signal BLTG0.

The sense amplifier 962 and the equalizing circuit 922 are shared by the bit line pairs BL10 and / BL10 included in the memory cell array MA # 11.

For this reason, the sense amplifier band SABX connects the bit line pairs BL10 and / BL10 to the sense amplifier 962 and the equalizing circuit 922 in response to the activation of the signal BLTG1, and the sense amplifier 962 and equalization in response to the deactivation of the signal BLTG1. The separation gate 966 which separates the bit line pairs BL10 and / BL10 from the circuit 922, and the bit line pairs BL11 and / BL11 are connected to the sense amplifier 963 and the equalizing circuit 923 according to the activation of the signal BLTG1, The isolation gate 967 separates the bit line pairs BL11 and / BL11 from the sense amplifier 963 and the equalizing circuit 923 according to the deactivation of BLTG1.

Since the layout area of the sense amplifier is reduced in this manner, a separate sense amplifier configuration in which two sets of bit line pairs are provided on both sides of the sense amplifier is generally used.

The sense amplifier is controlled by the drive signals S0 and / S0. Since the signals S0 and / S0 perform independent operations for each block, it is assumed that the numbers of each block are assigned and distinguished. Thus, for example, the drive signal corresponding to block BLOCK0 is represented by S0, and the drive signal corresponding to block 1 is represented by S1.

Equalizing circuits 922 and 923 comprise a total of three transistors for connecting a pair of complementary bit lines according to signal BLEQ, and two transistors for coupling two bit lines constituting the pair of bit lines by conducting according to signal BLEQ to potential VBL. Two transistors.

The connection circuits 964 and 965 connect the corresponding bit lines to the local IO lines LIO and / LIO according to activation of the column select lines CSL0 and CSL1, respectively.

The data read in the local IO lines LIO and / LIO is transferred to the global IO lines GIO and / GIO by the connection circuit 968 conducting in accordance with the signal IOSW0 and applied to the input / output circuit 14.

Fig. 22 is a circuit diagram showing the configuration of a sense amplifier control circuit 1005 for generating an internal signal mainly used for control of a sense amplifier stage of a conventional SDRAM.

Referring to FIG. 22, the control circuit 1002 receives a command CMD and an address ADDRESS, and when an address ADDRESS corresponding to the memory block BLOCK0 is input when an active command ACT or a precharge command PRE is applied from the outside as a command, the control circuit 1002 receives the command CMD and the address ADDRESS. Outputs the signals ACT0 and PRE0 generated accordingly.

Since the memory block BLOCK0 is represented here, only the configuration related to the signal B0SEL for selecting the memory block BLOCK0 will be described below. For convenience of explanation, all the input commands assume bank 0.

The sense amplifier control circuit 1005 detects that the signal ACT0 is at the H level, and that the row addresses RA5 and RA6 are at the L level, and the gate circuit 1038 for activating the output at the L level and the gate circuit 1038. An inverter 1040 receiving the output and an SR latch circuit 1042 set in accordance with the output of the inverter 1040 and reset in accordance with the signal PRE0. From the Q output of the SR latch circuit 1042, B0SEL indicating the selection of the memory block BLOCK0 is output.

The sense amplifier control circuit 1005 has an output of the gate circuit 1012 and the gate circuit 1012 for activating the output to the L level when the signals B0SEL and ACT0 are both at the H level and the signal RA4 is at the L level. Inverter 1014 for receiving and inverting, delay circuit 1028 for receiving and delaying signal PRE0, and set according to the output of delay circuit 1028, reset in accordance with the output of inverter 1014, and reset signal BLTG1 from the Q output. It further includes an SR latch circuit 1016 to output.

The sense amplifier control circuit 1005 is set in accordance with the output of the NAND circuit 1018 receiving the signals RA4, B0SEL, and ACT0, the inverter 1020 which receives the output of the NAND circuit 1018, and inverts it, and the delay circuit 1028. SR latch 1022, which is reset in accordance with the output of the inverter 1020 and outputs the signal BLTG0 from the Q output, and is set in accordance with the output of the delay circuit 1028 and reset in accordance with the signal ACT0 to output the equalized signal BLEQ. SR latch circuit 1024 is further included.

The sense amplifier control circuit 1005 includes a delay circuit 1026 that receives the signal ACT0, a delay circuit 1030 that receives the output of the delay circuit 1026, and a NAND circuit that receives the output of the delay circuit 1030 and the signal B0SEL ( 1032, an inverter 1034 which receives and inverts the output of the NAND circuit 1032, and is set in accordance with the output of the inverter 1034 and reset in accordance with the output of the delay circuit 1028 to output the signal S0 from the Q output. And an SR latch circuit 1036 and an SR latch circuit 1044 that is set in accordance with the output of the delay circuit 1026 and reset in accordance with the signal PRE0 to output the signal RAE from the Q output.

Signal RAE is a signal for activating row decoder 1046 which decodes the row address. The row decoder 1046 activates any one of the word lines WL00 to WL7F in accordance with the activation of the signal RAE.

Fig. 23 is an operation waveform diagram for explaining the operation of the conventional sense amplifier stage SABX.

21 and 23, in the initial state of time t0, the signals BLTG0 and BLTG1 are all at the H level, and the isolation gates 960, 961, 966, and 967 correspond to the bits corresponding to the sense amplifiers 962 and 963. Connect to the line. At this time, since the signal BLEQ is at the H level, the equalizing circuits 922 and 923 are activated, and the bit line pairs are coupled to the potential VBL which is a potential of the power supply potential VDD.

The drive signals S0, / S0, S1, / S1 are set to the potential VBL. In addition, the column select lines CSL0 and CSL1 are at the L level, the connection circuits 964 and 965 are both in a non-conductive state, and the bit line and the local IO line LIO are separated.

At time t1, when the active command ACT is applied as the command CMD, both the signal BLEQ and the signal BLTG1 change from the H level to the L level. Equalizing circuits 922 and 923 are deactivated to stop the equalizing operation. In addition, the separation gates 966 and 967 separate the bit line pairs BL10, / BL10, BL11, / BL11 from the corresponding sense amplifiers.

After a predetermined delay time corresponding to the delay circuit 1026 of FIG. 22 has elapsed, the word line WL00 corresponding to the designated row address is activated. The transistors included in the memory cells Cel100 and Cel101 are turned on, and the potentials of the memory cells are read out to the corresponding bit lines.

Further, after the delay time corresponding to the delay circuit 1030 has elapsed, the drive signals S0 and / S0 become H level and L level, respectively, so that the sense amplifier is activated. The sense amplifier is activated to amplify the potential difference between the bit line pairs.

At time t2, the read command RD and the address 00 are input from the outside. By doing so, the column select line CSL0 corresponding to the address is activated at the H level, the connection circuit 964 is turned on, and the data amplified by the sense amplifier 962 is transferred to the local IO line pair. Subsequently, the signal IOSW0 is activated at the H level, and the connection circuit 968 is turned on so that the potential of the local IO line pair is transmitted to the input / output circuit 14 via the global IO line pair.

When the precharge command PRE is applied from the outside at time t3, the word line WL00 is deactivated to the L level immediately after that, and after the delay time corresponding to the delay circuit 1028 in Fig. 22 has elapsed, the signal BLTG1 is at the H level, the signal. BLEQ is set to H level, signals S0 and / S0 are equalized, respectively.

At time t4, the active command ACT and address 30 are input from the outside. Therefore, the word line WL30 is activated at the H level, and similarly to the operation at time t1 described above, data is read from the memory cell to perform a sense operation.

At time t5, the write command WRT and address 00 are input from the outside. Therefore, the signal IOSW1 and the column select line CSL0 are set to the H level so that the data applied from the input / output circuit 14 is written to the memory cell via the global IO line and the local IO line.

At time t6, the precharge command PRE is input again from the outside. Therefore, the word line WL30 is deactivated to the L level, the signals BLTG and BLEQ are set to the H level, and the potential of the bit line pair is set to the potential VBL. In addition, the drive signals S1 and / S1 are both set to the potential VBL to be in a standby state.

At time t8, the read command RD and address 01 are input from the outside. Therefore, the column select line CSL1 is activated at the H level, the signal IOSW0 is activated at the H level, and as in the case of the time t2, the potential amplified by the sense amplifier passes through the local IO line and the global IO line, and the input / output circuit 14 Is delivered.

As described above, when reading and writing are executed for memory cells in which the same bank is connected to different word lines, the command ACT, RD, PRE, or the command ACT, WRT, PRE three for each cycle of reading and writing. Commands will be required. In this case, since the time required for repetition of reading from successive addresses is required, the effective transfer rate of data is greatly reduced.

Countermeasures against this problem are conventionally disclosed in Japanese Patent Application No. 2000-217069, Japanese Patent Application Laid-Open No. 11-250653, Japanese Patent Application Laid-Open No. 11-317072, Japanese Patent Application Laid-Open No. 2000-137982, and the like. As shown below, several individuals have been proposed.

For example, if a latch circuit is provided adjacent to the sense amplifier, and the data of the sense amplifier is transmitted and held by the latch circuit, reading of previous data from the latch circuit can be performed at high speed even after the sense amplifier is initialized. However, the disadvantage is that the chip area is increased by arranging the latch circuit next to the sense amplifier.

Further, the technique disclosed in Japanese Patent Laid-Open No. 11-250653 has a configuration in which a plurality of sense amplifiers are arranged in a pair of bit line pairs. This technique also has a very large disadvantage of increasing chip area, and it is unlikely that a product using these techniques will be realized in practice.

In addition, the technique disclosed in Japanese Patent Laid-Open No. 11-317072 proposes two methods in a memory employing a shared sense amplifier method. The first method is to activate a plurality of word lines, one for each of a plurality of blocks that do not share sense amplifiers. Further, the second method uses the second word line when the second word line of the second block sharing the same sense amplifier as the first block including the first word line already selected is selected as the first word line. Equalization of the activation and sense amplifiers is done in parallel. However, the first method is equivalent to bank segmentation. In addition, there is a problem that the burden on the memory controller side becomes large because the row addresses to be managed by either of the first and second methods become very large.

The technique disclosed in Japanese Unexamined Patent Application Publication No. 2000-137982 is an improved patent for a memory that speeds up a cycle called FCRAM, but since the initialization of the sense amplifier is performed during reading, it is necessary to transfer burst-length data to the buffer in parallel. A mechanism is required, which also increases the disadvantage of increasing the chip area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having an improved effective transfer rate of data when reading or writing is successively performed for memory cells in which the same bank is connected to different word lines.

1 is a block diagram showing the structure of a semiconductor memory device according to a first embodiment of the present invention;

2 shows an array arrangement of the memory cell array 7;

3 is a circuit diagram showing the configuration around the sense amplifier stage of the semiconductor memory device 1 of the first embodiment;

4 is a diagram for explaining assignment of row addresses;

5 is a diagram for explaining assignment of column addresses;

6 is a circuit diagram showing the configuration of the sense amplifier control circuit 5 in FIG. 1;

7 is an operation waveform diagram for explaining the operation of the semiconductor memory device according to the first embodiment;

8 is a block diagram showing the configuration of the semiconductor memory device 1A according to the second embodiment;

FIG. 9 is a circuit diagram showing the configuration of the row address comparison section 8A in FIG. 8;

FIG. 10 is a circuit diagram showing the configuration of the register array 210 in FIG. 9;

11 is a circuit diagram for explaining the configuration of the sense amplifier control circuit 5A in FIG. 8;

12 is an operation waveform diagram for explaining the operation of the semiconductor memory device according to the second embodiment;

Fig. 13 is a diagram showing the arrangement of memory cell arrays of the semiconductor memory device of Example 3;

14 is a circuit diagram showing a detailed configuration of a memory cell array;

Fig. 15 is a block diagram showing the configuration of the sense amplifier control circuit 5B used in the third embodiment;

FIG. 16 is a circuit diagram showing the configuration of the reference timing generator 502 in FIG. 15;

FIG. 17 is a circuit diagram showing the configuration of the sense amplifier control unit 504 in FIG. 15;

FIG. 18 is a circuit diagram showing the configuration of the separation gate control unit 506 in FIG. 15;

19 is a circuit diagram showing a configuration of the IOSW control unit 508 in FIG. 15;

20 is an operation waveform diagram for explaining the operation of the semiconductor memory device of Example 3;

21 is a circuit diagram showing a configuration around a sense amplifier stage of a conventional SDRAM;

Fig. 22 is a circuit diagram showing the configuration of a sense amplifier control circuit 1005 for generating an internal signal mainly used for control of a sense amplifier stage of a conventional SDRAM.

23 is an operation waveform diagram for explaining the operation of the conventional sense amplifier stage SABX.

Explanation of symbols for the main parts of the drawings

1, 1A: semiconductor memory

2, 2A: control circuit

3: low decoder

4: column decoder

5, 5A, 5B: sense amplifier control circuit

6, 14: input / output circuit

7: memory cell array

8A: row address comparison section

9: memory control unit

16: capacitor

18: transistor

20-25: equalization circuit

60, 61, 66, 67: separation gate circuit

62, 63: sense amplifier

64, 65, 450, 451: connection circuit

76: pulse generator circuit

102, 104, 106, 124, 126, 144, 510, 512, 514, 516, 520, 522, 524, 526, 540, 542, 544, 546, 550, 552, 554, 796, 798, 800, 804: Delay circuit

112, 120, 134, 136, 142, 146, 152, 160, 166: latch circuit

122: drive circuit

147, 168, 404, 610, 612, 614, 710, 712, 714, 814: signal generating circuit

202: address comparison unit

204: internal command signal generator

206: control signal output unit

210: register array

330 to 334: address bit comparison unit

344, 346: resistance

502: reference timing generator

504: sense amplifier control unit

506: separation gate control unit

508: IOSW control unit

570, 571: sense amplifier control signal generation circuit

604: driving circuit

760, 762: pulse generating circuit

BL, / BL, BL0, BL1, BL00 to BL21, / BL0, / BL1, / BL00 to / BL21: Bit line

BLOCK0 to BLOCK2: Memory Block

CSL, CSL0 to CSL11: column select line

Cel100, Cel110, Cel101, Cel111: Memory Cells

G # 0 to G # 2: connection gate circuit

GIO, / GIO: Global IO Line

LIO0, / LIO0, LIO1, / LIO1: Local IO Line

MA # 00 ~ MA # 21: memory cell array

RD # 00 ~ RD # 21: Row Decoder

SAB # 0 to SAB # 2: Sense Amplifier Stand

SW: Switch Array

WL, WL00 to WL5F: Word line

SUMMARY OF THE INVENTION The present invention summarizes a semiconductor memory device comprising a first memory cell array, a second memory cell array, a sense amplifier stage, and a control circuit.

The first memory cell array includes a plurality of first memory cell groups, a first bit line pair, and a first word line group provided to intersect the first bit line pair. The second memory cell array includes a plurality of second memory cell groups, a second bit line pair, and a second word line group provided to intersect the second bit line pair. The sense amplifier stage includes a sense amplifier shared by the first and second bit line pairs. The control circuit controls the initialization of the sense amplifiers, the initialization of the first and second bit line pairs, and the activation of the first and second word line groups. The control circuit outputs a timing signal for transitioning any one of the first and second word line groups from the inactive state to the active state in accordance with the first command, and simultaneously initializes the first and second bit line pairs. And the sense amplifier is initialized for a predetermined period.

According to another aspect of the present invention, a semiconductor memory device includes a first memory block, a second memory block, a switch circuit, and a control circuit.

The first memory block includes a plurality of first memory cell groups arranged in a matrix shape, a first memory cell array including a first bit line pair and a first word line group provided to intersect the first bit line pair, and a matrix shape. A second memory cell array including a plurality of second memory cell groups arranged, a second bit line pair, and a second word line group provided to intersect the second bit line pair, and a second memory cell array; And a first sense amplifier stage including one sense amplifier.

The second memory block may include a plurality of third memory cell groups arranged in a matrix shape, a third memory cell array including a third bit line pair and a third word line group intersecting the third bit line pair, and in a matrix shape. A fourth memory cell array including a plurality of fourth memory cell groups arranged, a fourth bit line pair, and a fourth word line group provided to intersect the fourth bit line pair, and a third common to the third and fourth bit line pairs; And a second sense amplifier stage including the two sense amplifiers.

A switch circuit is provided between the first and second memory blocks to connect the second bit line pair and the third bit line pair. The control circuit performs control of the first and second sense amplifiers and the switch circuit, and allows data transmission between the first and second sense amplifiers.

Therefore, the main advantage of the present invention is that the data read by the sense amplifier is held until the word line activation instruction is made, so that the held data can be read at high speed without waiting for activation of the word line.

The above and other objects, features, aspects, advantages, and the like of the present invention will become more apparent from the following detailed embodiments described with reference to the accompanying drawings.

EMBODIMENT OF THE INVENTION Below, the Example of this invention is described in detail with reference to drawings. In addition, in the figure, the same code | symbol shows the same or equivalent part.

(Example 1)

Fig. 1 is a block diagram showing the structure of the semiconductor memory device according to the first embodiment of the present invention.

Referring to FIG. 1, the semiconductor memory device 1 receives a command CMD, an address ADDRESS, and data DATA from the memory control device 9. The semiconductor memory device 1 includes a control circuit 2, a row decoder 3, a column decoder 4, a sense amplifier control circuit 5, an input / output circuit 6, and a memory cell array 7. Equipped. When the command control signal CMD and the address signal ADDRESS are transmitted from the memory control device 9 to the semiconductor memory device, the semiconductor memory device 1 performs transmission and reception of data DATA between the memory control device 9. In reality, the memory cell array 7 is divided into a plurality of banks, and the address signal includes a bank address for designating a bank. However, for convenience of explanation, the bank address is omitted and only a command for bank 0 is applied. The case will be described later.

2 is a diagram showing the arrangement of the memory cell array 7.

2, the typical array structure for description is shown. Normally, the SDRAM has a plurality of independently operable banks, but in this specification, description will be made only for the configuration of one bank 0.

The memory cell array 7 includes memory blocks BLOCK0, BLOCK1, BLOCK2,... It includes. The memory block BLOCK0 includes the memory cell arrays MA # 00 and MA # 01 which share the sense amplifier band SAB # 0 and the sense amplifier band SAB # 0, and are arranged on both sides of the sense amplifier band SAB # 0.

The memory block BLOCK1 shares the sense amplifier stage SAB # 1 with the sense amplifier stage SAB # 1, and includes memory cell arrays MA # 10 and MA # 11 disposed on both sides of the sense amplifier stage SAB # 1.

The memory block BLOCK2 shares the sense amplifier stage SAB # 2 with the sense amplifier stage SAB # 2, and includes memory cell arrays MA # 20 and MA # 21 disposed on both sides of the sense amplifier stage SAB # 2.

The row decoder 3 is provided in correspondence with the memory cell array MA # 00 to execute the control of the word lines WL00 to WL0F, and the row decoder 3 is provided corresponding to the memory cell array MA # 01 and controls the word lines WL10 to WL1F. Is provided in correspondence with the row decoder RD # 01 for executing the control and the row decoder RD # 10 for controlling the word lines WL20 to WL2F provided for the memory cell array MA # 10 and the word line WL30 for the memory cell array MA # 11. In response to the row decoder RD # 11 for controlling the WL3F, the row decoder RD # 20 for the control of the word lines WL40 to WL4F, and the memory decoder for the memory cell array MA # 21. And row decoder RD # 21 for controlling word lines WL50 to WL5F.

That is, memory cell arrays exist on both sides so as to hold the sense amplifier stand therebetween. Each memory cell array has 16 word lines which are distinguished by row address signals RA0 to RA3. One memory block is divided left and right with the sense amplifier stage in the center and designated by the row address signal RA4. There are four memory blocks, designated by row address signals RA5, RA6. In each block, connection gate circuits G # 0 to G # 2 are provided for connecting the local IO line LIO to the global IO line GIO.

Although not shown in Fig. 2, the column address is set to 16 addresses designated by the signals CA0 to CA3. The column select lines CSL0 to CSLF, which are not shown, are orthogonal to the word line group and may be common to the plurality of memory cell arrays shown.

3 is a circuit diagram showing the configuration around the sense amplifier stage of the semiconductor memory device 1 according to the first embodiment.

Referring to FIG. 3, divided memory cell arrays MA # 00 and MA # 11 are arranged on both sides of the sense amplifier band SAB # 0.

The memory cell array MA # 00 includes a memory cell Cel100 provided corresponding to the intersection of the word line WL0 and the bit line BL00, a memory cell Cel110 provided corresponding to the intersection of the word line WL1 and the bit line / BL00, and the word line WL0; Memory cell Cel101 provided at the intersection of the bit line BL01 and memory cell Cel111 provided corresponding to the intersection of the word line WL1 and the bit line / BL01.

The memory cell Cel100 includes a capacitor 16 having one end coupled to a cell plate potential Vcp and a transistor 18 connected between a bit line corresponding to the other end of the capacitor 16 and a gate connected to a corresponding word line. do. The memory cells Cel110, Cel101, and Cel111 also have the same configuration as the memory cells Cel100, and the description of the configuration of each memory cell is not repeated.

The memory cell array MA # 11 has the same configuration as that of the memory cell array MA # 00, and description thereof will not be repeated.

The sense amplifier stage SAB # 0 includes the sense amplifiers 62 and 63, the equalizing circuits 20, 22 and 24, the separation gate circuits 60 and 66, and the connection circuit 64 provided corresponding to the sense amplifiers 62. ).

Equalizing circuit 22 equalizes to initialize the sense amplifier upon activation of signal SAEQ0. The potential VBL is applied to the equalizing circuit 22 as the equalizing potential.

The equalizing circuit 22 is connected between the bit line BL0 and the bit line / BL0 to receive the signal SAEQ0 as a gate, and is connected between the node to which the potential VBL is applied and the bit line BL0 to the gate. An N-channel MOS transistor 35 that receives the signal SAEQ0 and an N-channel MOS transistor 36 that is connected between the node to which the potential VBL is applied and the bit line / BL0 and receives the signal SAEQ0 as a gate.

The isolation gate circuit 60 is connected between a bit line BL0 and a bit line BL00 and receives an N-channel MOS transistor 30 which receives a signal BLTG0 as a gate, and is connected between a bit line / BL0 and a bit line / BL00 and a signal BLTG0 as a gate. It includes an N-channel MOS transistor 31 that receives. The isolation gate circuit 66 is connected between the bit line BL0 and the bit line BL10 and receives the N-channel MOS transistor 40 which receives the signal BLTG1 as a gate, and is connected between the bit line / BL0 and the bit line / BL10 and the signal BLTG1 as a gate. It includes an N-channel MOS transistor 41 receives.

The connection circuit 64 is connected between the local IO line LIO and the bit line BL0, and the N-channel MOS transistor 50 whose gate is connected to the column select line CSL0, and is connected between the local IO line / LIO and the bit line / BL0. The gate includes an N-channel MOS transistor 51 connected to the column select line CSL0.

Although the equalizing circuits 20 and 24 receive the signal BLEQ in place of the signal SAEQ0, the internal circuit configuration is the same as that of the equalizing circuit 22, and thus description thereof will not be repeated. However, since the bit line pairs BL0 and / BL0 equalized by the equalization circuit 22 have smaller capacities than the bit lines BL00, / BL00, BL10, and / BL10 to which the memory cell array is connected, the equalization circuit 22 The size of the three transistors included is small compared to the size of the transistors included in the equalizing circuits 20 and 24.

The sense amplifier stage SAB # 0 further includes equalization circuits 21, 23, 25, isolation gate circuits 61, 67, and a connection circuit 65 provided corresponding to the sense amplifier 63.

The equalization circuit 23 is connected between the bit line BL1 and the bit line / BL1 and receives the signal SAEQ0 as a gate, and is connected between the node to which the potential VBL is applied and the bit line BL1 to the gate. An N-channel MOS transistor 38 that receives the signal SAEQ0 and an N-channel MOS transistor 39 that is connected between the node to which the bit line VBL is applied and the bit line / BL1 and receives the signal SAEQ0 as a gate.

The isolation gate circuit 61 is an N-channel MOS transistor 32 connected between the bit line BL1 and the bit line BL01 and receiving the signal BLTG0 as a gate, and connected between the bit line / BL1 and the bit line / BL01 and the signal BLTG0 as a gate. It includes an N-channel MOS transistor 33 receives. The isolation gate circuit 67 is an N-channel MOS transistor 42 connected between the bit line BL1 and the bit line BL11 to receive the signal BLTG1 as a gate, and is connected between the bit line / BL1 and the bit line / BL11 to the gate signal BLTG1. It includes an N-channel MOS transistor 43 receives.

The connection circuit 65 is connected between the local IO line LIO and the bit line BL1, and the N-channel MOS transistor 52 whose gate is connected to the column select line CSL1, and is connected between the local IO line / LIO and the bit line / BL1. The gate includes an N-channel MOS transistor 53 connected to the column select line CSL1.

Although the equalizing circuits 21 and 25 receive the signal BLEQ in place of the signal SAEQ0, the internal circuit configuration is the same as that of the equalizing circuit 23, and thus description thereof will not be repeated. However, since the bit line pairs BL1 and / BL1 equalized by the equalization circuit 23 have smaller capacities than the bit lines BL01, / BL01, BL11, and / BL11 to which the memory cell array is connected, the equalization circuit 23 The size of the three transistors included is smaller than the size of the transistors included in the equalizing circuits 21 and 25.

The data read by the sense amplifiers to the local IO lines LIO and / LIO is read to the global IO lines GIO and / GIO via the gate circuit G # 0 and transferred to the input / output circuit 14.

The gate circuit G # 0 is connected between the local IO line LIO and the global IO line GIO and receives the gate signal IOSW0, and is connected between the local IO line / LIO and the global IO line / GIO to the gate. And an N-channel MOS transistor 11 that receives the signal IOSW0.

Next, address assignment of the semiconductor memory device 1 will be described.

4 is a diagram for explaining assignment of row addresses.

Referring to Fig. 4, address signals A0 to A6 applied from the outside are recognized internally as row addresses RA0 to RA6 when they are applied together with a predetermined active command ACT. The word lines in the memory cell array are selected by the row address signals RA0 to RA3. For example, if (RA3, RA2, RA1, RA0) is (0000), the word line WL (0) is designated; if (0001), the word line WL (1) is specified, and (1111), the word line WL (F) is specified. Is specified.

In the row address signal RA4, either one of the left and right areas in the block is designated. When 0 is applied as the row address signal RA4, the left area is designated, and when 1 is applied, the right area is specified.

The row address signals RA5 and RA6 are used for block designation. For example, if (RA6, RA5) = (00), block BLOCK0 is specified, and if (RA6, RA5) = (01), block 1 is specified.

5 is a diagram for explaining assignment of column addresses.

Referring to Fig. 5, when addresses A0 to A6 are applied from the outside together with the read command RD or the write command WRT, they are recognized as the column addresses CA0 to CA6. The column address signals CA0 to CA3 are signals for selecting column select lines. For example, when (0000) is applied as (CA3, CA2, CA1, CA0), the column select line CSL (0) is selected, and when (0001) is applied, the column select line CSL (1) is selected, and (1111) When applied, the column select line CSL (F) is selected.

In the present invention, the column address signal CA4 is used for designation for directly reading a signal from a sense amplifier without driving a word line. If column address signal CA4 is 0, normal operation is specified, and if column address CA4 is 1, direct reading from the sense amplifier is specified.

The column address signals CA5 and CA6 are signals for specifying the block in which the sense amplifier to read exists. If (CA6, CA5) = (00) is applied while the signal CA4 is set to 1, data is read from the sense amplifier of the block BLOCK0. Further, when (CA6, CA5) = (01) is applied, data is read directly from the sense amplifier of block 1.

FIG. 6 is a circuit diagram showing the configuration of the sense amplifier control circuit 5 in FIG. 1. Referring to Fig. 6, a configuration necessary for control of selecting a block BLOCK0 is shown.

The sense amplifier control circuit 5 includes a signal generation circuit 147 which receives the internal address signal IADDRESS and the signal RD0 from the control circuit 2 and outputs a signal B0SEL for selecting the block BLOCK0.

The signal generation circuit 147 includes an OR circuit 154 that receives the row address signals RA5, RA6, a gate circuit 148 that receives the outputs of the signals CA4, RD0, and an OR circuit 154, and an output of the gate circuit 148. Inverter 150 for receiving and inverting, and SR latch circuit 152 receives the inverter 150 as a set input and receives the clock signal CLK as a reset input. The gate circuit 148 is a circuit for activating the output to the L level when the signals CA4 and RD0 are at the H level and the output of the OR circuit 154 is at the L level.

The signal generating circuit 147 includes a gate circuit 156 that receives the output of the delay circuit 102 and the output of the OR circuit 154, an inverter 158 that receives the output of the gate circuit 156, and inverts the inverter. SR latch circuit 160 which receives the output of 158 as a set input and receives the clock signal CLK as a reset input, and OR circuit 162 which receives the output of SR latch circuits 152 and 160 and outputs signal B0SEL. . The gate circuit 156 is a circuit that activates the output to the L level when the output of the delay circuit 102 is at the H level and the output of the OR circuit 154 is at the L level.

The sense amplifier control circuit 5 includes delay circuits 102, 104, 106 connected in series to receive the signal ACT0 applied from the control circuit 2.

The sense amplifier control circuit 5 includes an SR latch circuit 112 that receives the signal ACT0 as a set input and receives the output of the delay circuit 104 as a reset input, and a NAND circuit that receives the output of the delay circuit 106 and the signal B0SEL ( 108, an inverter 110 that receives and inverts the output of the NAND circuit 108, a NAND circuit 114 that receives the outputs of the signals B0SEL and the SR latch circuit 112, and an output of the NAND circuit 114 Inverter 116 is further included.

The sense amplifier control circuit 5 includes a delay circuit 124 for delaying the signal PRE0 output from the control circuit 2, a delay circuit 126 for delaying the signal PALL output from the control circuit 2, and a delay circuit. OR circuit 128 receiving the output of 124 and the output of delay circuit 126, delay circuit 144 for receiving and delaying the output of delay circuit 126, and set according to the output of delay circuit 126 And an SR latch circuit 146 that is reset in accordance with the output of delay circuit 144.

The sense amplifier control circuit 5 is set according to an OR circuit 118 that receives the output of the inverter 116 and the SR latch circuit 146 and outputs the signal SAEQ0, and is set in accordance with the output of the inverter 110 and the OR circuit ( SR latch circuit 120 resets according to the output of 118, and the drive circuit 122 for driving the sense amplifier driving signals S0, / S0 in accordance with the output of the SR latch circuit 120.

The sense amplifier control circuit 5 includes a gate circuit 130 that receives the output of the delay circuit 104 and the signals B0SEL and RA4, an inverter 132 that inverts the output of the gate circuit 130, and an inverter 132. And an SR latch circuit 136 that outputs a signal BLTG0 that is set in accordance with the output of and reset in accordance with the output of the OR circuit 128. The gate circuit 130 is a circuit in which the output of the delay circuit 104 and the signal B0SEL are at the H level, and the output is at the L level when the signal RA4 is at the L level.

The sense amplifier control circuit 5 includes a NAND circuit 138 that receives the output of the delay circuit 104 and the signals B0SEL and RA4, an inverter 140 that receives and inverts the output of the NAND circuit 138, and an inverter 140. The SR latch circuit 142 is set in accordance with the output of < RTI ID = 0.0 > OR < / RTI > and outputs the signal BLTG1, and is set in accordance with the output of the OR circuit 128 and reset in accordance with the signal ACT0 to reset the signal BLEQ. It further includes an SR latch circuit 134 to output.

The sense amplifier control circuit 5 is set according to the output of the OR circuit 164 receiving the signals PRE0 and PALL and the delay circuit 102 and reset according to the output of the OR circuit 164 to output the signal RAE. The circuit 166 further includes a signal generation circuit 168 for outputting the signal IOSW0 in accordance with the internal address signal IADDRESS and the signals WRT0 and RD0.

Signal RAE activates row decoder 3. When activated, the row decoder 3 activates any one of the word lines WL00 to WL7F in accordance with the row address RA.

7 is an operation waveform diagram for explaining the operation of the semiconductor memory device of the first embodiment.

In addition, for simplicity, the operation is performed on one bank address. In addition, the burst length is set to one clock.

3 and 7, in the initial state of time t0, the signals BLTG0 and BLTG1 are both at L level. Therefore, the transistors 30 to 33 and 40 to 43 are both in a non-conductive state.

Since the signal BLEQ is at the H level, the equalizing circuits 20, 21, 24, and 25 are activated, and the bit line pairs are initialized to the potential VBL of the power supply potential VDD. The sense amplifier drive signals S0 and / S0 are both set to the potential VBL, and the sense amplifiers 62 and 63 are in an inactive state. In addition, since the signal SAEQ0 is at the L level, the equalizing circuits 22 and 23 are deactivated. In addition, since the column select lines CSL0 and CSL1 are at the L level, the transistors 50 to 53 are in a non-conductive state.

At time t1, the active command ACT is input as the command signal CMD and 00 is input as the address signal ADDRESS. Then, the signal BLEQ is changed from the H level to the L level. The equalization circuits 20, 21, 24, 25 are then deactivated. In addition, the signal SAEQ0 is changed to the H level, and the signals S0 and / S0 are both set to the potential VBL. After a period corresponding to the delay circuit 102 of FIG. 6, the row decoder 3 is activated so that the word line WL00 corresponding to the designated row address is changed from the L level to the H level.

When the word line WL00 is activated, the transistors included in the memory cells Cel100 and Cel101 are turned on so that the accumulated charge of the capacitor 16 is transferred to the bit lines BL00 and BL01.

Further, after a predetermined time corresponding to the delay circuit 104, the signal BLTG0 is changed to the H level and the signal SAEQ0 is changed to the L level.

In other words, while the signal SAEQ0 is in the form of a pulse and is at the H level, the equalizing circuits 22 and 23 operate for a predetermined period of time to perform initialization of the sense amplifier. When the signal BLTG0 is changed from the L level to the H level, the data of the bit line pair is transferred to the sense amplifiers 62 and 63 via the transistors 30 to 33. Thereafter, the signals S0 and / S0 are activated at H level and L level, respectively, so that the sense amplifiers 62 and 63 amplify the potential of the bit line pair.

At time t2, the read command RD and the address 00 are input from the outside. Then, the column select line CSL0 is activated in a pulse shape to conduct the transistors 50 and 51. Therefore, the potential of the sense amplifier 62 is transmitted to the local IO line pair. Then, the signal IOSW0 is at the H level, and the transistors 10 and 11 are turned on so that the potentials of the local IO lines LIO and / LIO are transmitted to the input / output circuit 14 via the global IO lines GIO and / GIO.

At time t3, the precharge command PRE is input from the outside. Then, the word line is deactivated to the L level in accordance with the deactivation of the signal RAE of FIG. 6. Further, after the delay time corresponding to the delay circuit 124 has elapsed, the signal BLEQ changes to the H level, and the signal BLTG0 changes to the L level. Then, the potential of the bit line pair returns to the potential VBL. However, since the transistors 30 to 33 are in a non-conductive state, the sense amplifiers 62 and 63 are maintained when the signals S0 and / S0 are maintained at H and L levels, respectively. The state can be maintained while holding the data read from the memory cell.

Next, at time t4, the active command ACT and address 30 are input from the outside. Therefore, the word line WL30 is activated from the L level to the H level, data of the corresponding memory cell is read out to the bit line, and the sense operation is performed after the sense amplifier of the block BLOCK1 is initialized for a predetermined period by the signal SAEQ1.

At time t5, the write command WRT and address 00 and write data are input from the outside. Therefore, the signal IOSW1 is activated at the H level, and the column select line CSL0 is activated at the H level. Then, data from the input / output circuit 14 is written to the corresponding memory cell via the global IO line GIO, the local IO line LIO, and the bit line BL.

At time t6, address 11 is input from the outside along with the read command RD. The upper bit A4 of the address is used to designate to directly read data held in the sense amplifier. That is, reading from the sense amplifier corresponding to the block BLOCK0 and column address CA = 1 is specified. For this reason, as the column select line CSL1 is activated at the H level and the signal IOSW0 is activated at the H level, the holding data of the sense amplifier 63 passes through the local IO line LIO and the global IO line GIO to the input / output circuit 14. Is passed to.

At time t7, the write command WRT and address 01 and write data are input from the outside. Thus, the signal IOSW1 is activated at the H level, and the column select line CSL1 is activated at the H level. Then, data from the input / output circuit 14 is written to the corresponding memory cell via the global IO line GIO, the local IO line LIO, and the bit line BL.

As can be seen by comparing the operation waveform diagrams, in the conventional operation, as described with reference to Fig. 23, when the memory cells connected to the plurality of word lines are accessed, the precharge command PRE and the active command ACT are read command RD or the like. It is needed every time before the write command WRT. However, in the operation of the semiconductor memory device of the first embodiment shown in Fig. 7, the second and subsequent active commands ACT related to the read operation are not necessary, and only reading data held in the sense amplifier is sufficient.

In this embodiment, since the burst length is one clock, the latency of the read operation is greatly influenced. However, when the burst length is long, the effect of directly reading data from the sense amplifier is further enhanced.

In addition, although the access to another block is a write operation, it can be operated in the same manner in the case of the read operation, that is, even when the read operation is executed at time t5.

As described above, in the semiconductor memory device of the first embodiment, even when access is concentrated in the same bank, the memory cell connected to the word line once activated by holding in the sense amplifier which reads from the word line with the active command once Can be read in one command. Therefore, it becomes possible to keep the execution transmission rate high.

In addition, since the penalty in area of the present invention is small, it is possible to manufacture and separate the standard memory and the memory according to the present invention together on the same chip. In addition to invalidating the extended address CA4 inputted together with the read command RD, it is also easy to change the equalization timing of the sense amplifier to start when the precharge command enters as in the conventional memory.

As a method of making and dividing a standard memory and a memory according to the present invention, options for metal wiring in a wafer process, a method for executing a program by a laser trimmer, etc. Potential fixation and the like.

It is also possible to configure to select whether to operate as a standard memory or a memory according to the present invention by a register set command after power-up.

As described above, in the semiconductor memory device of the first embodiment, the bit line pair is initialized after the word line is unselected, but the sense amplifier is not yet initialized at that time. The sense amplifier is initialized when any word line in the memory block corresponding to that sense amplifier is next activated. As a result, the sense amplifier of each memory block holds the data of the memory cells connected to the word lines activated last time. Therefore, when reading the sustain data, it is possible to read directly from the sense amplifier without activating the word line. This readout is very fast since it does not follow the low system operation.

In conventional DRAM, the word line can be activated for a long time in anticipation of a paging operation, and the data can be held in the sense amplifier while waiting. However, in the case of selecting another word line, the word line is activated after inputting the precharge command PRE. Since the command ACT must be input, a delay occurs as long as the time required for precharging.

In the first embodiment, the word lines are deactivated at the same timing as the standard memory, and the bit line pairs that have a large capacity and require time to equalize are already equalized, so the timing at which any memory block inputs the active command ACT is equal to that of the standard memory. Similarly good. Compared with the conventional DRAM, an equalization circuit dedicated to the sense amplifier is required and the equalization of the sense amplifier starts after the word line is activated. However, since the capacity of the sense amplifier is small, the time penalty is small. In addition, it is thought that the area of an equalizing circuit does not become a big loss.

(Example 2)

In the first embodiment, the memory controller has to manage row addresses corresponding to data held in the sense amplifiers of the semiconductor memory device. Therefore, there is a problem that the functions required for the memory control device become very complicated, and the burden on the memory control device becomes excessively large. Example 2 relates to the countermeasure of this problem.

8 is a block diagram showing the configuration of the semiconductor memory device 1A according to the second embodiment. Referring to FIG. 8, the semiconductor memory device 1A of the second embodiment includes a control circuit 2A instead of the control circuit 2 in the configuration of the semiconductor memory device 1 shown in FIG. Instead of the control circuit 5, the sense amplifier control circuit 5A is included. The semiconductor memory device 1A differs from the semiconductor memory device 1 in that the semiconductor memory device 1A further includes a row address comparison unit 8A. Since other configurations are the same, the description is not repeated.

In the semiconductor memory device 1A of the second embodiment, a row address corresponding to a word line currently activated and a row address corresponding to a memory cell in which a sense amplifier holds data are held therein. The semiconductor memory device 1A has a function of comparing a row address designated from the outside with a row address held by them and notifying the result to the outside. This eliminates the need for the memory control device side to manage the address of the activation / deactivation of the word line of the memory, thereby enabling proper control.

In the semiconductor memory device 1A shown in the second embodiment, the control method is different from the general SDRAM.

First, there is no precharge command except for the precharge all command PALL. The input of the command SEN is necessarily required two clocks before the read command RD. The active command ACT is necessarily required two clocks before the write command WRT.

The input of the command ACT or the command SEN is necessary because there are a plurality of active rows in the same bank address, and therefore the row address corresponding to the read command RD / write command WRT needs to be clarified.

The active command ACT is a command for necessarily activating a word line and is used during a write operation. The word line once activated assumes a continuous write operation (burst write) and remains active until another word line in the same memory block is next activated.

The command SEN is similar in usage to the active command ACT, but does not activate the word line when the data of the memory cell corresponding to the row address is already held in the sense amplifier. This command SEN is used during the read operation. The word line activated at the command SEN is automatically deactivated after the sense operation is completed, and the bit line pair is equalized. Since the word line is in an inactive state after the data reading is finished, access to the memory cell is not possible.

When the precharge all command PALL is entered, all sense amplifiers are returned to their initial state.

The row address comparison section 8A shown in FIG. 8 holds the row address in the activated state and the row address holding data in the sense amplifier. When a row address is input from the outside, the row address comparison section 8A compares the stored address information with the input address information. When a separate row address in the memory block corresponding to the row address is currently active, the signal IntBUSY is returned to the control circuit 2A. On the other hand, the row address comparison section 8A returns the signal Ready to the control circuit 2A when the row address input to the memory cell in which data is held in the sense amplifier corresponds. When the busy signal IntBUSY is applied from the row address comparison section 8A, the control circuit 2A outputs the signal BUSY to the outside and prompts the memory control device 9 to re-enter the command.

FIG. 9 is a circuit diagram showing the configuration of the row address comparison section 8A in FIG.

Referring to FIG. 9, the row address comparison unit 8A compares the address comparison unit 202 for comparing the input row address with the row address holding therein, and the internal command signals ACT0 and PRE0 according to the signals SENREQ and ACTREQ. And an internal command signal generator 204 for outputting, a control signal output unit 206 for outputting a control signal in accordance with the output of the address comparator 202 and the internal command signal generator 204.

The address comparison unit 202 includes register arrays 210 to 213 corresponding to the memory blocks BLOCK0 to BLOCK3, respectively. The internal command signal generator 204 includes a NAND circuit 222 that receives signals SEN0REQ and HIT, an inverter 224 that receives and inverts the output of the NAND circuit 222, and a three-input that receives signals ACT0REQ, HIT, and WLON. NAND circuit 226, inverter 228 for inverting output of NAND circuit 226, OR circuit 230 for receiving output of inverter 224 and output of inverter 228, and OR circuit 230 And an SR flip-flop circuit 232, which is set according to the output of P and reset according to the clock signal CLK to output the signal Ready.

The internal command signal generator 204 includes a gate circuit 234 receiving signals SEN0REQ, WLON, and HIT, an inverter 236 for inverting the output of the gate circuit 234, and a gate circuit receiving signals ACT0REQ, WLON ( 238, an inverter 240 that receives the output of the gate circuit 238 and inverts it, an OR circuit 242 that receives the output of the inverter 236 and the output of the inverter 240, and an output of the OR circuit 242. And an SR flip-flop circuit 244 that is set according to the < RTI ID = 0.0 > and reset < / RTI >

The gate circuit 234 detects that the signal SEN0REQ is at the H level, the signal WLON is at the L level, and the signal HIT is at the L level, and activates the output to the L level. Further, the gate circuit 238 detects that the signal ACT0REQ is at the H level and the signal WLON is at the L level, thereby activating the output to the L level.

The internal command signal generator 204 receives the output of the clock inverter 246 by activating according to the clock signal / CLK and inverting the output of the inverter 236 and activating according to the clock signal CLK. A clock inverter 248 to invert, a clock inverter 250 activated according to the clock signal / CLK to receive and output the output of the clock inverter 248, and a clock inverter 250 activated according to the clock signal CLK to activate the output of the clock inverter 250. It further includes a clock inverter 252 for receiving and inverting.

The internal command signal generator 204 includes a gate circuit 254 that receives signals SEN0REQ, WLON, and HIT, an inverter 256 that receives and inverts the output of the gate circuit 254, and a gate that receives signals ACT0REQ, HIT, and WLON. The circuit 258 further includes an inverter 260 that receives the output of the gate circuit 258 and inverts it, and an OR circuit 262 that receives the output of the inverter 256 and the output of the inverter 260.

The gate circuit 254 detects that both the signal SEN0REQ and the signal WLON are at the H level, and the signal HIT is at the L level, thereby activating the output to the L level. The gate circuit 258 detects that the signals ACT0REQ and WLON are both at the H level, and the signal HIT is at the L level, thereby activating the output to the L level.

The internal command signal generator 204 includes a gate circuit 264 that receives the signal INBURST and an output of the OR circuit 262, an inverter 266 that receives the output of the gate circuit 264, and reverses the output of the gate circuit 264, and an inverter 266. And an SR flip-flop circuit 268 that is set according to the output and reset in accordance with the clock signal CLK. The gate circuit 264 detects that the signal INBURST is at the L level and that the output of the OR circuit 262 is at the H level, and activates the output to the L level.

The internal command signal generator 204 includes the NAND circuit 270 that receives the output of the OR circuit 262 and the signal INBURST, the inverter 272 that inverts the output of the NAND circuit 270, and the inverter 272. The SR flip-flop circuit 274 that is set according to the output and reset according to the clock signal CLK to output the signal NOP0, receives the output of the clock inverter 252 and the output of the SR flip-flop circuit 268, and outputs the signal PRE0. It further includes an OR circuit 276.

The control signal output unit 206 includes four input OR circuits 282 for receiving signals HIT0 to HIT3 and outputting signals HIT, four input OR circuits 284 for receiving signals INBURST0 to INBURST3 and outputting signals INBURST; Four input OR circuits 286 for receiving the signals WLON0 to WLON3 and outputting the signal WLON, and three input OR circuits 288 for receiving the signals ACT0, PRE0 and NOP0 and outputting the signal IntBUSY.

FIG. 10 is a circuit diagram showing the structure of the register array 210 in FIG.

Referring to FIG. 10, the register array 210 includes a NAND circuit 302 that receives signals ACT0 and B0SEL, an inverter 304 that receives and inverts the output of the NAND circuit 302, and an output of the inverter 304. SR flip-flop circuit 306 that is set and reset in accordance with signal BLEQ0, NAND circuit 308 that receives the output of SR flip-flop circuit 306 and signal B0SEL, and the output of NAND circuit 308 receives and inverts the signal. An inverter 309 for outputting WLON0.

The register array 210 receives the output of the inverter 304 as one input and receives the row address signals RA0 to RA4 as the other input, respectively, of the NAND circuits 310 to 314 and the NAND circuits 310 to 314. SR flip-flop circuits 320 to 324 each set in accordance with the output. The SR flip-flop circuits 320 to 324 are all reset in accordance with the signal SAEQ0.

The resistor array 210 includes a resistor 344 connected between the power supply node and the node N11, a resistor 346 connected between the ground node and the node N00, an inverter 342 which receives and inverts a signal B0SEL, and a node N11. And an address bit comparison unit 330 to 334, which are connected in parallel between the node and the node N00 and compare the row address signals RA0 to RA4 with values previously input, respectively.

The address bit comparison unit 330 includes P channel MOS transistors 352, 354, and 356 connected in series between a power supply node and a node N00, and an N channel MOS transistor 358 connected in series between a node N11 and a ground node. 360, 362).

The output of the SR flip-flop circuit 320 is applied to the gate of the P-channel MOS transistor 352, and the input row address signal RA0 is applied to the gate of the P-channel MOS transistor 354, and the P-channel MOS transistor 356 is applied thereto. The output of the inverter 342 is applied to the gate of. A signal B0SEL is applied to the gate of the N-channel MOS transistor 358, an output of the SR flip-flop circuit 320 is applied to the gate of the N-channel MOS transistor 360, and an input is input to the gate of the N-channel MOS transistor 362. The row address signal RA0 is applied.

The row address signals RA1 to RA4 are applied to the address bit comparison units 331 to 334 instead of the row address signals RA0 to be input, and the outputs of the SR flip flop circuits 321 to 324 respectively instead of the output of the SR flip flop circuit 320. Although this point is different from that of the address bit comparison unit 330, since the internal structure is the same as that of the address bit comparison unit 330, the description is not repeated.

The register array 210 detects that the node N11 is at the H level and the node N00 is at the L level, thereby inverting the output of the gate circuit 348 to output the signal HIT0 by inverting the output of the gate circuit 348. An inverter 350 is included.

The register array 210 receives and inverts the OR circuit 364 receiving the signal RD0 and the signal WRT0, the NAND circuit 366 receiving the output of the OR circuit 364 and the signal B0SEL, and the output of the NAND circuit 366. Inverter 368, clocked inverters 370 to 380 connected in series receiving the output of inverter 368, and set according to the output of inverter 368 and reset in accordance with the output of clock inverter 380 to signal INBURST0. SR flip-flop circuit 382 for outputting the same.

The clock inverters 370, 374, 378 are activated when the clock signal CLK is at the H level. On the other hand, the clock inverters 372, 376, and 380 are activated when the clock signal / CLK is at the H level.

9 and 10, the operation of the row address comparison section 8A will be briefly described.

First, when ACT is input as a command from the memory control device 9, the control circuit 2A activates the signal ACTREQ for the row address comparison section. In Fig. 9, the signal ACT0REQ is activated corresponding to the block BLOCK0. When the signal HIT is at the H level and the signal WLON is at the H level, since the corresponding word line is activated, the row address comparator activates the signal Ready to wait for the write command WRT continuously transmitted from the memory control device 9. do.

On the other hand, when the signal WLON is at the L level, the word line needs to be activated, so the signal ACT0 is activated by the SR flip-flop circuit 244.

When the signal HIT is at the L level and the signal WLON is at the H level, the busy signal BUSY is output because the designated memory block is in use. In this case, when signal INBURST is at L level, signal PRE0 is activated at the same time, but when signal INBURST is at H level, signal PRE0 is not activated and precharge is not executed.

Next, the case where the command SEN is applied from the memory control device 9 before the read command will be described. When the command SEN is applied, the control circuit 2A transmits the row addresses RA0 to RA4 and the signal SEN0REQ to the row address comparison section 8A. When the row addresses match and the signal HIT becomes H level, the row address comparison section 8A outputs the signal Ready and continues to wait for the read command RD to be transmitted.

On the other hand, when the signal HIT is at the L level and the signal WLON is at the L level, the word line needs to be activated. Therefore, the signal ACT0 is activated to activate the word line, and the signal PRE0 is automatically activated two clocks later. To disable the word line.

When the signal HIT is at L level and the signal WLON is at H level, the signal BUSY is activated because the memory block is in use. At this time, when the signal INBURST is L level, the signal PRE0 is activated at the same time. If the signal INBURST is at the H level, the signal PRE0 is not activated and no precharge is performed.

FIG. 11 is a circuit diagram for explaining the configuration of the sense amplifier control circuit 5A in FIG. 8.

Referring to FIG. 11, the control circuit 2A outputs signals ACT0REQ, SEN0REQ, RD0, WRT0, and PALL in accordance with a command CMD input from the outside. For convenience of explanation, the bank address is omitted, and the command is shown for bank O. In FIG.

The sense amplifier control circuit 5A further includes, in the configuration of the sense amplifier control circuit 5 shown in FIG. 6, a NAND circuit 402 that receives the signal B0SEL and the signal PRE0, and the output of the NAND circuit 402 is delayed. The difference is applied to the circuit 124 and the OR circuit 164.

The sense amplifier control circuit 5A differs from the sense amplifier control circuit 5 in that the sense amplifier control circuit 5A includes a signal generator circuit 404 instead of the signal generator circuit 147. Since the structure of the other part of the sense amplifier control circuit 5A is the same as that of the sense amplifier control circuit 5 of FIG. 6, description is not repeated.

The signal generation circuit 404 includes an OR circuit 406 that receives signals ACT0REQ and SEN0REQ, an OR circuit 408 that receives the outputs of the signal Ready and delay circuits 102, and an OR circuit 410 that receives signals RA5 and RA6. And a gate circuit 412 that receives the outputs of the OR circuits 408 and 410, an inverter 416 that receives and inverts the outputs of the gate circuits 412, and a clock signal CLK that is set in accordance with the output of the inverter 416. SR flip-flop circuit 418 that is reset according to the < Desc / Clms Page number 12 >

The gate circuit 412 detects that the output of the OR circuit 408 is at the H level and the output of the OR circuit 410 is at the L level, thereby activating the output to the L level.

The signal generation circuit 404 is a gate circuit 414 that receives the outputs of the OR circuits 410 and 406, an inverter 420 that inverts the output of the gate circuit 414, and an output of the inverter 420. And an SR flip-flop circuit 422 that is set and reset in accordance with the clock signal CLK. The gate circuit 414 detects that the output of the OR circuit 410 is at the L level and the output of the OR circuit 406 is at the H level, and activates the output to the L level.

The signal generating circuit 404 includes four clock inverters 424 to 430 connected in series to receive the output of the SR flip-flop circuit 418, the outputs of the SR flip-flop circuits 418 and 422, and the clock inverter 430. And an OR circuit 432 of three inputs that receives the output of < RTI ID = 0.0 > The clock inverters 424 and 428 are activated when the clock signal / CLK is at the H level to perform the inversion operation. On the other hand, the clock inverters 426 and 430 activate when the clock signal CLK is at the H level to perform the inversion operation.

12 is an operational waveform diagram for describing the operation of the semiconductor memory device of the second embodiment.

Referring to Fig. 12, at time t1, the command SEN and address 0 are input from the outside. Since it is the first input, no data is retained in the sense amplifier. For this reason, word lines are actually activated. That is, word line WL00 is selected among the word lines to be activated at the H level.

Thereafter, as in the case of the first embodiment, the sense amplifier is equalized in a pulse shape in accordance with the signal SAEQ0, and the sense operation is performed after the signal BLTG0 is activated from the L level to the H level. When the sense operation is completed, the word line activated at the command SEN is automatically deactivated, and the equalization of the bit line pair is started as the signal BLEQ0 is activated.

At time t2, the read command RD and address 00 are input. As a result, the column select lines CSL0, CSL1, CSL2, and CSL3 are sequentially activated to read out data held in the sense amplifier to the outside.

At time t3, the command SEN and address 00 are input again.

Since the data of the memory cell corresponding to the address 00 is already held in the sense amplifier, the row address comparison section 8A activates the signal Ready for the control circuit 2A. In this case, the row system does not need to be operated.

At time t4, the read command RD and address 04 are input. The column select lines CSL4, CSL5, CSL6, and CSL7 are sequentially activated in accordance with the column address to read the data held in the sense amplifier. By the above operation, data Q0 to Q7 are output to the outside as an output signal.

Subsequently, at time t5, an active command ACT and an address 20 are input to execute the write operation. Since the memory block 1 is in an inactive state, the word line corresponding to the row address is activated. Namely, the word line WL20 is selected to be activated from the L level to the H level. At the same time as the word line is activated, the sense amplifier is equalized into a pulse shape by the signal SAEQ0, and the sense operation is performed after the separation gate is opened in accordance with the signal BLTG1.

However, since the burst write is executed even after the sense operation is completed, the word line WL20 activated at the H level is kept in the activated state.

At time t6, the write command WRT and address 00 are input. Then, the recording data D0 to D3 are sequentially applied from the outside. Therefore, data is sequentially written to the memory cells designated by the word line WL20 and the column select lines CSL0, CSL1, CSL2, and CSL3.

At time t7, the active command ACT and address 20 are input from the outside.

However, the memory block BLOCK1 cannot activate other word lines because word line WL20 is in an active state and is in the middle of executing a write operation. Thus, the row address comparison section 8A outputs IntBUSY to the control circuit 2A. In addition, since the current is in burst operation, the precharge operation cannot be performed. Therefore, even if the active command ACT is applied from the outside, NOP (No Operation) becomes an internal operation. In this case, the external memory control device 9 is notified by the signal BUSY.

At time t8, the active command ACT and address 21 are input again from the outside. Since the word line WL20 is still active in the memory block BLOCK1, the row address comparison section 8A outputs the signal IntBUSY as in the case of time t7. However, since the burst operation is finished, the precharge operation is started inside the semiconductor memory device.

At time t9, the active command ACT and address 21 are input again. Since the memory block BLOCK1 is in an inactive state, the word line WL21 is activated.

At time t10, the write command WRT and address 00 are input. Then, data is sequentially written to the memory cells designated by the word line WL21 and the column select lines CSL0, CSL1, CSL2, and CSL3.

At time t11, the command SEN and address 00 are input. In this case, since the data has already been read in the sense amplifier, the row address comparison section 8A notifies the reception of the command by the signal Ready. The read command can be accepted immediately without the need to operate the row system.

At time t12, the read command RD and address 08 are input.

Therefore, the column select lines CSL8, CSL9, CSLA, and CSLB are sequentially activated to read data held in the sense amplifier.

As described above, the semiconductor memory device of the second embodiment includes a row address comparison section therein for managing row addresses. Therefore, it is not necessary to manage the row address on the side of the memory control device such as the chipset. Therefore, the ability to manage the row address on the chipset side makes it possible to achieve the maximum performance as a semiconductor memory device without deactivating the sense amplifier holding valid data.

In the case where these row address information is managed inside the memory device, when the activation of the word line is actually required and unnecessary, the time required for reading or writing is different. The function of notifying this to outside is required separately. When there is an access request from the CPU, the chipset determines whether or not the word line of the corresponding address is activated based on the signal from the memory rather than the register of the chipset itself. This eliminates the need for the chipset side to perform control management of activation / deactivation of word lines in the memory, so that proper word line control can be executed on the memory side.

In addition, in the semiconductor memory device of the second embodiment, the number of word lines is activated and the charge and discharge of the bit line pairs are reduced, so that power consumption can be reduced.

(Example 3)

In a semiconductor memory device, a balance between simplicity of control and high speed operation is important. In order to simplify the control, there may be a case where the conventional SDRAM control method is obeyed that the row system operation for the same bank cannot be performed while the word line for writing is being activated. Even in this case, it is possible to speed up the activation of the read word line.

Fig. 13 is a diagram showing the arrangement of memory cell arrays of the semiconductor memory device of the third embodiment.

Referring to Fig. 13, BLOCK0 and BLOCK1 are typically represented as memory blocks, and a switch array SW for connecting corresponding bit lines in accordance with the signal ARTG01 is disposed between the memory block BLOCK0 and the memory block BLOCK1.

Since the configuration of other parts is the same as the arrangement described in Fig. 2, the description is not repeated.

14 is a circuit diagram showing a detailed configuration of a memory cell array.

Referring to FIG. 14, the memory block BLOCK0 is disposed between the memory cell arrays MA # 00 and MA # 01 and the memory cell arrays MA # 00 and the memory cell arrays MA # 01 and are shared with the memory cell arrays. Contains SAB # 0. The memory block BLOCK1 includes memory cell arrays MA # 10 and MA # 11, and a sense amplifier band SAB # 1 disposed between the memory cell arrays MA # 10 and MA # 11 and shared among the memory cell arrays. Since the sense amplifier stage SAB # 0 has the same configuration as that described in FIG. 3, the description is not repeated. Since the configuration of the sense amplifier stage SAB # 1 is also the same as that of the sense amplifier stage SAB # 0, the description is not repeated.

The sense amplifier band SAB # 1 differs in that the control signal corresponding to the block BLOCK1 is applied instead of the control signal corresponding to the block BLOCK0.

The switch array SW is disposed between the memory cell array MA # 01 and the memory cell array MA # 10.

The switch array SW includes a connection circuit 450 for connecting the bit line pairs BL10 and / BL10 and bit line pairs BL20 and / BL20, and a connection circuit 451 for connecting the bit line pairs BL11, / BL11 and bit line pairs BL21 and / BL21. do.

The connection circuit 450 includes an N channel MOS transistor 460 connected between the bit line BL10 and the bit line BL20, and an N channel MOS transistor 461 connected between the bit line / BL10 and the bit line / BL20. The connection circuit 451 includes an N-channel MOS transistor 462 connected between the bit line BL11 and the bit line BL21, and an N-channel MOS transistor 463 connected between the bit line / BL11 and the bit line / BL21. N-channel MOS transistors 460 to 463 all receive signal ARTG01 as a gate.

Fig. 15 is a block diagram showing the configuration of the sense amplifier control circuit 5B used in the third embodiment.

Referring to Fig. 15, the sense amplifier control circuit 5B outputs a signal RAE for enabling row addressing and a signal BLEQ for instructing equalization of bit lines in accordance with signals ACT0, SEN0, PRE0, and PALL. And a reference timing generator 502 for outputting the reference timing signals ACTD1 to ACD3, SEND1 to SEND7, ACTSEN, ACTSEND1 to ACTSEND3, PRED1, PALLD1, PALLD2, and PCD1.

The sense amplifier control circuit 5B includes a sense amplifier controller 504 that outputs signals S0, / S0, SAEQ0, S1, / S1, SAEQ1, a row address signal / RA4 and a clock selection signal B0SEL, B1SEL, and a reference timing generator. Separation gate control unit 506 for outputting signals ARTG01 and BLTG0 to BLTG3 for executing control of the separation gate provided on the bit line in accordance with the output, and signals CAE, IOSW0, IOSW1, B0SEL, and B1SEL in accordance with signals RD0, WRT0, and IADDRESS. It further includes an IOSW control unit 508 for outputting.

FIG. 16 is a circuit diagram showing the configuration of the reference timing generator 502 in FIG.

Referring to FIG. 16, the reference timing generator 502 includes a delay circuit 510 for delaying the signal ACT0 and outputting the signal ACTD1, a delay circuit 512 for delaying the signal ACTD1 and outputting the signal ACTD2, and a signal ACTD2. Delay circuit 514 for delaying the signal ACTD3 and delay circuit 516 for delaying the signal ACTD3.

The reference timing generator 502 delays the signal SEN0 to output the signal SEND1, delay circuit 522 to delay the signal SEND1 to output the signal SEND2, and delays the signal SEND2 to delay the signal SEND3. A delay circuit 524 for outputting and a delay circuit 526 for delaying the signal SEND3 are further included.

The reference timing generator 502 includes an OR circuit 530 that receives the signal ACT0 and the signal SEN0 and outputs the signal ACTSEN, an OR circuit 532 that receives the signal ACTD1 and the signal SEND1 and outputs the signal ACTSEND1, and a signal ACTD2 and the signal. OR circuit 534 that receives SEND2 and outputs signal ACTSEND2, OR circuit 536 that receives signals ACTD3 and signal SEND3 and outputs signal ACTSEND3, and outputs signal SEND4 by receiving the outputs of delay circuits 516 and 526 It further includes an OR circuit 538.

The reference timing generator 502 delays the signal SEND4 to output the signal SEND5, delays the signal SEND5 to delay the signal SEND6, and delays the signal SEND6 to delay the signal SEND7. A delay circuit 544 is further included.

The reference timing generator 502 includes a delay circuit 546 for delaying the signal PRE0 to output the signal PRED1, a delay circuit 552 for delaying the signal PALL and outputting the signal PALLD1, and delaying the signal PALLD1 to provide the signal PALLD2. A delay circuit 554 for outputting, an OR circuit 548 for receiving the signal PRE0 and the signal PALL and outputting the signal PC, and a delay circuit 550 for receiving and delaying the signal PC and outputting the signal PCD1.

The reference timing generator 502 includes an OR circuit 556 that receives a signal PALL and a signal PRE0, an SR flip-flop circuit 558 that is set in accordance with the signal ACTD1 and reset in accordance with the output of the OR circuit 556, and the signal SEND1. SR flip-flop circuit 560 is set according to the reset and reset according to the signal SEND7, and OR circuit 562 for receiving the output of the SR flip-flop circuits (558, 560) and outputs the signal RAE.

The reference timing generator 502 includes an OR circuit 564 that receives signals SEND7 and a signal PCD1, and an SR flip-flop circuit 566 that is set according to the output of the OR circuit 564 and reset according to the signal ACTSEN to output the signal BLEQ. More).

The main signal RAE generated in the circuit of FIG. 16 will be described.

The signal RAE is activated by the signal ACTD1 output in accordance with the active command and deactivated when the precharge command is input. On the other hand, when the command SEN is input, the signal RAE is activated according to the activation of the signal SEND1 after a predetermined delay time elapses. When the predetermined time elapses, the signal RAE is reset because the flip-flop circuit 560 is reset according to the signal SEND7. The activation timing of the word line is defined by the activation period of this signal RAE.

In this way, the reference timing generator 502 generates the operation reference timing of the row system by a combination of outputs of a plurality of delay circuits for delaying the signals ACT0, SEN0, PRE0, and PALL.

FIG. 17 is a circuit diagram showing the configuration of the sense amplifier control unit 504 in FIG. 15.

Referring to FIG. 17, the sense amplifier control unit 504 includes a sense amplifier control signal generation circuit 570 for outputting signals S0, / S0, and SAEQ0 in order to control the sense amplifier band SAB # 0 in FIG. A sense amplifier control signal generation circuit 571 that outputs signals S1, / S1, and SAEQ1 for executing control of the amplifier to SAB # 1 is included.

The sense amplifier control signal generation circuit 570 is set in accordance with the NAND circuit 574 for receiving the signals B1SEL and SEND6, the inverter 576 for inverting the output of the NAND circuit 574, and the signal SEND4, and in accordance with the signal SEND5. An SR flip-flop circuit 572 to be reset, a NAND circuit 578 receiving the outputs of the signals B1SEL and an SR flip-flop circuit 572, an inverter 580 that receives the output of the NAND circuit 578, and inverts the signal; SR flip-flop circuit 582 set according to PALLD1 and reset according to signal PALLD2, OR circuit 584 receiving the output of inverter 580 and the output of SR flip-flop circuit 582, and of inverter 576. An SR flip-flop circuit 586 is set according to the output and reset according to the output of the OR circuit 584.

The sense amplifier control signal generation circuit 570 is set in accordance with the signal ACTSEND2, the NAND circuit 588 receiving the signals ACTSEND3, B0SEL, the inverter 590 which receives and inverts the output of the NAND circuit 588, and the signal ACTSEND2. The SR flip-flop circuit 592 to be reset, the NAND circuit 594 receiving the outputs of the signals B0SEL and the SR flip-flop circuit 592, the inverter 596 for inverting the output of the NAND circuit 594, and the SR. OR circuit 598 that receives the output of flip-flop circuit 582 and the output of inverter 596, and an SR flip-flop circuit that is set according to the output of inverter 590 and reset according to the output of OR circuit 598 ( 600).

The sense amplifier control signal generation circuit 570 includes an OR circuit 602 that receives the outputs of the SR flip-flop circuits 586 and 600, and a driving circuit that drives signals S0 and / S0 in accordance with the output of the OR circuit 602 ( 604 and an OR circuit 606 for receiving the outputs of the OR circuits 584 and 598 and outputting the signal SAEQ0.

In the configuration of the sense amplifier control signal generation circuit 570, the sense amplifier control signal generation circuit 571 receives the signal B0SEL instead of the signal B1SEL, receives the signal B1SEL instead of the signal B0SEL, and replaces the signals S0, / S0, and SAEQ0. Although the points of outputting S1, / S1, and SAEQ1 differ, the internal structure is the same as that of the sense amplifier control signal generation circuit 570, and thus the description is not repeated.

In this way, the sense amplifier control unit 504 controls equalization, activation, and deactivation of the sense amplifier based on the operation reference timing applied from the reference timing generation unit 502 to the memory block designated by the block selection signal. .

FIG. 18 is a circuit diagram showing the configuration of the separation gate control unit 506 in FIG. 15.

Referring to FIG. 18, the separation gate control unit 506 executes control of the signal generation circuit 610 that outputs signals BLTG0 and BLTG1 and control of the separation gate of the memory block BLOCK1 in order to perform control of the separation gate of the memory block BLOCK0. To this end, a signal generating circuit 612 for outputting signals BLTG2 and BLTG3 and a signal generating circuit 614 for outputting signal ARTG01 for executing control of a switch array disposed between memory blocks BLOCK0 and BLOCK1 are included.

The signal generation circuit 610 is a three-input NAND circuit 620 that receives signals ACTD2, B0SEL, and RA4, an inverter 622 that receives and inverts the output of the NAND circuit 620, and an output of the inverter 622. And an SR flip-flop circuit 624 that is set and reset in accordance with the signal PCD1.

The signal generating circuit 610 is a three-input NAND circuit 626 that receives signals SEND2, B0SEL, and RA4, an inverter 628 that receives and inverts the output of the NAND circuit 626, and an output of the inverter 628. It further includes an SR flip-flop circuit 630 that is set and reset in accordance with the signal SEND7.

The signal generation circuit 610 has a gate circuit 632 for activating the output to the L level when the signals SEND4 and B0SEL are both at the H level and the signal RA4 is at the L level, and an inverter that receives the output of the gate circuit 632 and inverts it. 634 and an SR flip-flop circuit 636 which is set in accordance with the output of the inverter 634 and reset in accordance with the signal SEND7. The signal generating circuit 610 is set according to the output of the NAND circuit 638 receiving the signals SEND5 and B1SEL, the inverter 640 which receives the output of the NAND circuit 638, and the output of the inverter 640, and is connected to the signal SEND7. And a four-input OR circuit 643 which receives the output of the SR flip-flop circuits 624, 630, 636, and 642, and outputs the signal BLTG1.

The signal generating circuit 610 receives the output of the gate circuit 644 and the gate circuit 644 for detecting that the signals ACTD2 and B0SEL are at the H level, and the signal RA4 is at the L level, and activating the output to the L level. And an SR flip-flop circuit 648 which is set according to the output of the inverter 646 and reset in accordance with the signal PCD1.

The signal generating circuit 610 detects that the signals SEND2 and B0SEL are at the H level and the signal RA4 is at the L level, and receives the output of the gate circuit 650 and the gate circuit 650 for activating the output to the L level and inverts the output. The inverter 652, the SR flip-flop circuit 654 set according to the output of the inverter 652, and reset according to the signal SEND7, and the SR flip-flop circuits 648 and 654 are outputted to output the signal BLTG0. It further includes an OR circuit 656.

The signal generating circuit 612 receives the output of the gate circuit 660 and the gate circuit 660 that detects that the signals ACTD2 and B1SEL are at the H level and the signal RA4 is at the L level, and activates the output to the L level. And an SR flip-flop circuit 664 set according to the output of the inverter 662 and reset according to the signal PCD1.

The signal generating circuit 612 detects that the signals SEND2 and B1SEL are at the H level and the signal RA4 is at the L level, and receives the output of the gate circuit 666 and the gate circuit 666 for activating the output to the L level. And an SR flip-flop circuit 670 which is set according to the output of the inverter 668 and reset in accordance with the signal SEND7.

The signal generating circuit 612 is set in accordance with the output of the NAND circuit 672 receiving the signals SEND4, B1SEL, and RA4, the inverter 674 for receiving and inverting the output of the NAND circuit 672, and the output of the inverter 674. It further includes an SR flip-flop circuit 676 that is reset in accordance with SEND7.

The signal generating circuit 612 is set in accordance with the NAND circuit 678 for receiving the signals SEND5 and B0SEL, the inverter 680 for inverting the output of the NAND circuit 678, and the output of the inverter 680, and in response to the signal SEND7. The circuit further includes an SR flip-flop circuit 682 which is reset accordingly and a four-input OR circuit 684 that receives the output of the SR flip-flop circuits 664, 670, 676, and 682 and outputs a signal BLTG2.

The signal generation circuit 612 is a three-input NAND circuit 686 that receives signals ACTD2, B1SEL, and RA4, an inverter 688 that receives and inverts the output of the NAND circuit 686, and an output of the inverter 688. SR flip-flop circuit 690 that is set and reset in accordance with signal PCD1, a three-input NAND circuit 692 that receives signals SEND2, B1SEL, and RA4, and an inverter 694 that receives and inverts the output of NAND circuit 692. And an SR flip-flop circuit 696 set according to the output of the inverter 694 and reset according to the signal SEND7, and an OR circuit 698 that receives the output of the SR flip-flop circuits 690 and 696 and outputs the signal BLTG3. Includes more.

The signal generating circuit 614 is set in accordance with the NAND circuit 700 receiving the signals SEND4 and B0SEL, the inverter 702 which receives and inverts the output of the NAND circuit 700, and the output of the inverter 702 and is connected to the signal SEND7. According to the SR flip-flop circuit 704, the NAND circuit 706 that receives signals SEND4 and B1SEL, the inverter 708 that receives and inverts the output of the NAND circuit 706, and the output of the inverter 708. An SR flip-flop circuit 707 that is set and reset in accordance with the signal SEND7, and an OR circuit 709 that receives the output of the SR flip-flop circuits 707 and 704 and outputs the signal ARTG01.

The signals BLTG0 and BLTG3 are not related to the control when transferring data held in the sense amplifier to adjacent memory blocks.

On the other hand, the signal BLTG1 is related to the control for transmitting the maintenance data of the sense amplifier to the adjacent block. Therefore, in order to generate the signal BLTG1 in addition to the circuit corresponding to the circuit configuration in which the signal BLTG0 is generated, the gate circuit 632, the inverter 634, the SR flip-flop circuit 636, the NAND circuit 638, and the inverter 640 and an SR flip-flop circuit 642 are provided.

The signal BLTG2 is similarly related to the control for transmitting the data held in the sense amplifier to the adjacent memory block. Therefore, in addition to the circuit corresponding to the circuit configuration for generating the signal BLTG3, NAND circuits 672 and 678, inverters 674 and 680 and SR flip-flop circuits 676 and 682 are added to generate the signal BLTG2. .

FIG. 19 is a circuit diagram showing the configuration of the IOSW control unit 508 in FIG. 15.

Referring to FIG. 19, the IOSW control unit 508 activates a signal generator circuit 710 for outputting signals B0SEL and B1SEL for selecting a block according to the row address signals RA5 and RA6, and activates the column decoder according to the signals WRT0 and RD0. And a signal generator circuit 712 for outputting signals WIOSW and RIOSW that are activated in a pulse shape corresponding to the signal CAE and the burst operation to be made, and a signal generator circuit 714 for outputting signals IOSW0 and IOSW1.

The signal generation circuit 710 includes an OR circuit 720 that receives signals RA5 and RA6, an inverter 722 that receives and inverts the output of the OR circuit 720, and a NAND circuit that receives the output of the inverter 722 and the signal ACTSEN. 724, an inverter 726 for receiving and inverting the output of the NAND circuit 724, and an SR flip-flop circuit 728 set according to the output of the inverter 726 and reset in accordance with the clock signal CLK.

The signal generation circuit 710 receives the outputs of the clock inverter 736 and the clock inverters 730 to 736 connected in series connected to the output of the SR flip-flop circuit 728 and the SR flip-flop circuit 728. An OR circuit 738 for outputting the signal B0SEL is further included.

The clock inverters 730 and 734 perform an inversion operation according to the activation of the clock signal / CLK. In addition, the clock inverters 732 and 736 perform the inversion operation in response to the activation of the clock signal CLK.

The signal generating circuit 710 detects that the signal RA5 is at the H level and the signal RA6 is at the L level, and receives and inverts the gate circuit 740 for activating the output to the L level and the output of the gate circuit 740. Set according to the output of the inverter 742, the NAND circuit 744 that receives the output of the inverter 742 and the signal ACTSEN, the inverter 746 that receives the inverted output of the NAND circuit 744, and the output of the inverter 746. And an SR flip-flop circuit 748 that is reset in accordance with the clock signal CLK.

The signal generation circuit 710 receives the output of the SR flip-flop circuit 748 and the serially connected clock inverters 750 to 756, the output of the SR flip-flop circuit 748, and the output of the clock inverter 756. An OR circuit 758 for outputting the signal B1SEL is further included.

The clock inverters 750 and 754 perform an inversion operation according to the activation of the clock signal / CLK. In addition, the clock inverters 752 and 756 perform the inversion operation in accordance with the activation of the clock signal CLK.

The signal generation circuit 712 includes a pulse generation circuit 760 for generating a pulse signal corresponding to the burst operation in accordance with the signal WRT0, and a pulse generation circuit 762 for generating a pulse signal corresponding to the burst operation in accordance with the signal RD0; An OR circuit 764 which receives the signal WCSL from the pulse generating circuit 760 and receives the signal RCSL from the pulse generating circuit 762 and outputs the signal CAE to the column decoder 4, and the pulse generating circuits 760 and 762. OR circuit 766 receiving signals INBURSTW and INBURSTR from the NAND circuit, NAND circuit 768 receiving the output of OR circuit 766 and signal B0SEL, and NAND circuit 768 receiving the inverted signal, and outputting signal INBURST0. An inverter 770, an NAND circuit 772 that receives the output of the OR circuit 766 and the signal B1SEL, and an inverter 774 that receives the output of the NAND circuit 772 and inverts it to output the signal INBURST1.

The pulse generating circuit 762 includes six clock inverters 780 to 790 connected in series receiving the signal RD0, and an SR flip set according to the signal RD0 and reset according to the output of the clock inverter 790 to output the signal INBURSTR. A flop circuit 794. The clock inverters 780, 784, and 788 are activated according to the clock signal CLK to perform the inversion operation. Clock inverters 782, 786, and 790 are activated according to the clock signal / CLK to perform an inversion operation.

The pulse generating circuit 762 is a four-input OR circuit 792 that receives the output of the clock inverters 780, 784, 788 and the signal RD0, and a delay circuit 796 connected in series that receives the output of the OR circuit 792. 798, 800, 804, SR flip-flop circuit 802 that is set in accordance with the output of the delay circuit 796 and reset in accordance with the output of the delay circuit 800 to output the signal RCSL, and the delay circuit 798 And an SR flip-flop circuit 806 that is set according to the output of and resets according to the output of the delay circuit 804 to output the signal RIOSW.

The pulse generating circuit 760 receives the signal WRT0 instead of the signal RD0 and outputs the signals INBURSTW, WIOSW, and WCSL instead of the signals INBURSTR, RCSL, and RIOSW, respectively, but the internal configuration is the pulse generating circuit 762. ), So the description is not repeated.

The signal generation circuit 714 includes a NAND circuit 810 that receives signals ACTSEN and B0SEL, an inverter 812 that receives and inverts the output of the NAND circuit 810, and signals INBURST0 and RIOSW are H level, and an inverter 812. The gate circuit 814 detects that the output of the L) is at the L level and activates the output at the L level, and an inverter 816 that receives the output of the gate circuit 814 and inverts the output.

The signal generation circuit 714 receives a NAND circuit 818 that receives signals ACTSEN and B1SEL, an inverter 820 that receives and inverts the output of the NAND circuit 818, and receives an output of the signals INBURST1, RIOSW and the inverter 820. It further includes a three-input NAND circuit 822 and an inverter 824 that receives and inverts the output of the NAND circuit 822.

The signal generating circuit 714 receives a signal of the NAND circuit 826 that receives the signals INBURST0 and WIOSW, an inverter 828 that receives and inverts the output of the NAND circuit 826, and receives an output of the inverters 816, 824, and 828. It further includes an OR circuit 830 of three inputs for outputting IOSW0.

The signal generating circuit 714 includes a NAND circuit 832 that receives signals ACTSEN and B1SEL, an inverter 834 that receives and inverts the output of the NAND circuit 832, and the signals INBURST1 and RIOSW are all at the H level, and the inverter ( It further includes a gate circuit 836 for detecting that the output of 834 is at the L level and activating the output to the L level, and an inverter 838 for receiving and inverting the output of the gate circuit 836.

The signal generation circuit 714 receives a NAND circuit 840 that receives signals ACTSEN and B0SEL, an inverter 842 that receives and inverts the output of the NAND circuit 840, and receives an output of the signals INBURST0, RIOSW, and the inverter 842. It further includes a three-input NAND circuit 844 and an inverter 846 that receives and inverts the output of the NAND circuit 844.

The signal generating circuit 714 receives a signal of the NAND circuit 848 that receives the signals INBURST1 and WIOSW, an inverter 850 that receives and inverts the output of the NAND circuit 848, and receives an output of the inverters 838, 846, 850. It further includes an OR circuit 852 of three inputs for outputting IOSW1.

The main signals generated in the circuit of FIG. 19 will be described.

The signal INBURSTR is generated in accordance with the signal RD0, and is a signal which becomes the period H level of the burst length. The signals RCSL and RIOSW are signals that are activated in the shape of pulses according to the signal RD0 by the number of data output in the burst period.

Similarly, the signal INBURSTW is a signal that becomes H level during the burst length period in accordance with the signal WRT0. The signals WCSL and WIOSW are signals generated according to the signal WRT0 and activated in the shape of pulses by the number of data of the burst operation.

The signal IOSW0 is output in the following three cases.

The first case is the case where the signal INBURST0 = H, the signal RIOSW = H, and the memory block BLOCK0 do not accept the command ACT or the command SEN.

The second case is the case where the signal INBURST1 = H, the signal RIOSW = H, and the memory block BLOCK1 accept the command ACT or the command SEN.

The third case is the case where the signal INBURST0 = H and the signal WIOSW = H.

Similarly, the signal IOSW1 is output in the following three cases.

The first case is a case where the signal INBURST1 = H, the signal RIOSW = H, and the memory block BLOCK1 do not accept the command ACT or the command SEN.

The second case is a case where the signal INBURST0 = H, the signal RIOSW = H, and the memory block BLOCK0 receive the command ACT or the command SEN.

The third case is the case where the signal INBURST1 = H and the signal WIOSW = H.

In this way, by controlling the signals IOSW0 and IOSW1, normally, either one of IOSW0 and IOSW1 on the selected memory block side is activated and outputted. However, when a command ACT or a command SEN is input to the selected memory block during a burst operation. The gate circuit on the side of the adjacent memory block is opened to continue data output.

20 is an operational waveform diagram for describing the operation of the semiconductor memory device of the third embodiment.

14 and 20, an example in which a read operation is performed from a plurality of word lines belonging to the same memory block will be described. The burst length is 4 clocks.

First, in the initial state of time t0, the signal BLEQ is at the H level. In addition, the signals SAEQ0 and SAEQ1 are both at L level. The signals BLTG0, BLTG1, and BLTG2 are all at L level. The signals S0, S1, / S0, and / S1 are all potentials VBL (1/2 of the power source potential VDD).

At time t1, the command SEN and address 00 are input. Therefore, the signal BLEQ is changed from the H level to the L level. In addition, the signal SAEQ0 is activated in the pulse shape at the H level. Therefore, the bit lines BL00, / BL00, BL01, / BL01 in Fig. 14 are in a high impedance state. The sense amplifiers 62 and 63 are initialized.

The word line WL00 corresponding to the address 00 is activated at the H level, and the data of the memory cell is read out to the bit line BL00. Thereafter, the signal BLTG0 is activated from the L level to the H level, thereby transferring the potential of the bit line pair to the sense amplifiers 62 and 63.

Then, the signals S0 and / S0 are activated at the H level and the L level, respectively, so that the potential difference between the bit line pairs is amplified in the sense amplifiers 62 and 63.

Since no valid data is stored in the sense amplifiers 62 and 63 included in the memory block BLOCK1, the sense amplifiers in which the data amplified by the sense amplifiers 62 and 63 included in the memory block BLOCK0 are included in the memory block BLOCK1. The operation transmitted to 62, 63 is started.

The signals BLTG1 and ARTG01 are activated from the L level to the H level, so that the potential of the bit line pair amplified by the sense amplifier is transferred to the memory block BLOCK1 side. That is, the potential of the bit line BL00 is transferred to the bit line BL10 and further to the bit line BL20. Similarly, the potential of the bit line / BL00 is first transferred to the bit line / BLl0 and subsequently to the bit line / BL20.

Thereafter, the signal SAEQ1 is activated in a pulse shape at the H level, and the sense amplifiers 62 and 63 included in the sense amplifier stage SAB # 1 are initialized. Thereafter, the signal BLTG2 is activated from the L level to the H level, the signals S1 and / S1 are activated at the H level and the L level, respectively, and the potential difference between the bit lines BL20 and / BL20 is amplified. Since this potential is originally a potential difference between the bit lines BL00 and / BL00, the sense amplifier 62 of the sense amplifier unit SAB # 0 and the sense amplifier 62 of the sense amplifier unit SAB # 1 maintain the same value.

Since the word line WL00 is activated according to the command SEN, the data is automatically deactivated to the L level when data is read by the sense amplifier after a predetermined time has elapsed.

When data transfer is completed, the signals BLTG0, ARTG01, BLTG1, BLTG2 are set to L level, and the signal BLEQ is set to H level.

The above operation is executed in response to the input of the command SEN at time t1.

In parallel with these operations, at time t2, the command RD and address 00 are input from the outside. Since the burst length is 4, data corresponding to column addresses 00 to 03 is read.

In response to the input of the command RD, the column select line CSL0 is activated to the H level so that the sense amplifiers 62 of the sense amplifier band SAB # 0 and SAB # 1 are connected to the local IO lines LIO0 and LIO1, respectively.

The signal IOSW0 is set to the H level, and the local IO line LIO0 is connected to the global IO line GIO, and the data of the sense amplifier 62 of the sense amplifier stage SAB # 0 passes through the local IO line LIO0 and the global IO line GIO. 14).

Subsequently, in accordance with the burst operation, the column select line CSL1 is activated at the H level, and the sense amplifiers 63 of the sense amplifier band SAB # 0 and SAB # 1 are connected to the local IO lines LIO0 and LIO1, respectively.

The signal IOSW0 is activated at the H level, the local IO line LIO0 is connected to the global IO line GIO, and the data of the sense amplifier 63 of the sense amplifier band SAB # 0 passes through the local IO line LIO0 and the global IO line GIO. 14 is passed.

At time t3, the command SEN and address 01 are input. Therefore, the signal BLEQ is set at the L level, and the signal SAEQ0 is activated at the H level in a pulse shape. Equalization of the bit line pair is stopped, and the sense amplifier is initialized.

At this time, since the read operation is in progress, the sense amplifiers 62 and 63 of the memory block BLOCK0 holding the data have been initialized regardless of whether the data needs to be continuously read. However, since the data of the sense amplifiers 62, 63 on the memory block BLOCK0 side are all transmitted to the block BLOCK1 side by activating the signal ARTG01 at time t2, from the sense amplifiers 62, 63 on the memory block BLOCK1 side. The read operation can continue.

In accordance with the burst operation, the column select line CSL2 is activated at the H level, and a sense amplifier (not shown) is connected to the local IO line pair.

Instead of signal IOSW0, signal IOSW1 is activated at H level so that local IO line LIO1 is connected to global IO line GIO. The data of the sense amplifier on the memory block BLOCK1 side is transmitted to the input / output circuit 14 via the local IO line LIO1 and the global IO line GIO. The first two pulses of the signal IOSW0 are output from the OR circuit 830 via the gate circuit 814 and the inverter 816, and the subsequent two pulses of the IOSW1 are in the midst of an active command being input to the memory block BLOCK0. It is output from the OR circuit 852 via the NAND circuit 844 and the inverter 846.

Further, the column select line CSL3 and the signal IOSW1 are subsequently activated at the H level, and the data of the corresponding sense amplifier (not shown) is transmitted to the input / output circuit 14 via the local IO line LIO1 and the global IO line GIO.

Operation related to word lines is also carried out as in the case of time t1. First, the word line WL01 goes to the H level, and the data of the memory cell is read. In order to transfer the read data to the sense amplifier, the signal BLTG0 goes to H level. The signals S0 and / S0 are set to H level and L level, respectively, so that the sense amplifier amplifies the potential difference between the bit line pairs.

The data transfer from the sense amplifier on the memory block BLOCK0 side to the sense amplifier on the memory block BLOCK1 side is executed in the same manner as when the command SEN is input at time t1. First, signals ARTG01 and BLTG1 are set to H level, and signals S1 and / S1 are both set to potential VBL. Then, the signal SAEQ1 is activated in the pulse shape at the H level. Thereafter, the signal BLTG2 is set to the H level, the signals S1 and / S1 are set to the H level and the L level, respectively, and the sense amplifiers 62 and 63 of the sense amplifier to SAB # 1 amplify the data transmitted from the memory block BLOCK0. After completion of data transfer, the signals BLTG0, ARTG01, BLTG1, BLTG2, and word line W01 are set to L level, and signal BLEQ is set to H level.

Then, at time t4, the read command RD and address 00 are input.

Unlike the last time, since no command SEN is input at the end of the read operation, a burst read operation similar to that of a normal SDRAM occurs. That is, the column select lines CSL0, CSL1, CSL2, and CSL3 are activated in the pulse shape of H level in order. In response to the activation of each column select line, the signal IOSW0 is activated in four pulse shapes. The local IO line LIO0 is connected to the global IO line GIO, and the data of the sense amplifiers 62 and 63 inside the sense amplifier stage SAB # 0 and the sense amplifiers corresponding to the column selection lines CSL2 and CSL3 (not shown) are stored in the local IO line LIO0. The data is transmitted to the input / output circuit 14 via the global IO line GIO.

After time t5, the recording operation will be described. First, the command ACT and address 01 are input.

The same operation as the word line activation according to the command SEN at time t1 is performed. First, the word line WL01 is activated at the H level to read data of the memory cell. Then, the signal BLTG0 is set at the H level, and the signals S0 and / S0 are activated at the H level and the L level, respectively, so that the sense amplifier amplifies the potential difference between the bit line pairs.

The data transfer from the sense amplifier on the memory block BLOCK0 side to the sense amplifier on the memory block BLOCK1 side is performed in the same manner as in the case of time t1. The signals ARTG01 and BLTG1 are set to the H level, the signals S1 and / S1 are both set to the potential VBL, and the signal SAEQ1 is activated in the pulse shape and at the H level.

Thereafter, the signal BLTG2 is activated at the H level, the signals S1 and / S1 are at the H level and the L level, respectively, so that the sense amplifiers 62, 63, ... in the sense amplifier stage SAB # 1 are used to transfer data transmitted from the memory block BLOCK0. After amplification and completion of data transmission, the signals ARTG01, BLTG1, BLTG2 are set to L level.

At time t6, the write command WRT and address 04 are input.

The signal IOSW0 is set at the H level, the column select line CSL4 is activated at the H level, and an unillustrated sense amplifier corresponding to the column select line CSL4 receives data via the global IO line GIO and the local IO line LIO0, Data is also written to the memory cell.

Thereafter, the column select lines CSL5, CSL6, and CSL7 are activated to the H level in order by the burst operation, and data is written to the memory cells of the corresponding column addresses, respectively.

As described above, when the semiconductor memory device according to the third embodiment is used, since the row address can be input even during the read operation, the effective transfer rate of the data can be kept very high.

The semiconductor memory device according to the present invention has a great advantage over the prior art which does not exert the maximum effect because the burden on the controlling side is large despite the theoretically providing method of increasing the effective transfer rate. .

In addition, in the third embodiment, since a normal sense amplifier is used as a storage location for evacuation data, there is also an effect that the disadvantage in terms of manufacturing cost is reduced because the increase in layout area is small.

Since the semiconductor memory device of the third embodiment has almost no increase in chip area due to the addition of a circuit, even if used as a standard SDRAM, it is not disadvantageous in terms of cost. If it is provided with means for determining a specific command for which the function described in the third embodiment becomes valid, it is possible to operate as a normal SDRAM compatible product in a general system.

It is also possible to manufacture and divide together with the standard memory. As a production division method, operation switching using the option of the metal wiring in a wafer process, the programming by a laser trimmer, etc., the potential fixing of the internal pad in the assembly process, the potential fixing of the specific terminal of an apparatus, etc. are considered.

Since the semiconductor memory device according to one aspect of the present invention holds the data read by the sense amplifier until the word line activation instruction is given, the held data can be read at high speed without waiting for the activation of the word line. Become.

Since the semiconductor memory device according to another aspect of the present invention holds the data read to the sense amplifier until the word line activation instruction is made, the held data can be read at high speed without waiting for the activation of the word line. In addition, data reading can be performed from either of the two sense amplifiers.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.

Claims (3)

In a semiconductor memory device, A first memory cell array including a plurality of first memory cell groups arranged in a matrix shape, a first bit line pair, and a first word line group provided to intersect the first bit line pair; A second memory cell array including a plurality of second memory cell groups arranged in a matrix shape, a second bit line pair, and a second word line group provided to intersect the second bit line pair; A sense amplifier stage including a sense amplifier shared by the first and second bit line pairs; A control circuit for controlling initialization of the sense amplifier, initialization of the first and second bit line pairs, and activation of the first and second word line groups, The control circuit outputs a timing signal for transitioning any one of the first and second word line groups from an inactive state to an active state according to a first command, and simultaneously outputs the first and second bits. A semiconductor memory device for canceling line pair initialization and initializing the sense amplifier for a predetermined period. The method of claim 1, The control circuit, if any word line included in the first and second word line groups transitions from an inactive state to an active state and data from the first and second memory cell groups is read into the sense amplifier. Maintains the activated state of the sense amplifier until any one of the word lines included in the first and second word line groups is transitioned from an inactive state to an active state, And the sense amplifier holds the read data until any one of the word lines included in the first and second word line groups transitions from the non-selected state to the selected state. In a semiconductor memory device, A first memory block, The first memory block, A first memory cell array including a plurality of first memory cell groups arranged in a matrix shape, a first bit line pair, and a first word line group provided to intersect the first bit line pair; A second memory cell array including a plurality of second memory cell groups arranged in a matrix shape, a second bit line pair, and a second word line group provided to intersect the second bit line pair; A first sense amplifier stage including a first sense amplifier shared by the first and second bit line pairs, Further comprising a second memory block, The second memory block, A third memory cell array including a plurality of third memory cell groups arranged in a matrix shape, a third bit line pair, and a third word line group provided to intersect the third bit line pair; A fourth memory cell array including a plurality of fourth memory cell groups arranged in a matrix shape, a fourth bit line pair, and a fourth word line group provided to intersect the fourth bit line pair; A second sense amplifier stage including a second sense amplifier shared by the third and fourth bit line pairs, A switch circuit provided between the first and second memory blocks to connect the second bit line pair and the third bit line pair; And a control circuit for controlling the first and second sense amplifiers and the switch circuit to perform data transfer between the first and second sense amplifiers.