KR20030069636A - Method for demodulating wobble signal on optical disc - Google Patents

Abstract

PURPOSE: A method for demodulating a wobble signal of an optical disk is provided to detect an accurate wobble data bit clock and automatically correct an error of the detection. CONSTITUTION: A bit clock counts time intervals between edges of peak detecting signals or level-sliced pulse signals for calculating the accumulated mean value(S10). The bit clock counts a time interval between a first falling edge and a second falling edge of peak detecting signals or pulse signals for comparing the counted value with the accumulated mean value(S11). If the time count value is smaller than the accumulated mean value, the bit clock detects the next rising edge, and compares the counted value with the accumulated mean value to shift the level and initialize the time count value(S12). If the time count value is larger than the accumulated mean value, a level of a bit clock is shifted and the time count value is initialized(S13). The bit clock counts a time interval between the second rising edge and the next rising edge for comparing the time count value with the accumulated mean value(S14). If the time count value is smaller than the accumulated mean value, the bit clock detects the next falling edge, and compares the counted value with the accumulated mean value to shift the level and initialize the time count value(S15). If the time count value is larger than the accumulated mean value, the level of the bit clock is shifted and the time count value is initialized to count a time interval between the next rising edges(S16).

Description

Demodulation method of optical disc wobble signal {Method for demodulating wobble signal on optical disc}

The present invention relates to an optical disc wobble signal demodulating method for demodulating a wobble signal recorded as physical address information on an optical disc such as a recordable CD (CD) or a DVD (DVD).

In general, a recordable optical disc, for example, an optical disc such as a DVD-RAM or a DVD-RW (Re-Writable), has a recording surface of an optical disc for controlling a spindle servo operation or providing a clock for recording and reproducing data. Physical address information must be recorded in advance on the screen. A wobble addressing method for recording the physical address information as a wobble signal on an optical disc will now be described.

First, the wobble addressing method using the Complementary Allocated Pit Addressing (CAPA) method is used in the case of the DVD-RAM, and the wobble addressing method using the Land Pre-Pit Addressing method in the case of the DVD-RW. A method and the like have been used. In recent years, a wobble addressing method using a minimum shift keying (MSK) modulation method has been proposed.

On the other hand, in the MSK modulation scheme, a block diagram, the in-phase messages from a wobble data to be recorded as a physical address information on the optical disc, as shown in _{1 (m I: Inphase messageof wobble} data) and quadrature phase messages (m _Q: Quadrature message By the combination of the wobble data, two different frequencies (f ₁ , f ₂ ) and two phases (P ₁ , P ₂ ), respectively, are determined, and by the two different frequencies and two phases, 4 To generate wobble signals of two different waveforms, wherein the two different frequencies, for example, the first frequency f ₁ , have a frequency value higher than the center frequency fc and the second frequency f. ₂ ) has a frequency value lower than the center frequency f _c ,

The two different phases, for example, the first phase P ₁ have a zero phase, and the second phase P ₂ has a 180 degree phase π. As described above, four different waveforms generated according to the first and second frequencies and the first and second phases, that is, , , , And The MSK wobble signal having? Is expressed by the following equation.

-Formula (1)

Here, T _b represents the wobble data bit duration. For example, as shown in FIG. 2, when the wobble data to be recorded on the optical disc is bit string data of '11010000', the in-phase the combination of the message (m _I) and quadrature phase messages (m _Q) is always so should be (m _I, m _Q), (m _I, m _Q) of the first bit '1', the second bit ' Combination with 1 'results in (1,1), and ( m _I , m _Q ) for the second bit' 1 'becomes (0,1) in combination with the third bit' 0 '. .

Since ( m _I , m _Q ) for the third bit '0' becomes (1,0) by combination with the fourth bit '1', eventually ( m _I , m _Q ) becomes (1 , 1), (1,0), (0,1), (0,0), and the pulse signal corresponding thereto is different from two different frequencies as shown in FIG. You will have four different waveforms with two phases.

Therefore, the MSK wobble signal S _MSK (t) has a smoothly continuous pulse waveform by summing the pulse signals, so that the wobble signal can be recorded more accurately on the optical disc.

On the other hand, in the demodulation device for demodulating the MSK wobble signal read out from the optical disc, as shown in Fig. 3, the analog mixers 10 and 11, the interval integrators 12 and 13, the phase determiners 14 and 15, and logic are shown. A circuit 16 is included. In the analog mixers 10 and 11, the wobble signal read out from the optical disc includes the first and second encoding frequencies ( , ), The wobble signal of the corresponding frequency is extracted, and the interval integrators 12 and 13 integrate the extracted wobble signal of the corresponding frequency in a predetermined section, and in the phase determiner 14 and 15, The integral value is compared with a preset reference value (Threshold = 0) to determine a phase.

The logic circuit 16 interleaves the determined phases to restore and output binary sequence bit string data, that is, original wobble data. Therefore, the MSK wobble signal recorded in the pulse waveform which is naturally continuous by the MSK modulation method is demodulated and output as wobble data without high frequency noise by the demodulation device configured as described above.

However, when the rotational speed of the optical disk is changed by the spindle servo operation in the optical disk device, since the frequency of the wobble signal read out from the optical disk is variable, the first and second encodings applied to the analog mixer 20 respectively. Frequency must be varied, which requires a complex hardware configuration and demodulation algorithm.

Accordingly, the present invention has been made to solve the above problems, and when demodulating the MSK wobble signal, the level transition period of the level slice pulse signal after the integration of the wobble signal, or the level transition period of the peak detection signal of the wobble signal is determined. Monitors and detects a wobble data bit clock of a certain period, and at the falling edge of the bit clock of the wobble data, original wobble data is determined based on the level value of the level sliced pulse signal or the level value of the peak detection signal. It is an object of the present invention to provide a method of demodulating an optical disc wobble signal for detecting and outputting the wobble data bit clock more accurately.

1 is a table illustrating equations and conditions applied to a general MSK wobble signal modulation method.

2 is a waveform diagram of an MSK wobble signal modulated by a general MSK wobble signal modulation method.

3 illustrates a configuration of a demodulation device of a general MSK wobble signal.

4 illustrates a configuration of an apparatus for modulating an optical disc wobble signal according to the present invention.

5 is a waveform diagram of an MSK wobble signal modulated by the optical disc wobble signal modulation method according to the present invention.

6 shows a configuration of an apparatus for demodulating an optical disc wobble signal according to the present invention.

7 shows each signal and wobble data detected and demodulated by the optical disc wobble signal demodulation method according to the present invention;

8 is a table showing reference information applied to a method for demodulating an optical disc wobble signal according to the present invention;

FIG. 9 is a waveform diagram of an analog wobble signal with respect to a first frequency and a second frequency determined by an apparatus and method for modulating an optical disc wobble signal according to another embodiment of the present invention.

FIG. 10 shows a configuration of an apparatus for demodulating an optical disc wobble signal according to another embodiment of the present invention.

11 illustrates each signal and wobble data detected and demodulated by an optical disc wobble signal demodulation method according to another embodiment of the present invention;

12 illustrates a configuration of an apparatus for demodulating an optical disc wobble signal according to another embodiment of the present invention.

13 shows each signal and wobble data detected and demodulated by the optical disc wobble signal demodulation method according to another embodiment of the present invention;

14 is a flowchart illustrating a method for detecting a bit clock in a clock detector according to the present invention;

15 and 16 illustrate an embodiment of a bit clock detection process in a clock detector according to the present invention.

※ Explanation of code for main part of drawing

10,11: analog mixer 12,13: interval integrator

14,15: phase determination unit 16: logic circuit

20: I / Q message combination unit 21: frequency and phase determination unit

22: wobble signal recording unit 30, 50, 70: band pass filter

31,51,71: A / D converter 32,72: Slope detector

33,73: peak detector 34: wobble PLL circuit

35 component indicator 36 frequency and phase detector

37: address decoder 52: integrator

53: level slicer 54,74: clock detector

55,75: bit detector 56,76: address decoder

In accordance with another aspect of the present invention, there is provided a method of demodulating an optical disc wobble signal, comprising: performing a band pass filtering of an analog wobble signal read from an optical disc, and then performing A / D conversion to a digital wobble signal; Integrating the A / D-converted digital wobble signal after level integrating; Monitoring a level transition period of the level sliced pulse signal to detect a wobble data bit clock having a predetermined period; And detecting and outputting the original wobble data based on the level value of the level sliced pulse signal at the falling edge of the detected bit wobble data bit clock, wherein the three steps include: Time counts between each edge of the sliced pulse signal and calculates a cumulative average value for the time count value, while calculating the cumulative average value and the time count value between adjacent falling edges or rising edges of the pulse signal. By comparison, detecting the wobble data bit clock,

In addition, the demodulation method of the optical disc wobble signal according to the present invention includes a step of performing A / D conversion of a digital wobble signal after band-pass filtering the analog wobble signal read out from the optical disc; Detecting a peak point of the A / D-converted digital wobble signal and outputting a peak detection signal level shifted from the peak point; Monitoring a level transition period of the peak detection signal to detect a wobble data bit clock having a predetermined period; And detecting and outputting original wobble data based on a level value of the peak detection signal at the falling edge of the detected bit wobble data bit clock, wherein the three steps include the peak detection signal. Time counts between each edge of and calculates a cumulative average value for the time count value, comparing the cumulative average value with a time count value between adjacent falling edges or rising edges of the peak detection signal, The wobble data bit clock is detected.

Hereinafter, a preferred embodiment of a method for demodulating an optical disc wobble signal according to the present invention will be described in detail with reference to the accompanying drawings.

4 shows a configuration of an apparatus for modulating an optical disc wobble signal according to the present invention. The modulator includes an in-phase and quadrature message combiner 20, a frequency and phase determiner 21, and an MSK wobble signal recorder 22. The in-phase and quadrature message combiner At 20, as described above, the in-phase message m _I and the quadrature message m _Q of the wobble data to be recorded as the physical address information of the optical disc are always combined into ( m _I , m _Q ). .

On the other hand, in the frequency and phase determination unit 21, a combination value of ( m _I , m _Q ), that is, (1,1), (1,0), (0,1), (0,0) Depending on which one determines two different frequencies f ₁ , f ₂ and two phases P ₁ , P ₂ , four different waveforms, i.e. , , , And The MSK wobble signal is generated, wherein the first and second frequencies are determined to be values satisfying the following equation.

--- Equation (2)

--- Equation (3)

Here, K and P are natural numbers and K-P = 1 is satisfied.

That is, the frequency and phase determiner 21 determines the first and second frequencies f ₁ and f ₂ as values satisfying equations (2) and (3) defined by the MSK modulation scheme, respectively. However, if the values of K and P are natural and at the same time determine to have a value satisfying KP = 1, the minimum value of the MSK wobble signal is satisfied when the condition (K, P is a natural number, KP = 1) is satisfied. Alternatively, the maximum peak point is always formed at the time when the first frequency and the second frequency are changed.

For example, when the first frequency and the second frequency satisfy K = 3, P = 2, and KP = 1 , The case is determined in detail as follows.

First, as shown in FIG. 5, when the wobble data to be recorded on the optical disc is '00110' bit string data, the combination of the in-phase message m _I and the quadrature message m _Q is always ( m _I). , m _Q ), so that ( m _I , m _Q ) for the first bit '0' becomes (0,0) by combining with the second bit '0' and the second bit '0' For ( m _I , m _Q ) is (1,0) by combination with the third bit '1'.

Thus, by ( m _I , m _Q = 0,0) for the first bit '0', the second frequency f ₂ has a 180 degree phase π. Is generated, and has a first frequency (f ₁ ) and a zero phase by ( m _I , m _Q = 1,0) for the second bit '0'. Pulse signal is generated.

In addition, by ( m _I , m _Q = 1,1) for the third bit '1', a second frequency f ₂ and a zero phase are obtained. Pulse signal is generated and has a first frequency f ₁ and a 180 degree phase π by ( m _I , m _Q = 0,1) for the fourth bit '1'. Pulse signal is generated.

That is, when the values of K and P are natural numbers and have a value satisfying K-P = 1, the MSK wobble signal has a minimum / maximum peak point when the first frequency and the second frequency are changed.

On the other hand, as shown in Fig. 6, the demodulation device for demodulating the MSK wobble signal modulated and recorded as described above includes a band pass filter 30, an A / D converter 31, a slope detector 32, and a peak detector ( 33, wobble PLL circuit 34, component indicator 35, frequency and phase detector 36, and address decoder 37, which can be read from the optical disc in the band pass filter 30. The analog wobble signal of the push-pull signal is filtered to a predetermined frequency band to remove high frequency noise components and the like, and the A / D converter 31 converts the band pass filtered analog wobble signal into a digital wobble signal. Will be converted to.

The slope detector 32 monitors and detects the slope of the A / D-converted digital wobble signal, and the peak detector 33 minimizes the point where the detected slope is changed from negative to positive. The peak point is detected, the point where the detected slope is changed from positive to negative is detected as the maximum peak point, and the corresponding peak detection signal is output.

The wobble PLL circuit 34 outputs a wobble PLL signal synchronized with the peak detection signal, wherein the wobble PLL signal is the lowest frequency, that is, the lowest frequency among the plurality of frequencies included in the peak detection signal. It is synchronized to a pulse signal with a long period.

In the meantime, the component indicator 35 repeatedly outputs a component indication signal CI that is transitioned to a high / low level at the rising edge of the wobble PLL signal.

For example, as shown in FIG. 7, the MSK wobble signal output through the band pass filter 30 and the A / D converter 31 has two different frequencies f1 and f2 and two phases. In the case of the pulse signal ① having four waveforms , , , In the case where the peak detector 33 detects the point of time when the slope of the MSK wobble signal is switched from negative to positive, and the point of time from positive to negative, respectively, as the minimum / maximum peak point, and the minimum / maximum peak. At this point, the peak detection signal (2) which is shifted to the high / low level is output.

On the other hand, the wobble PLL circuit 34 outputs a wobble PLL signal ③ in which high / low levels are repeated by 50% in synchronization with the second frequency f2 of the peak detection signal, and the component indicator In (35), the component indication signal (4), which transitions to the high / low level at the rising edge of the wobble PLL signal, is generated and outputted, wherein the component indication signal, the peak detection signal, and the wobble PLL signal are respectively input. In the frequency and phase detector 36, as shown in Fig. 8, the peaks for each section ⓐ, ⓑ, ⓒ, ⓓ, ... corresponding to one wobble data bit width T _b . Comparing and calculating the detection signal PD and the wobble PLL signal PLL by an exclusive logical sum XOR And compare and integrate the peak detection signal PD and the indication signal CI with an exclusive logical sum XOR. )

Then, the integral value AB is detected and confirmed to be any one of a plurality of preset reference values, for example, Th1 = 0, Th2 = 33, Th3 = 50, Th4 = 66, and Th5 = 100. .

therefore. In the section ⓐ shown in FIG. 7, an integral value (A) obtained by comparing and integrating the peak detection signal PD and the wobble PLL signal PLL by an exclusive logical sum XOR is equal to Th5 = 100 when 100 is viewed as maximum. Since the values are close to each other, the second frequency and the 180-degree phase are detected with reference to the demodulation table shown in FIG. 8, and in the section ⓑ, an exclusive logical sum of the peak detection signal PD and the wobble PLL signal PLL ( Since the integral value A compared and integrated by XOR becomes a value close to Th3 = 50 when the maximum value is 100, the peak detection signal PD is detected while the first frequency is detected with reference to the demodulation table. ) And the component indication signal (CI) compared with the exclusive logic sum (XOR), the integral value (B) becomes close to Th2 = 33 when the maximum is 100, and thus the zero phase is detected. .

In the period ⓒ, the integral value A obtained by comparing and integrating the peak detection signal PD with the wobble PLL signal PLL by an exclusive logical sum XOR is a value close to Th1 = 0 when 100 is viewed as maximum. Therefore, the second frequency and the zero phase are detected with reference to the demodulation table. In the section ⓓ, the peak detection signal PD and the wobble PLL signal PLL are integrally integrated with an exclusive logical sum XOR. Since the integral value A becomes close to Th3 = 50 when the maximum is 100, the first frequency is detected with reference to the demodulation table, and the peak detection signal PD and the component indication signal ( Since the integral value B obtained by comparing CI) with the exclusive OR (XOR) becomes a value close to Th4 = 66 when the maximum is 100, the 180 degree phase is detected.

Accordingly, the frequency and phase detector 36 simply detects the frequency and phase for each MSK wobble signal section corresponding to one wobble data bit width T _b through the above-described process, and the frequency and phase information. Is output to the address decoder 37.

On the other hand, in the address decoder 37, on the basis of the detected frequency and phase, the combined ( m _I , m _Q ) values can be detected inversely when the MSK wobble signal is modulated. As shown in the figure, when the second frequency and the 180 degree phase are detected in the period ⓐ, since the value of ( m _I , m _Q ) becomes (0,0), the bit value of the wobble data is '0'. Is demodulated by

When the first frequency and zero phase are detected in the section ⓑ, the ( m _I , m _Q ) value becomes (1,0), so that the bit value of the wobble data is set to '0'. When the second frequency and zero phase are detected in the section ⓒ, the value of ( m _I , m _Q ) becomes (1,1), so that the bit value of the wobble data is '1'. When the first frequency and the 180-degree phase is detected in the section ⓓ, the value of ( m _I , m _Q ) becomes (0,1), and thus the bit value of the wobble data is set to '1'. As it is demodulated, the bit string of the original wobble data '0011 ..' is finally demodulated sequentially.

On the other hand, the optical disc wobble signal demodulation apparatus and method as described above use a peak detection signal level shifted at the peak point of the wobble signal and a wobble PLL circuit synchronized with the peak detection signal when demodulating the MSK wobble signal. By simply extracting the modulation frequency and phase information of the MSK wobble signal, and demodulating the MSK wobble signal based on the frequency and phase information, the hardware configuration for demodulating the MSK wobble signal can be simplified, as well as the optical disc. The stable wobble signal demodulation operation is possible even when the frequency of the wobble signal read out from the variable varies.

However, this requires a wobble PLL circuit. In addition, an algorithm and hardware configuration for determining the modulation frequency and phase are required. Hereinafter, the wobble PLL circuit is deleted, and the configuration of the algorithm and hardware for discriminating modulation frequency and phase can be omitted. A more detailed demodulation device and method for the same will be described in detail.

First, in the frequency and phase determination unit 21 described above with reference to FIG. 4, equations (2) and equations defining first and second frequencies f ₁ and f ₂ in the MSK modulation scheme are described. (3) is determined to satisfy each value, and the values of K and P are determined to be both natural and at the same time satisfying KP = 1, wherein the first frequency (f ₁ ) and the second frequency (f) are determined. ₂ ) each , (n is a natural number).

That is, it is determined that k value of the first frequency is 3 or more odd k = 2n + 1 and p value of the second frequency satisfies 2 or more even 2n smaller than k.

For example, when the k value of the first frequency is '3' and the p value of the second frequency is '2', the first frequency and the second frequency are: , In this case, the analog wobble signals 41 and 42 according to the first frequency are opposite to each other at the start peak and the end peak, as shown in FIG. The analog wobble signals 43 and 44 have the same start peak and end peak.

Accordingly, since the same operation is performed as the precoding by the exclusive logical sum (XOR) that compares the current data with the next data to '1' and the same data to '0', the waveforms of the analog wobble signals are free. The coded data is modulated as it is, resulting in a direct correlation with the original wobble bit data.

That is, since the start peak and the end peak of the analog wobble signal by the first frequency are mutually opposite to each other, the original wobble bit data '1' is modulated as it is, and the start peak and the end peak of the analog wobble signal by the second frequency are Since are equal to each other, the original wobble bit data '0' is modulated as it is.

On the other hand, as shown in FIG. 10, the demodulation device for demodulating the MSK wobble signal recorded and modulated as described above includes a band pass filter 50, an A / D converter 51, an integrator 52, and a level slicer 53. As shown in FIG. And a clock detector 54, a bit detector 55, and an address decoder 56. In the band pass filter 50, an analog of a push-pull signal read out from an optical disk is included. The wobble signal is filtered to a predetermined frequency band to remove high frequency noise components and the like, and the A / D converter 51 converts the band pass filtered analog wobble signal into a digital wobble signal.

In the integrator 52, as shown in FIG. 11, the A / D-converted digital wobble signal is integrated to become a zero point at the point where the wobble signal becomes a peak point. At the point where the wobble signal becomes a zero point, a pulse signal that becomes a peak point is output. The level slicer 53 slices the pulse signal output from the integrator 52 to a preset reference level. After that, the level sliced pulse signal is again inverted and the pulse signal output through the integrator 52 crosses the zero point to output a pulse signal that is level shifted. .

For example, as shown in FIG. 11, when the original wobble bit data '0100111011' is calculated by using an exclusive logical OR (XOR) and precoded, the precoded data becomes '110100110', and the first When modulating the analog wobble signal by the frequency and the second frequency, the levels of the start peak and the end peak are opposite to each other or have the same pulse waveform.

Accordingly, the pulse signal output after being level sliced by the integrator 52 and the level slicer 53 has two kinds of periods in which the periods of the level transition points are different from each other. ) Detects the period of the level transition point, respectively, and detects and outputs a bit clock signal of a constant period that is the least common multiple of two different kinds of periods.

On the other hand, as shown in Fig. 11, the constant clock bit clock is a clock signal having the same period as the bit transition point of the original wobble bit data. In the bit detector 55, the bit clock signal falls. At the edge, the level value of the level sliced pulse signal output from the level slicer 53 is detected and confirmed.

At this time, the bit detector 55, at the falling edge of the detected bit clock signal, a wobble of '0' if the level value of the level sliced pulse signal is low, and '1' if it is high The data is detected and output.

Accordingly, since the decoded data detected and output by the bit detector 55 is demodulated to the same value of '0100111011' as the original wobble data sequence as shown in FIG. 11, as described above, the wobble PLL circuit It is not necessary to use and it is also possible to omit the configuration of the algorithm and hardware for the modulation frequency and phase discrimination.

Meanwhile, an optical disc wobble signal demodulation device and method according to another embodiment of the present invention will be described.

First, as shown in FIG. 12, a demodulation device for demodulating the MSK wobble signal includes a band pass filter 70, an A / D converter 71, a slope detector 72, a peak detector 73, and a clock detector ( 74, the bit detector 75, and the address decoder 76, the band pass filter 70, the analog wobble signal of the push-pull signal read from the optical disk to a predetermined frequency The band-pass filtering removes high frequency noise components and the like, and the A / D converter 71 converts the band-pass filtered analog wobble signal into a digital wobble signal.

The slope detector 72 monitors and detects the slope of the A / D-converted digital wobble signal, and the peak detector 73 minimizes the point where the detected slope is changed from negative to positive. The peak point is detected, the point where the detected slope is changed from positive to negative is detected as the maximum peak point, and the corresponding peak detection signal is output.

For example, as shown in FIG. 13, when the original wobble bit data '0100111011' is calculated by using an exclusive OR, the precoded data becomes '110100110', and the first coded data is '110100110'. When modulating the analog wobble signal by the frequency and the second frequency, the levels of the start peak and the end peak are opposite to each other or have the same pulse waveform.

Therefore, the peak detection signal decoded and output by the address decoder 76 has two kinds of periods in which the periods of the level transition points are different from each other. In this case, the clock detector 74 determines the level transition points. Each cycle is detected, and a bit clock signal having a constant cycle which is the least common multiple of two different cycles is detected and output.

On the other hand, as shown in Fig. 13, the constant clock bit clock is a clock signal having the same period as the bit transition point of the original wobble bit data. In the bit detector 75, the bit clock signal falls. At the edge, the level value of the peak detection signal detected and output from the peak detector 73 is detected and confirmed.

At this time, the bit detector 75, at the falling edge of the detected bit clock signal, if the level value of the peak detection signal is Low (0), if the high (W1), wobble data of "1" Detection output.

Therefore, as shown in FIG. 13, the decoded data output by the address decoder 76 is demodulated to the same value of '0100111011' as the original wobble data sequence. It is not necessary to use, and also the configuration of algorithms and hardware for the modulation frequency and phase discrimination can be omitted.

Meanwhile, in the clock detectors 54 and 74 described above with reference to FIGS. 10 to 13, the level sliced pulse signal output from the level slicer 53 or the peak detected and output from the peak detector 73. The bit clock detection method for monitoring the level transition period of the detection signal and accurately detecting the bit clock signal of the predetermined period will be described in detail as follows.

First, in the clock detectors 54 and 74, as shown in Figs. 14 and 15, time counts between the edges of the peak detection signal or the pulse signal sliced after integration, and the time count value. It is repeated to calculate and update the cumulative average value (T _avg ) for (S10), in practice, since the pulse values of the short period in the MSK wobble signal is less than about 10% of the total, the cumulative average value is The time count value for the long period of the MSK wobble signal gradually becomes approximately the same.

On the other hand, in the clock detector, time counting is performed between falling edges of the peak detection signal or the pulse signal sliced after integration, and the time count value T _ff is compared with the accumulated average value T _avg . It is made (S11).

For example, as shown in Fig. 15, the time count value (T _1-3 ) between the first falling edge (1) to the next falling edge (3) of the peak detection signal or the level sliced pulse signal after integration. ) Is 120 and the cumulative average value T _avg is 174, the bit detector determines that the time count value T _1-3 between the falling edges 1-3 is smaller than the cumulative average value. (T _1-3 <T _avg ), the next rising edge 4 is detected, and the time count value T _1-4 until then is compared with the cumulative average value again, wherein the time count If the value is 180 which is greater than the cumulative average value 174, the bit clock is level shifted and the time count value T _1-4 is initialized to zero (S12).

Subsequently, time counting is performed between rising edges. If the time count value T _1-3 between the falling edges is larger than the cumulative average value (T _1-3 > T) _avg ), the clock detector level shifts the bit clock, initializes the time count value (T _1-3 ), counts the time between the next falling edges (3-5) and counts the time A series of operations of comparing the values T _3-5 with the cumulative average value T _avg is repeated (S13).

On the other hand, in the clock detector, when the time count between the rising edges (Rising Edge) through the above process, for example, as shown in Figure 15, the second rising edge (4) from the next The time is counted between the rising edges 6, and the time count value T _4-6 is compared with the cumulative average value (S14).

When the time count value T _4-6 is 120 and the cumulative average value T _avg is 174, the clock detector determines the time count value T ₄ between the rising edges 4-6. _-6 ) determines that it is smaller than the cumulative average value (T _4-6 < T _avg ), and detects the next falling edge 7, and accumulates the time count value T _4-7 until then. When the time count value is 180 which is greater than the cumulative average value 174, the bit clock is level shifted and the time count value T _4-7 is initialized to zero. (S15).

After that, time counting is again performed between falling edges. If the time count value T _4-6 between the rising edges is greater than the cumulative average value (T _4-6 > T _avg ), the clock detector level shifts a bit clock, initializes the time count value T _4-6 , and then counts the time between the next rising edges 6-8 to determine the time. A series of operations of comparing the count value T _6-8 with the cumulative average value T _avg is repeatedly performed (S16).

Therefore, the clock detector repeats the above-described process, and thus accurately detects and outputs a bit clock signal of a predetermined period as shown in FIG. 15.

On the other hand, the bit clock detection operation as described above, as shown in FIG. 16, may start at the next falling edge (eg, the second falling edge 3) instead of the first falling edge (1). It may be.

In this case, the clock detector compares the time count value T _3-5 between the second falling edge 3 and the next falling edge 5 with the cumulative mean value, wherein the time count The value T _3-5 becomes 120 smaller than 174 which is a cumulative average value T _avg .

Accordingly, the clock detector detects the next rising edge 6 as described above, and compares the time count value T _3-6 up to that time with the cumulative average value again. When the time count value is 180 greater than the cumulative average value 174, the bit clock is level shifted, and the time count value T _3-6 is initialized to zero.

Then, after that time is counted between the rising edges (Rising Edges), time counting between the third rising edge (6) and the next rising edge (8), the time count value (T _6-8 ) Is compared with the cumulative mean value.

On the other hand, when the time count value T _6-8 is 150 and the cumulative average value T _avg is 174, in the clock detector, the time count value T ₆ between the rising edges 6-8 is obtained. _-8 ) determines that it is smaller than the cumulative average value (T _6-8 < T _avg ), and detects the next falling edge 9, and accumulates the time count value T _6-9 until then. When the time count value is 240 which is greater than the cumulative average value 174, the bit clock is level shifted and the time count value T _6-9 is initialized to zero. .

Then, since time counts again between falling edges, as described above with reference to FIG. 15, a normal bit clock detection operation is performed to automatically correct a bit clock detection error. You can do it.

Or more, preferred embodiments of the present invention described above, which is posted for the purpose of illustration, those skilled in the art to improve the various other embodiments within the spirit and technical scope of the present invention disclosed in the appended claims below Changes, substitutions or additions will be possible.

The optical disc wobble signal demodulation method according to the present invention constructed and constructed as described above monitors the level transition period of a pulse signal or a peak detection signal of a wobble signal that is level sliced after integration of the wobble signal, Detecting a wobble data bit clock having a period and detecting and outputting the original wobble data on the falling edge of the wobble data bit clock based on the level value of the level sliced pulse signal, wherein the level sliced pulse signal Or time counting between each edge of the peak detection signal to calculate a cumulative average value for the time count value, and the calculated cumulative average value and adjacent falling edges or rising edges of the pulse signal or the peak detection signal. Accurate wobble days by comparing the time count value between them and detecting the wobble data bit clock In addition to being able to detect the terbit clock, it is a very useful invention that can automatically correct the detection error of the wobble data bit clock.

Claims (10)

Performing band pass filtering of the analog wobble signal read out from the optical disc, and then performing A / D conversion to a digital wobble signal; Integrating the A / D-converted digital wobble signal after level integrating; Monitoring a level transition period of the level sliced pulse signal to detect a wobble data bit clock having a predetermined period; And And detecting and outputting the original wobble data based on the level value of the level sliced pulse signal at the falling edge of the detected wobble data bit clock. The step 3 includes time counting between each edge of the level sliced pulse signal, calculating a cumulative average value for the time count value, and the cumulative average value and adjacent falling edges or rising edges of the pulse signal. And demodulating the wobble data bit clock by comparing time count values between them. The method of claim 1, In step 3, when the cumulative average value T _avg is compared with a time count value T _ff between adjacent falling edges of the pulse signal, the time count value is larger (T _ff > T). _avg ) Level shifting the bit clock, initializing the time count value, and then comparing the time count value T _ff between the next falling edge with the cumulative average value again. . The method of claim 1, In the step 3, when the cumulative average value is compared with a time count value between adjacent falling edges of the pulse signal, when the time count value is smaller (T _ff <T _avg ), until the next rising edge When the time count value T _fr is compared with the cumulative mean value and the time count value is larger than the cumulative mean value (T _fr > T _avg ), the bit clock is level shifted to initialize the time count value. After that, the time count value (T _rr ) between the next rising edge is compared with the cumulative average value again. The method of claim 3, wherein In step 3, when the time count value T _rr between the next rising edge is compared with the cumulative average value, when the time count value is larger (T _rr > T _avg ), the bit clock is level shifted. And initializing the time count value, and then comparing the time count value (T _rr ) between the next rising edges with the cumulative average value again. The method of claim 4, wherein In step 3, when the time count value between the next rising edge is compared with the cumulative average value, when the time count value is smaller (T _{rr <} T _avg ), the time count value until the next falling edge is obtained. If (T _rf ) is compared with the cumulative average value and the time count value is larger than the cumulative average value (T _rf > T _avg ), the bit clock is level shifted, and after the time count value is initialized, And demodulating the time count value (T _ff ) between falling edges with said cumulative average value again. Performing band pass filtering of the analog wobble signal read out from the optical disc, and then performing A / D conversion to a digital wobble signal; Detecting a peak point of the A / D-converted digital wobble signal and outputting a peak detection signal level shifted from the peak point; Monitoring a level transition period of the peak detection signal to detect a wobble data bit clock having a predetermined period; And On the falling edge of the bit clock of the detected wobble data, based on the level value of the peak detection signal, comprising the four steps of detecting and outputting the original wobble data, The step 3 includes time counting between each edge of the peak detection signal and calculating a cumulative average value for the time count value, while the cumulative average value and adjacent falling edges or rising edges of the peak detection signal are calculated. And demodulating the wobble data bit clock by comparing time count values therebetween. The method of claim 6, In step 3, when the cumulative average value T _avg is compared with a time count value T _ff between adjacent falling edges of the peak detection signal, the time count value is larger (T _ff > T _avg ) level shifts the bit clock, initializes the time count value, and then compares the time count value T _ff between the next falling edge with the accumulated average value again. Way. The method of claim 6, In step 3, when the cumulative average value is compared with a time count value between adjacent falling edges of the peak detection signal, when the time count value is smaller (T _ff <T _avg ), the next rising edge When the time count value T _fr is compared with the cumulative mean value, and the time count value is larger than the cumulative mean value (T _fr > T _avg ), the bit clock is level shifted and the time count value is initialized. And then comparing the time count value (T _rr ) between the next rising edge with the cumulative average value again. The method of claim 8, In step 3, when the time count value T _rr between the next rising edge is compared with the cumulative average value, when the time count value is larger (T _rr > T _avg ), the bit clock is level shifted. And initializing the time count value, and then comparing the time count value (T _rr ) between the next rising edges with the cumulative average value again. The method of claim 9, In step 3, when the time count value between the next rising edge is compared with the cumulative average value, when the time count value is smaller (T _{rr <} T _avg ), the time count value until the next falling edge is obtained. If (T _rf ) is compared with the cumulative average value and the time count value is larger than the cumulative average value (T _rf > T _avg ), the bit clock is level shifted, and after the time count value is initialized, And demodulating the time count value (T _ff ) between the falling edges with the cumulative average value again.