KR20030065816A - Circuit of driving for responsing high speed thin flim transistor liquid display - Google Patents

Abstract

PURPOSE: A driving circuit for high-speed response in a TFT LCD is provided to increase a response time and reduce the number of frame memories to the halves by compensating present input data by virtual data. CONSTITUTION: A driving circuit for high-speed response in a TFT LCD includes an A/D conversion portion(10), the first and the second frame memory portions(40), a scaler IC portion(20), and a micro computer portion(30). The A/D conversion portion receives RGB analog data, a vertical synchronous signal, and a vertical synchronous signal and generates RGB digital data. The first and the second frame memory portions stores even data and odd data, respectively. The scaler IC portion receives the RGB data and the frame data and generates the corrected data when the (n-1)th frame data is different from the nth frame data. The micro computer portion controls the A/D conversion portion, the first and the second frame memory portions, and the scaler IC portion.

Description

CIRCUIT OF DRIVING FOR RESPONSING HIGH SPEED THIN FLIM TRANSISTOR LIQUID DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for high-speed response of a thin film transistor liquid crystal display (TFT-LCD). In particular, when intermediate luminance data is input from a scaler, virtual data is currently input. The present invention relates to a driving circuit for a high-speed response of a TFT-LCD which compensates for the increase in a response time of a TFT LCD.

When using a TFT-LCD, the response time of the liquid crystal depends on the magnitude of the applied voltage. In particular, when the data changes near the intermediate luminance L127 (L100 at L127 or L127 at L100), the response time of the white level L255 is usually increased by 3 to 4 times higher than the response time of the black level L0 at the white level L255. Therefore, when driving a moving image having a lot of intermediate brightness with a TFT LCD, the output image is blurred. In order to solve this disadvantage, conventionally, as shown in FIG. 1, a separate data processing unit for fast response is required.

Referring to FIG. 1, the driving circuit of the TFT-LCD includes an LCD panel 1, a source driver 2, a gate driver 3, a source / gate control signal generator 4, a connector 5, and a data processing unit. (6), frame memory 7 and ROM 8;

The data processing unit compensates the virtual data to the n th frame data currently input when the intermediate luminance data of the (n-1) th frame is input. This compensated data is applied to the TFT LCD panel to reduce the response time, thereby enabling high speed response.

However, the drive circuit of the conventional TFT-LCD configured as described above requires a high speed response processing chip for the high speed data processing unit and a separate frame memory, thereby increasing the layout area and increasing the manufacturing cost. .

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to compensate for virtual data to current input data when intermediate luminance data is input from a scaler, thereby providing a response time of a TFT LCD. To provide a driving circuit for the high-speed response of the TFT-LCD that can increase the number of times, and reduce the number of frame memories in half.

1 is a block diagram of a driving circuit of a TFT-LCD according to the related art.

2 is a block diagram of a driving circuit for fast response of a TFT-LCD according to the present invention;

3 is a block diagram of a frame data compensator included in the scaler IC shown in FIG.

FIG. 4 is a detailed block diagram of the frame data compensator shown in FIG.

FIG. 5 is another detailed block diagram of the frame data compensator shown in FIG.

FIG. 6 is another detailed block diagram of the frame data compensator shown in FIG.

[Description of Code for Major Parts of Drawing]

10: AD converter 20: scaler IC

30: micom 40: frame memory

100: AD conversion block unit 200: frame data compensation unit

210: comparator 220: look-up table

230: Adder 241, 244, 341, 344, 441, 444: buffer

250, 350, 450: multiplexer260, 360, 460: delay

310, 410: subtractor 320, 420: AD converter

330, 430: Decoder / Lookup Table 340, 440: Adder

The driving circuit of the TFT-LCD according to the present invention for achieving the above object,

An AD converter which receives the RGB analog data, the vertical synchronization signal, and the horizontal synchronization signal to generate RGB digital data;

First and second frame memory sections for storing even and odd frame data, respectively;

A scaler IC which receives the RGB digital data and the frame data and compares the contents of the (n-1) th frame data and the n th frame data and generates n th frame data which compensates for the difference when the data of the two frames are different from each other. Wealth,

And a micom unit for controlling the operation of the AD converter, the first and second frame memory units, and the scaler IC unit, respectively.

The scaler IC unit outputs a result of receiving and comparing the nth frame data and the (n-1) th frame data, and a look that receives an output signal of the comparator and stores a value corresponding to the output signal. And an adder for receiving the n-th frame data and the output signal of the look-up table and outputting the sum value.

The result of the comparator is three kinds: + (nth data> (n-1) th data),-(nth data <(n-1) data), 0 (nth data = (n-1) th data) It is characterized by having a case.

The look-up table is characterized by using a ROM (ROM).

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

FIG. 2 is a block diagram of a driving circuit for fast response of a TFT-LCD according to the present invention, and FIG. 3 is a block diagram of a frame data compensator included in the scaler IC 20 shown in FIG.

The drive circuit of FIG. 2 is composed of an AD converter 10, a scaler IC 20, a microcomputer 30, and a frame memory 40.

The AD converter 10 receives an analog signal (Analog RGB) of the RGB pixel, a vertical synchronization signal (Vsync), and a horizontal synchronization signal (Hsync) to generate a digital signal of the RGB pixel.

As shown in FIG. 3, the scaler IC 20 includes a comparator 120, a look-up table 220, and an adder 230. The scaler IC 20 compares the contents of the (n-1) th frame data and the n th frame data and finds a value considering the difference in the look-up table 220 when the data of the two frames are different from each other. Compensate for frame data.

The result of the comparator 120 is + (n th data> (n-1) th data),-(n th data <(n-1) data), 0 (n th data = (n-1) th data) ) Can have three cases. Two frame memories are required to implement this function, and each frame memory stores even and odd frame data.

Since the look-up table 220 should have a value suitable for the result of the comparator 210, a ROM should be used.

4 is a detailed block diagram of the frame data compensator 100 illustrated in FIG. 3.

As shown, the frame data compensator 200 receives the RGB digital data and transmits the first buffer 241 to the first frame memory 42 and the output of the first frame memory 42. The first clock buffer 242 outputs a signal to the multiplexer 250 by a control signal Con, and the RGB digital data is received and transmitted to the second frame memory 44 by the control signal Con. A second clock buffer 243, a second buffer 244 that receives an output signal of the second frame memory 243 and outputs the output signal to the multiplexer 250, and an output signal of the first clock buffer 242. And a multiplexer 250 that receives the output signal of the second buffer 244 and selects and outputs one by the control signal Con, and a delay 260 that outputs a signal delayed by receiving the RGB digital signal. ), The output signal of the multiplexer 250 and the A comparator 210 receiving the output signal of the delay 260 and outputting a result of comparing the two signals, and a look-up receiving the output signal of the comparator 210 and storing a value corresponding to the output signal. And a table 220 and an adder 230 which receives the n-th frame data and the output signal of the look-up table and outputs the sum of the n-th frame data.

The control signal Con for controlling the operation of the first and second clock buffers 242 and 243 determines in which frame memory the received RGB digital data is written. When the control signal Con is 'high', the frame (nth frame) RGB digital data currently input to the first frame memory 42 is stored, and at the same time, the (n-1) th frame of the (n-1) th frame is stored in the second frame memory 44. Read RGB digital data.

In addition, when the control signal Con becomes 'low', the opposite operation is performed. The digital data of the frame memory selected by the multiplexer 250 is compared with the currently input data (n-th frame), and the corresponding value is found in the look-up table 220 by the difference. The output value of the look-up table 220 calculates panel data by operating with the currently input data.

The output value of the comparator shown in FIG. 4 exists only in three cases of +,-, 0. The meaning of these three cases is that there are only three conditions to compensate. Subtractors are used instead of comparators to realize a wide range of compensation conditions.

FIG. 5 is another detailed block diagram of the frame data compensator shown in FIG. 3.

As shown, the frame data compensator 300 receives the RGB digital data and transmits the first buffer 341 to the first frame memory 142 and the output of the first frame memory 142. The first clock buffer 342 outputs a signal to the multiplexer 350 by a control signal Con, and the RGB digital data is received and transmitted to the second frame memory 144 by the control signal Con. A second clock buffer 343, a second buffer 344 that receives an output signal of the second frame memory 144 and outputs the output signal to the multiplexer 350, and an output signal of the first clock buffer 342. And a multiplexer 350 that receives an output signal of the second buffer 344 and selects and outputs one by the control signal, and a delay 360 that outputs a signal delayed by receiving the RGB digital signal. The output signal of the multiplexer 350 and the A subtractor 310 receiving the output signal of the ray 360 and outputting a result of comparing the two signals, an AD converter 320 receiving the output signal of the subtractor 310 and converting the digital signal into a digital signal; A decoder and look-up table 330 which receives an output signal of the AD converter 320 and stores a value corresponding to the output signal, an output signal of the delay 360 and the decoder and look-up table ( And an adder 340 for receiving the output signal of the output unit 330 and outputting the added value.

As shown in FIG. 5, the output of the subtractor 310 becomes an analog voltage, so that the analog voltage is converted to digital using the AD converter 320. This digital data becomes the address of the look-up table.

FIG. 6 is another detailed block diagram of the frame data compensator shown in FIG. 3. In addition, the video image speed detector 435 is further configured in FIG. 5 in consideration of the video image speed. The output signal of the moving image speed detector 435 is input to the decoder and the lookup table 430.

The driving circuit for the high speed response of the TFT-LCD according to the present invention can be used in the field of TFT LCD which requires moving picture and high speed response. The present invention can also be applied to flat panel displays having low-speed response characteristics.

As described above, according to the driving circuit for the high-speed response of the TFT-LCD according to the present invention, when intermediate luminance data is input from the scaler, the response time of the TFT LCD is compensated by compensating the virtual data to the currently input data. You can increase the response time and cut the number of frame memories in half. Therefore, the cost can be reduced because the number of frame memories can be reduced by half. It can also be applied to displays with slow response characteristics.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (7)

An AD converter which receives the RGB analog data, the vertical synchronization signal, and the horizontal synchronization signal to generate RGB digital data; First and second frame memory sections for storing even and odd frame data, respectively; A scaler IC that receives the RGB digital data and the frame data and compares the contents of the (n-1) th frame data and the nth frame data and generates nth frame data that compensates for the difference when the data of the two frames are different from each other. Wealth, And a micom unit for controlling the operation of the AD converter, the first and second frame memory units, and the scaler IC unit, respectively. The method of claim 1, wherein the scaler IC unit, A comparator for outputting a result of receiving and comparing the nth frame data and the (n-1) th frame data; A look-up table that receives an output signal of the comparator and stores a value corresponding to the output signal; And an adder for receiving the n-th frame data and the output signal of the look-up table and outputting the sum of the n-th frame data and the output signal of the look-up table. The method of claim 2, The result of the comparator is three kinds: + (nth data> (n-1) th data),-(nth data <(n-1) data), 0 (nth data = (n-1) th data) A drive circuit for high speed response of a TFT-LCD characterized by having a case. The method of claim 2, And said look-up table uses a ROM. The method of claim 1, wherein the scaler IC unit, A first buffer which receives the RGB digital data and transmits the RGB digital data to the first frame memory; A first clock buffer configured to output an output signal of the first frame memory to a multiplexer by a control signal; A second clock buffer which receives the RGB digital data and transmits the RGB digital data to a second frame memory by the control signal; A second buffer receiving the output signal of the second frame memory and outputting the output signal to the multiplexer; A multiplexer which receives an output signal of the first clock buffer and an output signal of the second buffer, selects and outputs one by the control signal; A delay for receiving the RGB digital signal and outputting a delayed signal; A comparator configured to receive an output signal of the multiplexer and an output signal of the delay and output a result of comparing the two signals; A look-up table that receives an output signal of the comparator and stores a value corresponding to the output signal; And an adder for receiving the n-th frame data and the output signal of the look-up table and outputting the sum of the n-th frame data and the output signal of the look-up table. The method of claim 1, wherein the scaler IC unit, A first buffer which receives the RGB digital data and transmits the RGB digital data to the first frame memory; A first clock buffer configured to output an output signal of the first frame memory to a multiplexer by a control signal; A second clock buffer which receives the RGB digital data and transmits the RGB digital data to a second frame memory by the control signal; A second buffer receiving the output signal of the second frame memory and outputting the output signal to the multiplexer; A multiplexer which receives an output signal of the first clock buffer and an output signal of the second buffer, selects and outputs one by the control signal; A delay for receiving the RGB digital signal and outputting a delayed signal; A subtractor for receiving an output signal of the multiplexer and an output signal of the delay and outputting a result of comparing the two signals; An AD converter which receives the output signal of the subtractor and converts it into a digital signal; A decoder and look-up table for receiving an output signal of the AD converter and storing a value corresponding to the output signal; And an adder for receiving the output signal of the delay and the output signal of the decoder and the look-up table and outputting the added value. The method of claim 6, And a moving picture image speed detecting unit for generating a signal detecting a moving picture image speed to the decoder and a lookup table.