KR20030064434A - Wakeup apparatus and method for detecting existence of signal in twisted pair line - Google Patents

Abstract

PURPOSE: A wakeup device for detecting signals on a twisted pair line and a method therefor are provided to check whether signals exist on the twisted pair line only by using a pure logic process without an additional circuit, thereby automatically waking up a corresponding data transceiving device. CONSTITUTION: The first and the second bypass capacitor(C1,C2) extract alternating current components existing in two signals inputted from a twisted pair line(90). A signal-clock converter(2624) amplifies the alternating current signals generated from the first and the second bypass capacitor(C1,C2) and converts the amplified signals into digital signals. A clock generator generates clocks by responding to the digital signals outputted from the signal-clock converter(2624). An up-counter(2660) counts the number of the clocks. And a comparator(2680) compares the number of the counted clocks with a predetermined reference value, to generate a control signal to wake up a data transceiving device if the number of the clocks is larger than the reference value.

Description

Wakeup apparatus and method for detecting existence of signal in twisted pair line}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication device and a method thereof. In particular, a data transmission / reception terminal using a twisted pair line detects the presence of a signal in a line and automatically wakes up the data transmission / reception device according to a detection result. It relates to a device and a method for up.

In order to determine the existence of a signal on twisted pair lines, which are mainly used in telephone lines, analog signals are converted into digital signals using an analog to digital convertor (ADC), and then a specific frequency component is analyzed through fast fourier transform (FFT) analysis. The method of detecting is mainly used. However, this method has a disadvantage in that the analog-to-digital conversion must be continuously performed and the DSP (Digital Signal Processor) for processing the converted digital signal is continuously operated, which leads to high power consumption and complicated circuit configuration. .

In order to solve this problem, U. S. Pat. No. 6,087,860, "APPARATUS AND METHOD FOR GENERATING AN ENVELOPE FOR DATA SIGNALS USING CMOS", detects the envelope of the signal and detects the signal in the twisted pair line. However, since such a circuit requires a separate CMOS analog circuit, there is a problem that the circuit becomes complicated and the manufacturing cost accordingly increases.

The present invention provides an apparatus and method for automatically detecting a presence of a signal on a twisted pair line using a pure logic process without a separate circuit, and automatically waking up a corresponding data transmission / reception apparatus using the same.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of the drawings is provided.

1 is a block diagram showing a general configuration of a data transmission and reception apparatus using a twisted pair line.

2 is a block diagram showing a detailed configuration of an analog front end (AFE) equipped with a wake-up detection apparatus according to the present invention.

FIG. 3 is a block diagram illustrating a detailed configuration of the wakeup circuit illustrated in FIG. 2.

FIG. 4 is a detailed circuit diagram of the signal-clock conversion circuit shown in FIG. 3.

FIG. 5 is a diagram illustrating waveforms of input signals input through nodes A1 and A2 illustrated in FIG. 4.

FIG. 6 is a view illustrating waveforms of an output signal output through the RS flip-flop shown in FIG. 4.

7 is a flowchart illustrating a wake-up method according to a preferred embodiment of the present invention for automatically waking up a data transmission / reception apparatus by detecting the presence of a signal in a twisted pair line.

<Description of Symbols for Main Parts of Drawings>

1, 1 ': data transceiver 90: twisted pair line

100, 100 'interface 200, 200': AFE

220: TX path function block 240: RX path function block

260: wake-up circuit 280: clock generator

300, 300 ': Digital modem 500, 500': Application

A wake-up device of a data transmission / reception apparatus using a twisted pair line according to the present invention for achieving the above technical problem comprises: first and second bypasses for extracting an AC component present in two signals input from the twisted pair line; Capacitors; A signal converter configured to amplify the AC signals generated from the first and second bypass capacitors and convert the amplified signals into digital signals, respectively; A clock generator which generates a clock in response to the digital signals output from the signal converter; A counter for counting the number of clocks; And a comparator for comparing the counted clock number with a predetermined reference value and generating a control signal to wake up the data transmission / reception apparatus when the number of clocks is greater than the reference value.

A wake-up method of a data transmission / reception apparatus using a twisted pair line according to the present invention for achieving the above technical problem comprises: (a) receiving two signals having different phases from the twisted pair line; (b) amplifying the alternating current components of the two signals and converting each of the amplified signals into digital form; (c) generating a clock signal in which values of 0 and 1 are alternately output when the converted digital signals have different values; (d) counting the number of clocks and comparing the counted number of clocks with a predetermined reference value; And (e) waking up the data transceiver when the number of clocks is greater than the reference value as a result of the comparison in step (d).

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a block diagram showing a general configuration of a data transceiver 1, 1 'using a twisted pair line. Referring to FIG. 1, a data transceiver 1, 1 ′ connected through a twisted pair line 90 may be classified into a physical layer 10, 10 ′, and a link layer 30, 30 ′. And an application layer (50, 50 ').

The physical layers 10 and 10 'include interfaces 100 and 100' that directly interface with communication lines, high speed A / D converters for converting data input and output through the interfaces 100 and 100 ', Analog front ends (200, 200 ') (hereinafter referred to as AFEs) with D / A converters and high frequency components are included. The link layer 30, 30 'has a digital modem 300, 300' for interpreting signals received through the AFE 200, 200 'according to a prescribed data format and correcting errors contained in the data. Included. The application layers 50 and 50 'include applications 500 and 500' that make the data processed by the data transceiving devices 10 and 10 'into a form that a user can actually see or hear.

2 is a block diagram showing a detailed configuration of the AFE 200 equipped with a wake-up detection apparatus according to the present invention. Referring to FIG. 2, the AFE 200 includes a TX path function block 220, an RX path function block 240, a wakeup circuit 260, and a clock generator 280.

The TX path function block 220 transmits a signal input from the digital modem 300 to another data transmission / reception apparatus through the interface 100. The RX path function block 240 receives a signal input from another data transceiver through the interface 100 and transmits the signal to the digital modem 300.

The wakeup circuit 260 is connected to the RX receiving end of the interface 100 to detect whether a signal is present on the twisted pair line 90, and if a signal is present on the twisted pair line 90, the clock is present. The generator 280 generates the clock enable signal CLK_EN. The clock generator 280 generates a main clock signal for the data transceiver 1 and 1 ′ to the digital modem 300 in response to the clock enable signal CLK_EN generated from the wakeup circuit 260. As a result, the data transmission / reception apparatuses 1 and 1 'are automatically woken up to perform the data transmission / reception operation.

3 is a block diagram illustrating a detailed configuration of the wakeup circuit 260 of FIG. 2. Referring to FIG. 3, the wakeup circuit 260 includes a signal-clock conversion circuit 2620, an RS flip-flop 2640, an up counter 2660, and a comparator 2680. .

The signal-clock converter 2620 includes a signal input unit 2622 and a signal-clock converter 2624. First and second bypass capacitors C1 and C2 are respectively connected between the twisted pair line 90 and the signal input unit 2622.

The first and second bypass capacitors C1 and C2 remove a direct current (DC) component present in a signal input from the twisted pair line 90, and convert an alternating current (AC) component present in the signal into a signal input unit ( 2622). At this time, the two signals input from the twisted pair line 90 to the signal input unit 2622 have different phases. The first and second bypass capacitors C1 and C2 allow the DC components of the two signals transmitted to the signal input unit 2622 through the A1 and A2 nodes to be separated from each other.

The signal input unit 2622 receives the AC signal transmitted from the first and second bypass capacitors C1 and C2 and transmits it to the signal-clock converter 2624. The signal-clock converter 2624 amplifies the input AC signal, converts the amplified signal into a digital signal, and outputs the digital signal.

The two AC signals converted into digital form through the signal-clock converter 2624 are input to the R and S terminals of the RS flip-flop 2640, respectively. The operation of the RS flip-flop 2640 by the signal input to the RS flip-flop 2640 through the signal-clock converter 2624 is shown in Table 1 below.

TABLE 1

R S Q 0 0 Q (n) 0 One One One 0 0 One One X

Referring to [Table 1], the RS flip-flop 2640 outputs an output signal in the form of a digital clock signal in which values of 0 and 1 are repeated when a signal input to R and a signal input to S have different values. Det) is generated. That is, the RS flip-flop 2640 is a digital clock signal Det whose values of 0 and 1 are repeated when two AC signal values converted into a digital form through the signal-clock converter 2624 have different phases. Will occur.

The output signal Det of the RS flip-flop 2640 is input to the up counter 2660, and the value counted by the up counter 2660 is input to the comparator 2680. The count value of the up counter 2660 increases as the number of input clocks increases.

The comparator 2680, which has received the value counted by the up counter 2660, compares the count value with the reference value Ref. As a result of the comparison, when the counted value is larger than the reference value Ref, the comparator 2680 generates the clock enable signal CLK_EN to the clock generator 280. The clock enable signal CLK_EN is used as a start signal for operating the entire data transceiver. The clock generator 280 operates the data transceivers 1 and 1 'in response to the clock enable signal CLK_EN. It generates the main clock signal needed to achieve this.

4 is a detailed circuit diagram of the signal-clock conversion circuit 2620 shown in FIG. Referring to FIG. 4, the signal input unit 2622 may include a first resistor R1 connected between first and second external input pins P1 and P2 that are external to the system, and third and third devices that are external to the system. And a second resistor R2 connected between the external input pins P3 and P4, respectively. One terminal of the first resistor R1 connected to the first external input pin P1 is connected to one terminal of the first bypass capacitor C1 and the second resistor R2 connected to the third external input pin P3. One terminal of) is connected to one terminal of the second bypass capacitor C2, respectively, and receives an input signal of the AC component AC from the twisted pair line 90, respectively.

The signal-clock converter 2624 amplifies an AC signal input through the signal input unit 2622 and converts it into a digital signal form. To this end, the signal-clock converter 2624 includes a first inverter having an input terminal connected to the first external input pin P1 and an output terminal connected to the second external input pin P2, and the first inverter. And second and third inverters connected in series to the output terminal. The signal-clock converter 2624 includes a fourth inverter having an input terminal connected to a third external input pin P3 and an output terminal connected to a fourth external input pin P4, and the fourth inverter. And fifth and sixth inverters connected in series with the output terminals.

The first to sixth inverters include one PMOS transistor (MP11, MP12, ..., MP23) and one NMOS transistor (MN11, MN12, ..., MN23) having a current path connected in series between a power supply voltage and a ground voltage. It includes each.

The first and fourth inverters of these inverters operate as push-pull amplifiers, respectively, and the outputs of the first and fourth inverters are the second and fourth external input pins P2 and P4, respectively. Is passed). The first and fourth inverters acting as amplifiers occupy less area and have larger bandwidths than with conventional differential amplifiers.

As shown in FIG. 4, the second and fourth external input pins P2 and P4 connected to the output terminals of the first and fourth inverters are connected to one terminal of the first and second resistors R1 and R2. Each is connected. The other terminals of the first and second resistors R1 and R2 are connected to input terminals of the first and fourth inverters, respectively. Accordingly, output signals of the first and fourth inverters transmitted to the second and fourth external input pins P2 and P4 are respectively passed through the first and second resistors R1 and R2 to the first and third external input pins. It is fed back to the first and fourth inverters through P1 and P3.

At this time, the first resistor R1 maintains the DC operating points (that is, the operating points of the input terminal and the output terminal of the first inverter) of the node A1 and the node B1 at the value Vdd / 2. The second resistor R2 maintains the DC operating points of the A2 and B2 nodes (that is, the operating points of the input terminal and the output terminal of the second inverter) at the Vdd / 2 value. To this end, the first and second resistors R1 and R2 are implemented outside the logic circuit to have a size of 1 MΩ or more, respectively.

As such, the two AC signals inputted through the A1 and A2 nodes are amplified through the first and fourth inverters, and then converted into digital signals through the second and third inverters and the fifth and sixth inverters, respectively. At this time, a capacitor may be added to adjust the minimum frequency component of the signal output through the D1 and D2 nodes.

FIG. 5 is a diagram illustrating waveforms of input signals input through the A1 and A2 nodes shown in FIG. 4, and FIG. 6 is a diagram of an output signal Det output through the RS flip-flop 2640 shown in FIG. 4. This figure shows a waveform.

3 to 6, the signal-clock conversion circuit 2620 according to the present invention receives AC signals having different phases through the A1 node and the A2 node, and outputs a digital clock signal as shown in FIG. 6. do. Each clock shown in FIG. 6 is generated when a signal exists on the twisted pair line 90. Therefore, when the count result of the number of clocks is more than a predetermined number, the signal on the twisted pair line 90 is generated. It is determined to exist. When it is determined that a signal exists on the twisted pair line 90 as described above, the data transmission / reception apparatus is automatically woken up by the clock enable signal CLK_EN generated by the wakeup apparatus 260.

7 is a flowchart illustrating a wake-up method according to a preferred embodiment of the present invention for automatically waking up a data transmission / reception apparatus by detecting the presence of a signal in a twisted pair line. Referring to FIG. 7, the wake-up method according to the present invention first determines whether a signal exists on the twisted pair line 90 (step 2621). As a result of the determination, when a signal exists on the twisted pair line 90, two signals having different phases are input from the twisted pair line 90 (step 2423). Subsequently, an AC component of the two input signals is amplified and converted into a digital form (step 2625). When the converted digital signal has a different value, a digital clock signal is generated in which 0 and 1 are alternately output. (2641 steps). The number of clocks of the clock signal generated in step 2641 is counted (step 2661), and it is determined whether the counted result has a value greater than the reference value (step 2268). As a result of the determination, when the counted result has a value larger than the reference value, the main clock is enabled to wake up the data transceiver (step 2683).

As described above, the wake-up apparatus and method according to the present invention does not require a separate CMOS analog circuit as in the prior art, and a small size signal (for example, 200 mV) existing on a twisted pair line even with a pure logic process alone. Small signal) can be accurately detected, and automatic wake-up of the data transmission / reception apparatus using the same can be performed.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the wake-up apparatus and method thereof according to the present invention can accurately detect even a small signal existing on the twisted pair line by a pure logic process without a separate circuit.

Claims (10)

In a data transmission and reception apparatus using a twisted pair line: First and second bypass capacitors for extracting an alternating current component present in two signals input from the twisted pair line; A signal converter configured to amplify the AC signals generated from the first and second bypass capacitors and convert the amplified signals into digital signals, respectively; A clock generator which generates a clock in response to the digital signals output from the signal converter; A counter for counting the number of clocks; And And a comparator for comparing the counted clock number with a predetermined reference value and generating a control signal to wake up the data transceiver when the number of clocks is greater than the reference value. . The method of claim 1, And the two signals inputted from the twisted pair line have different phases. The method of claim 1, wherein the signal conversion unit First to fourth external input pins provided outside the data transmission / reception device; A first feedback resistor having one end connected to the first external input pin and the other end connected to the first bypass capacitor and the second external input pin; A second feedback resistor having one end connected to the third external input pin and the other end connected to the second bypass capacitor and the fourth external input pin; A first inverter having an input terminal connected to the first external input pin and an output terminal connected to the second external input pin; Second and third inverters connected in series with the output terminal of the first inverter; A fourth inverter having an input terminal connected to the third external input pin and an output terminal connected to the fourth external input pin; And And a fifth and a sixth inverter connected in series with the output terminal of the fourth inverter. The method of claim 3, wherein The first inverter is a push-pull amplifier to amplify and output the AC signal input from the first bypass capacitor, The wakeup circuit of claim 1, wherein the amplification result of the first inverter is fed back to the input terminal of the first inverter through the first feedback resistor. The method of claim 3, wherein And the first feedback resistor maintains an operating point of an input terminal and an output terminal of the first inverter at a value of 1/2 of a power supply voltage. The method of claim 3, wherein The fourth inverter is a push-pull push-pull amplifier for amplifying and outputting the AC signal input from the second bypass capacitor, The amplification result of the fourth inverter is a feedback circuit, characterized in that fed back to the input terminal of the second inverter through the second feedback resistor. The method according to claim 3 or 5, And the second padback resistor maintains an operating point of an input terminal and an output terminal of the fourth inverter at a value 1/2 of the power supply voltage. The method of claim 3, wherein The first to sixth inverters each include a P-type MOS transistor and an N-type MOS transistor connected in series with a current path. The method of claim 1, And the clock generator is an RS flip-flop for outputting any one of values of 0 and 1 when the digital signals output from the signal converter have different values. In the wake-up method of a data transmission and reception device using a twisted pair line: (a) receiving two signals having different phases from the twisted pair line; (b) amplifying the alternating current components of the two signals and converting each of the amplified signals into digital form; (c) generating a clock signal in which values of 0 and 1 are alternately output when the converted digital signals have different values; (d) counting the number of clocks and comparing the counted number of clocks with a predetermined reference value; And and (e) waking up the data transmitting / receiving device when the number of clocks is greater than the reference value as a result of the comparison in step (d).