KR20030062987A - memory cell array architecture for use in low power semiconductor device - Google Patents

Abstract

PURPOSE: A memory cell array structure suitable for a low power semiconductor device is provided to secure the implementation of the low power operation, thereby being employed suitable for the high speed portable device. CONSTITUTION: A memory cell array structure suitable for a low power semiconductor device includes a first memory cell array(23) and a second memory cell array(13). In the memory cell array, the number of columns of the first memory cell array(23) is equal to that of the second memory cell array(13) and the number of rows of the first memory cell array(23) is larger than that of the second memory cell array(13). Therefore, the first size of the first memory cell array(23) becomes larger than the second size of the second memory cell array(13). And, the second memory cell array(13) having an access time being larger than the word line access time of the first memory cell array(23) is formed on the same chip.

Description

Memory cell array architecture suitable for low power semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a memory cell array structure of semiconductor memory devices having different sized arrangements.

BACKGROUND With the widespread popularity and miniaturization of electronic devices such as portable devices, large scale integrated circuits such as semiconductor memory devices employed therein are required to operate at low power. This is because a semiconductor memory device operating at lower power can extend battery life for supplying power to a portable device. In addition, the adoption of a low power semiconductor memory device can contribute to making the size of the battery relatively small, so that the overall size of the electronic device can be reduced. In particular, a large-capacity semiconductor memory device is used in applications such as video image processing and language recognition, and it is necessary to reduce power consumption of the entire system in order to reduce power consumption during access.

Techniques for reducing power consumption of memory devices by changing the arrangement of memory cell arrays in semiconductor memory devices are known in the art. 1 shows examples of arrangement of a memory cell array according to the prior art. (A) shown on the left side in FIG. 1 shows an arrangement of a typical memory cell array, in which no partition is used. Therefore, in this case, since the bit line load is large, it is known that the access time is long and the power consumption is large.

1B illustrates an example in which two memory cell array arrays are implemented by applying the same partition. Here, the two arrays, that is, the first and second memory cell arrays MAL and MAS, each have the same size. In general, since the time taken to select the word line of the MAS 21 is faster than the time taken to select the word line of the MAL 11, the access time of the MAS 21 and the access time of the MAL 11 are different. . This method is effective when the access frequency is random, but it is not very efficient in the program code that can be reassigned. In other respects, since the maximum value of the access time of the MAS 21 and the MAL 11 access time becomes the final access time, unnecessary power consumption is generated from the viewpoint of the MAS 21.

FIG. 1C illustrates an example in which two memory cell arrays are arranged by applying a biased partition. Here, the two memory cell arrays MAS 22 and MAL 12 have different sizes. This arrangement method has the advantage of greatly reducing the power consumption for the access of the MAS (2). However, since an address must be assigned to each of the MAS and MAL by access frequency prediction and address reallocation, there is a problem that it is not suitable for applications having random access frequencies.

Accordingly, it is an object of the present invention to provide a memory cell array arrangement that can reduce or minimize power consumption.

Another object of the present invention is to provide a memory cell array arrangement of a semiconductor integrated circuit which improves the performance of a semiconductor chip by improving the arrangement of the memory cell array.

A semiconductor memory cell array structure according to an aspect of the present invention for achieving the above objects includes a first memory cell array having a first size; The first memory cell array is arranged in a column direction and has the same number of columns as the number of columns of the first memory cell array, and the number of rows is large, so that the partition has a second size larger than the first size. A second memory cell array longer than the word line access time of one memory cell array is formed on the same chip.

According to another aspect of the present invention, the memory cell array is divided into two partition sizes on the left and right, and the size of the first memory cell array arranged on the left side and the size of the second memory cell array arranged on the right side are arranged differently. It is done.

1 illustrates various arrangement examples of a memory cell array according to the related art.

2 is a diagram illustrating an arrangement structure of a memory cell array according to an exemplary embodiment of the present invention.

3 is a view illustrating an arrangement structure of a memory cell array according to another exemplary embodiment of the present invention.

Hereinafter, a preferred embodiment of a low power arrangement of a semiconductor memory cell array suitable for an application in which access frequency prediction is difficult is described with reference to the accompanying drawings.

2 illustrates a layout structure of a memory cell array according to an embodiment of the present invention. Referring to the drawings, an example in which two memory cell arrays MAS 23 and MAL 13 are arranged by applying a biased partition is shown. This is the same as in FIG. 1C in that two memory cell arrays having different sizes are arranged by applying a biased partition, but the arrangement of the memory cell arrays MAS 23 and MAL 13 is illustrated in FIG. The opposite of c) is characterized. As mentioned in FIG. 1B, the lower array MAL has a longer evaluation time than the upper array MAS, that is, a time from selecting a word line to enabling the sense amplifier. It is worth noting. Accordingly, by increasing the size of the lower array MAL and decreasing the size of the upper array, it is possible to reduce power consumption and shorten the access time as a whole.

If this is expressed as a formula, it is as follows. In FIG. 2, the structure specific variables of the bottom array MAL are as follows.

Bitline Load: Cmal Evaluation Time: Tmal Voltage Swing: deltaVmal

In contrast, the structure-specific variables of the upper array (MAS) are as follows.

Bitline Load: Cmas Evaluation Time: Tmas Voltage Swing: deltaVmas

Since power consumption is proportional to the amount of charge

Lower charge consumption = leval * Tmal = Cmal * deltaVmal --- (Equation 1)

Top Consumption Charge = leval * Tmas = Cmas * deltaVmas ---- (Equation 2)

Where leval represents the current driving capability of the bit cell, that is, the memory cell. Since the voltage swings at all memory cell positions in the memory array are equal, it is normal to arrange the equations such that deltaVmal = deltavmas in Equations 1 and 2 above.

Tmal / Cmal = Tmas / Cmas ---- (Equation 3)

This formula expands to Tmal / Tmas = Cmal / Cmas, so if Tmal> Tmas, then Cmal> Cmas

It can be seen that

As such, when the arrangement of the memory cell array is divided into two top and bottom on a plane, and the lower array has an asymmetrical arrangement in which the size of the lower array is larger than that of the upper array, low power consumption is realized.

3 is a diagram illustrating an arrangement of a memory cell array according to another exemplary embodiment of the present invention. Referring to the drawings, an arrangement structure for implementing low power through an asymmetric wordline arrangement is shown. This method applies a biased partition to make a difference in the sizes of the two arrays MAS and MAL, which is the same as in FIG. However, the asymmetric word line array MAS 100 and the MAL 101 are implemented without using the asymmetric bit line array as shown in FIG. In FIG. 3, the left and right asymmetric word line arrays 100 and 101, the word line decoder 200, the asymmetric array selection switch 300 and 301, the main control circuit 400, the corresponding array column line decoders 500 and 501, the corresponding array sense amplifiers and input / output The configuration of the circuits 600 and 601 and the inter-array input / output circuit connector 700 is shown. The row decoder 200 is shared by the MAS 100 and the MAL 101, and the column decoders 500 and 501 and the sense amplifiers 600 and 601 are independently connected to the MAS 100 and the MAL 101, respectively.

Here, it is preferable to assign an address having data having a high data access frequency to the MAS 100 which is a small memory array. If the data access frequency of an address allocated to an array of a large memory cell array is high, it must be reassigned to an address of the small memory array MAS 100. In other words, memory access should be concentrated in the small memory array MAS 100. In order to implement this, first, the access frequency of the memory data is estimated and the data is rearranged accordingly.

Therefore, according to the arrangement of the memory cell array as described above, since the power consumed by the memory device during data access can be minimized or reduced, the performance of the chip can be improved.

Although the above description has been given by way of example only with reference to the accompanying drawings, it will be apparent to those skilled in the art that the present invention may be modified or changed within the scope of the technical idea of the present invention. Or change will also belong to the claims of the present invention. For example, if the matter is different, the arrangement may be changed or the component blocks of the circuit may be replaced with other equivalent elements.

According to the arrangement of the memory cell array of the present invention as described above, there is an effect of ensuring low power operation. Therefore, it can be suitably employed in a higher speed portable device.

Claims (5)

A first memory cell array having a first size; The first memory cell array is arranged in a column direction and has the same number of columns as the number of columns of the first memory cell array, and the number of rows is large, so that the partition has a second size larger than the first size. A semiconductor memory cell array structure, wherein a second memory cell array longer than the word line access time of one memory cell array is formed on the same chip. The two memory cell arrays each having a plurality of memory cells are divided into two upper and lower partitions and arranged in an asymmetrical arrangement structure such that the size of the memory cell array located in the lower partition is larger than that of the memory cell array located in the upper partition. A memory cell array structure, characterized in that. And dividing the memory cell array into two partition sizes on the left and right sides, and differently arranging the size of the first memory cell array arranged on the left side and the size of the second memory cell array arranged on the right side. 4. The memory cell array structure of claim 3, wherein the first and second memory cell arrays have respective way column decoders having the same number of rows and different numbers of columns. A semiconductor integrated circuit in which first and second memory cell arrays are divided into two partitions and are disposed on the same chip. And the first and second memory cell arrays have the same number of rows and different number of columns, and are connected to each column decoder while sharing a row decoder.