KR20030061159A - Hardware for ieee802.11 mac wep algorithm - Google Patents

Abstract

The hardware device disclosed herein implements a WEP algorithm by creating a state table with a register file to minimize the frame processing time delay caused by WEP operation. The key setup phase may be completed during a hardware cycle, and one pseudo-random number may be generated during one hardware cycle.

Description

HARDWARE FOR IEEE802.11 MAC WEP ALGORITHM

The present invention relates to hardware for the IEEE802.11 MAC Wired Equivalent Privacy (WEP) algorithm. In IEEE802.11, frame transmission / reception within a frame exchange sequence should start within a predetermined time after the transmission and reception of a previous frame. Can not be done. In particular, when receiving a frame, key setup, which is the most complicated and time consuming step in the RC4 algorithm, is started with the reception of a frame since it is performed using an initialization vector (IV) in the received frame. In order to minimize the effect of the WEP operation on the frame processing time, the hardware that executes the WEP algorithm should be fast.

Accordingly, an object of the present invention is to provide hardware capable of processing the WEP algorithm at high speed.

1 shows a WEP algorithm;

FIG. 2 shows a data processing apparatus having a register file having two data input terminals and two data output terminals to perform data swapping shown in FIG. 1 in one hardware cycle; FIG.

FIG. 3 shows a data processing apparatus having two register files capable of performing the encryption phase shown in FIG. 1 during one hardware cycle; FIG. And

4 is a diagram illustrating an algorithm for selecting one of S [i], S [j], and S [k] as a pseudo random number.

* Description of the main parts of the drawings *

11, 12, 21, 22: register file

14, 15, 23, 24: Operator

25: comparison unit

(Configuration)

According to an aspect of the present invention for achieving the above object, a register file includes: a first write address terminal that accepts a first address, a first read address terminal that accepts the first address, and the first read A first data output terminal for outputting data stored in the first address input to the address terminal, a second data input terminal for receiving data output from the first data output terminal, a second write address for receiving a second address A terminal, a second read address terminal that accepts the second address, a second data output terminal that outputs data stored at the second address input to the second read address terminal, and data output from the second data output terminal. It includes a first data input terminal for receiving a.

In a preferred embodiment, the data input to the first data input terminal is stored at the first address, and the data input to the second data input terminal is stored at the second address.

According to another feature of the invention, a pseudo-random number generator has a plurality of addresses and has a first register file and a plurality of addresses for storing data at each address and data at each address. It includes a second register file for storing the.

The first register file outputs data stored at a first write address terminal that accepts a first address, a first read address terminal that accepts the first address, and the first address input to the first read address terminal. A first data output terminal to receive data, a second data input terminal to receive data output from the first data output terminal, a second write address terminal to receive a second address, and a second read address terminal to receive the second address And a second data output terminal for outputting data stored at the second address input to the second read address terminal, and a first data input terminal for receiving data output from the second data output terminal. The second register file includes a third write address terminal for receiving the first address, a third data input terminal for receiving data output from the second data output terminal of the first register file, and the second address. A fourth write address terminal to accept, a fourth data input terminal to accept data output from the first data output terminal of the first register file, a third read address terminal to accept a third address and the third read address And a third data output terminal for outputting data stored at the second address input to the terminal. One of the data output from the first to third data output terminals is output as a pseudo-random number.

(Example)

The RC4 algorithm uses a state table to generate pseudo-random numbers for data encryption / decryption. When initializing this state table and generating pseudo-random numbers, swapping the values of the state table takes place. When a state table is implemented using a register file, data is generated during one hardware cycle. The swapping can be completed, thereby minimizing the frame processing time delay caused by the WEP operation.

1 shows a WEP algorithm. Referring to FIG. 1, the Wired Equivalent Privacy (WEP), or RC4, algorithm uses a key setup phase and a key setup phase to initialize a register file using a secret key or key array. Can be divided into ciphering phases to generate pseudo-random numbers.

First, the key setup phase consists of a first process of initializing a register file (ⓛ) and a second process of mixing a register file 256 times using a security key (②). Since the first process (ⓛ) can be performed independently of the security key, the key setup time can be reduced by performing the process immediately after transmission and reception of the frame. The second process (②) reads S [i] and S [j] from the register file using a security key and repeats the operation 256 times. In this case, when a state table is implemented using a register file having two data input terminals and two data output terminals, data swapping may be performed in one hardware cycle.

FIG. 2 shows a data processing apparatus having a register file having two data input terminals and two data output terminals to perform data swapping shown in FIG. 1 in one hardware cycle. Referring to FIG. 2, the data processing apparatus includes register files 11 and 12, a security key register 13, and operators 14 and 15.

The register file 11 includes a first write address terminal W1ADDR, a first data input terminal W1DATA, a second write address terminal W2ADDR, a second data input terminal W2DATA, and a first read address terminal R1ADDR. The first data output terminal R1DATA, the second read address terminal R2ADDR, and the second data output terminal R2DATA are included.

In the key setup phase shown in FIG. 1, i increases from 0 to 255, and one data swapping for each i is performed in the following order.

(1-1) Input the address i to the first write address terminal W1ADDR and the first read address terminal R1ADDR.

(1-2) Input of output data S [i] of first data output terminal R1DATA to second data input terminal W2DATA

(1-3) Input address j to second write address terminal W2ADDR and second read address terminal R2ADDR

(1-4) Input of output data S [j] of second data output terminal R2DATA to second data input terminal W2DATA

(1-5) Write data input to the first and second data input terminals W2DATA and W2DATA

Steps (1-1) to (1-5) as described above are performed during one hardware cycle.

FIG. 3 shows a data processing apparatus having two register files to perform the encryption phase shown in FIG. 1 in one hardware cycle. Referring to FIG. 3, the data processing apparatus includes register files 21 and 22, operators 23 and 24, and a comparator 25.

The register file 21 includes a first write address terminal W1ADDR, a first data input terminal W1DATA, a second write address terminal W2ADDR, a second data input terminal W2DATA, and a first read address terminal R1ADDR. The first data output terminal R1DATA, the second read address terminal R2ADDR, and the second data output terminal R2DATA are included. The register file 22 includes a third write address terminal W3ADDR, a third data input terminal W3DATA, a fourth write address terminal W4ADDR, a fourth data input terminal W4DATA, and a third read address terminal R3ADDR. And a third data output terminal R3DATA.

In the encryption phase, swapping of the register file occurs once each time 1 byte encryption / decryption is performed as described above (③). The formulas for indexing register files used for swapping vary, but the flow is consistent with the swapping method in the key setup phase. In addition, there is a process of reading a pseudo-random number from a register file after swapping, which requires another read operation. This can be done in one hardware cycle through mirroring the register file. The register file 22 performs the same write operation performed on the register file 21 to operate as a copy for storing the same data as the register file 21. By keeping S and S 'the same, pseudo-random numbers can be generated during one hardware cycle.

The following steps (2-1) to (2-7) summarize the operation procedure of the encryption phase.

(1) Input the address i to the first write address terminal W1ADDR and the first read address terminal R1ADDR.

(2) Input output data S [i] of the first data output terminal R1DATA to the second data input terminal W2DATA.

(3) Input address j to the second write address terminal W2ADDR and the second read address terminal R2ADDR.

(4) Input the output data S [j] of the second data output terminal R2DATA to the second data input terminal W2DATA.

(5) Input address k to third read address terminal R3ADDR

(6) Data S [k] is output to the third data output terminal R3DATA.

(7) Write data input to the first and second data input terminals W2DATA and W2DATA

Since S [k] is read before swapping in the above-described process, the pseudo-random number may be S [i] or S [j] rather than S [k]. To do this, we need to determine the pseudo-random number using i, j, and k.

(8) select one of S [i], S [j], and S [k] as a pseudo random number in consideration of i, j, and k

An algorithm for performing step (8) is shown in FIG.

As described above, 256 hardware cycles after the secret key is determined by implementing a WEP algorithm by creating a state table with a register file to minimize the frame processing time delay caused by the WEP operation. You can complete the key setup phase and generate one pseudo-random number in one hardware cycle.

According to the present invention as described above, the key setup phase can be completed for 256 hardware cycles after the security key is determined, and one pseudo-random number can be generated for one hardware cycle.

Claims (8)

In a register file: A first write address terminal receiving a first address; A first read address terminal to accept the first address; A first data output terminal configured to output data stored at the first address inputted to the first read address terminal; A second data input terminal for receiving data output from the first data output terminal; A second write address terminal that accepts a second address; A second read address terminal that accepts the second address; A second data output terminal configured to output data stored at the second address inputted to the second read address terminal; And And a first data input terminal for receiving data output from said second data output terminal. The method of claim 1, And the data input to the first data input terminal is stored at the first address. The method of claim 1, And the data input to the second data input terminal is stored at the second address. For pseudo-random number generators: A first register file having a plurality of addresses and storing data at each address; And A second register file having a plurality of addresses, the second register file storing data at each address; The first register file, A first write address terminal receiving a first address; A first read address terminal to accept the first address; A first data output terminal configured to output data stored at the first address inputted to the first read address terminal; A second data input terminal for receiving data output from the first data output terminal; A second write address terminal that accepts a second address; A second read address terminal that accepts the second address; A second data output terminal configured to output data stored at the second address inputted to the second read address terminal; And A first data input terminal for receiving data output from the second data output terminal; The second register file, A third write address terminal that accepts the first address; A third data input terminal for receiving data output from the second data output terminal of the first register file; A fourth write address terminal that accepts the second address; A fourth data input terminal for receiving data output from the first data output terminal of the first register file; A third read address terminal that accepts a third address; And A third data output terminal configured to output data stored at the second address inputted to the third read address terminal; Pseudo-random number generator, characterized in that one of the data output from the first to third data output terminals is output as a pseudo-random number. The method of claim 4, wherein And said data inputted to said first data input terminal of said first register file is stored at said first address. The method of claim 4, wherein And the data inputted to the second data input terminal of the first register file is stored at the second address. The method of claim 4, wherein And the data input to the third data input terminal of the second register file is stored at the first address. The method of claim 4, wherein And the data inputted to the fourth data input terminal of the second register file is stored at the second address.