KR20030060529A - System And Control Method Of Recording and Reproducing Compressed Music Files - Google Patents

Abstract

PURPOSE: A device and a method for recording/reproducing compressed music files and a method for controlling the same are provided to employ the extended serial peripheral interface for realizing the control in connection with various external devices simply. CONSTITUTION: A device for recording/reproducing compressed music files includes a 9-pin connector for the connection with external devices and a micro-control unit(MCU;102), a recording unit for recording compressed music files and information thereon, a reproducing unit for reproducing the compressed music files, an incorporated Li-Polymer battery(107), a display unit and a key input part(111). The MCU is connected to the 9-pin connector via device control signal lines(CS) for device control signals to control the devices, device state display signal lines(BUSY) for signals displaying the ready state of the devices, data clock signal lines(CLK) for data clock signals to control the clocks of received or transmitted data, and data signal lines for bidirectional data.

Description

System and Control Method of Recording and Reproducing Compressed Music Files}

The present invention relates to a music compressed file storage / playback apparatus, and more particularly, to a music compressed file storage / playback apparatus capable of storing and playing back a music compressed file by employing an extended serial peripheral interface (Extended Serial Peripheral Interface). It is about a method.

Recently, with the development of multimedia technology, software players have been developed that can play MP3 (MPEG1 Layer 3) music compressed files as digital files through a computer. MP3 can compress data as much as 50 times that of general compact discs while maintaining sound quality close to compact discs. Therefore, the MP3 system can be used as a hardware player as demand for MP3 music increases. MP3 players have been developed as personal portable devices.

The MP3 player manages MP3 music in the form of a file in a memory, which is a storage medium, and has a control unit for controlling internal operations. In addition, the MP3 player has a serial port or parallel port and has a function of communicating with each other via a serial cable or a parallel cable as a source of MP3 music data, for example, to download MP3 music data from a computer.

The music compressed file storage / playback apparatus has such a problem that the music compressed file storage / playback apparatus has a problem such as lack of compatibility due to the difference between complicated transmission methods and different transmission methods in data transmission, and other external devices. Since the interface with them is fixed, it is difficult to apply and apply various devices. In addition, copyright issues such as illegal sound source copying due to random detachment and copying of memory have been raised.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and by applying an extended synchronous serial communication method, a music compressed file storage / playback device and control which makes it possible to control various external devices more easily than the conventional method. The main purpose is to provide a method.

Another object of the present invention is to provide an apparatus and a control method of a music compressed file storage / playback in an extended synchronous serial communication method having a low-cost, high-speed data writing structure.

Another object of the present invention is to provide an apparatus and a control method for storing / reproducing music compressed files of an extended synchronous serial communication method using two internal memories to optimally use the memory without fragments.

Another object of the present invention is to provide an apparatus and a control method for storing / reproducing music compressed files of an extended synchronous serial communication method, which improves security of data by preventing physical separation between the memory and the components.

Another object of the present invention is to configure the file type for optimizing the performance of the control unit (MCU) to save / play music compressed files of the extended synchronous serial communication method that can reduce the production cost and the number of parts during production An object of the present invention is to provide an apparatus and a control method.

In order to achieve the above object, a music compressed file storage / playback apparatus according to a preferred embodiment of the present invention includes: connection means for connection with the external device; Storage means for storing the music compressed file and its information; Reproducing means for reproducing the stored music compressed file; A device control signal line through which a device control signal for controlling the device flows; Device ready display signal line through which device ready status indication signal flows to indicate that the device is ready to operate, data clock signal line through which data clock signal flows to clock data transmitted and received, and data signal line flowing data in both directions Is connected to the connecting means through, and comprises a control means for controlling the storage and playback of the music compressed file.

In order to achieve the above object, a data input / output control method for recording and reproducing a music compressed file in a music compressed file storage / playback apparatus according to a preferred embodiment of the present invention includes a device control signal for controlling the device. A device control signal line, a device ready state display signal line through which a device ready state indication signal flows to indicate that the device is ready for operation, a data clock signal line through which a data clock signal for clocking data to be transmitted and received flows, and bidirectional; A music compressed file storage / reproducing apparatus, comprising: a data signal line having data flowing therethrough, for transferring data with an external device, downloading and storing a digital music compressed file from the external device, and reproducing the stored music compressed file; Detecting a low level switching of the device control signal line; A second step of bringing the device ready state indication signal line to a low level during a one-byte clock period upon detecting a low level transition in the first step; A third step of performing input / output of data through the data signal line when the data clock signal line advances to a low level state; A fourth step of confirming switching of the device ready status indication signal line to a high level; A fifth step of confirming the high level switch of the device control signal line when the high level switch is confirmed in the fourth step; A sixth step of repeating the second to fifth steps when the switching of the high level is not confirmed in the fifth step; If the switching of the high level is confirmed in the fifth step, the step of ending the input and output of data through the data signal line.

1 is a block diagram of an overall configuration of a music compressed file storage / playback apparatus according to the present invention;

2 is a view for explaining an external connection in the music compressed file storage / playback apparatus according to the present invention;

3 is a block diagram showing the configuration of a control device in a music compressed file storage / playback apparatus according to the present invention;

4 is a view for explaining a memory addressing method in a music compressed file storage / playback apparatus according to the present invention;

5 and 6 are signal timing diagrams of an extended synchronous serial transmission method in a music compressed file storage / playback apparatus according to the present invention;

7 is a system flowchart of extended synchronous serial transmission in a music compressed file storage / playback apparatus according to the present invention;

8 is a detailed flowchart of the serial data reading step A of FIG.

9 is a detailed flowchart of the serial data writing step (B) of FIG. 7;

10 to 16 is a view for explaining the memory structure and operation in the music compressed file storage / playback apparatus according to the present invention,

17 to 21 are flowcharts illustrating a system operation in a music compressed file storage / playback apparatus according to the present invention.

※ Explanation of code for main part of drawing

102: control unit 103,104: NAND flash memory

105: decoder 106: digital / analog converter

107: battery 108: liquid crystal display driver

109: liquid crystal display 110: information storage unit

111: key input unit

Hereinafter, a music compression file storage / playback apparatus and a control method according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, the overall system configuration of the music compressed file storage / playback apparatus according to the present invention will be described with reference to Figs.

1 is a block diagram of an overall configuration of a music compressed file storage / playback apparatus according to the present invention. The music compressed file storage / playback apparatus of the present invention comprises a 9-pin connector, a control unit 102, a storage unit, a playback unit, a built-in lithium polymer (Li-Polymer) battery 107, a display unit, and a key input unit 111. It is composed.

The 9-pin connector has an extended synchronous serial transmission communication line 100 (CS, BUSY, CLK, DIO), a power signal line (PWR), a battery signal line (BAT), two audio output lines (Audio output (R), Audio output (L)] and ground line (GND). The extended synchronous serial transmission communication line 100 includes a device control signal line CS, a device ready state display signal line BUSY, a data clock signal line CLK, and a bidirectional data signal line DIO.

The control unit (Micro Control Unit (MCU)) 102 is responsible for the overall control of the device, and is connected to the 9-pin connector through the expansion synchronous serial transmission communication line 100. The storage unit is composed of two NAND type flash memories 103 and 104 in which a music compressed file is stored, and an information storage unit (E2PROM) 110 for storing state and song information of the system.

The playback unit includes an MP3 (MEPG1 Layer 3) decoder 105 for decoding the music compressed file stored in the memory 103 and 104 under the control of the control unit 102, and the MP3 decoder 105. And digital to analog converter (DAC) 106 for converting the converted music digital data into analog data and outputting the same.

The display unit includes a liquid crystal display (LCD) 109 and a drive driver 108 for driving the liquid crystal display 109 according to the control of the control unit 102.

As shown in FIG. 2, the 9-pin integrated connector has a battery signal line BAT connected to the audio signal lines Audio R and Audio L of the stereo output audio R and L and the battery 107 from the digital / analog converter 106. , A power signal line (PWR) connected to a low drop regulator (LDO) 300 that supplies power to the entire system, and signal lines connected to an interface (MCU Interface) 301 of a control unit (MCU) 102 ( It is responsible for connecting BUSY, DIO, CLK, CS) with external devices. The signal lines BUSY, DIO, CLK, and CS are implemented by an extended synchronous serial transmission scheme. The battery signal line BAT and the power signal line PWR are connected to form a structure for supplying power to the system.

Next, a control device which is a system operation essential part of the compressed file storage / reproducing apparatus according to the present invention will be described with reference to FIG.

The control unit (MCU) 102 of the apparatus includes a synchronous serial transmission control apparatus 200 implemented in a software manner and a serial transmission control apparatus 201 configured in hardware. The apparatus 200, 201 is directly connected by the signal line CLK (DIO), and serial transmission is possible through the signal line CLK (DIO). The system busy control unit 202 outputs a ready state of the system through the signal line BUSY. The ISR initialization control unit 204 is configured as an interrupt service routine (ISR) unit, and when the signal line CS is changed to a low level state, the ISR initialization control unit 204 serves to operate the serial transmission device through the control units 200, 201, and 202. . The decoder DAC interface control unit 203 controls the decoder 105 through a DAC (digital / analog converter) control signal D_READY and a mute signal line. The DAC control signal D_READY is decoded by the decoder 105. The signal requesting data, and the MUTE signal line serves to cut off the output from the DAC 106. The control unit 102 of the device decrypts data coming from the software serial transmission device 200 via the command decoder 205. According to this decryption, the data buffer 207, the memory addressing control unit 206, and the I2C interface control unit 209 performing I2C communication can be controlled. The control unit of the apparatus also includes an internal control system 207 and an LCD drive interface 208.

Next, a memory address designation in the compressed file storage / playback apparatus according to the present invention will be described with reference to FIG.

The device can contain up to two NAND-type flash memories. In the NAND flash memory, the page variable 300 constitutes one page with an offset of 0 to 527, and 32 pages constitute one block 301. In this configuration, if two bytes are used as the page variable 300, the maximum possible page 300 is 65536 * 528 = 34603008Byte. Therefore, NAND flash memory of 32 Mbytes or more cannot be represented with only the page variable 300 of 2 bytes. The block variable 301 of 2 bytes can specify 1107279360Byte. The lower address 302 of 0 ~ 34603008Byte is designated as the page variable 300 through the relationship of page = block * 32, and the upper address 303 of the remaining 34603008Byte ~ 1107279360Byte is designated through the block variable 301. This method can assign a logical address of up to 1107279360Byte size by only 2Byte variable operation, and logically designate large memory to low-cost 8Bit MCU where 4Byte operation is impossible.

Accordingly, the apparatus designates 32 Mbytes as each page index and logically up to 1.1 Gbytes as the block index, so that two memories may each use 550 Mbytes of memory.

Next, the extended synchronous serial transmission method of the compressed file storage / playback apparatus according to the present invention will be described with reference to FIGS.

The extended serial transmission method applied to this apparatus is composed of a device control signal line CS, a device ready state display signal line BUSY, a transmit and receive data clock signal line CLK, and a bidirectional data signal line DIO as shown in FIG. do. When the device control signal line CS proceeds to a low level state at T100, the device brings the device ready state signal line BUSY to a low level state at T101 by the controller 102 (MCU). When the data clock signal line CLK proceeds to the low level state at T102, the most significant bit (MSB) data of the corresponding data is output at T104 at the point of time T103 through the bidirectional data signal line DIO. Or enter The order of T105 to T106 is input / output sequentially from the most significant bit (MSB) of the 1 byte data to the least significant bit (Least Significant Bit). After all data is output, the data clock signal line CLK proceeds to the high level state at the time T107 and is designated as the low active state. BUSY goes to the high level and stops further data input. If the device control signal line CS is at the high level at time T109, further data transmission and reception are stopped.

As a basic 1 byte transmission and reception method, as shown in FIG. 6, when the device ready state signal line CS is at a low level, a series of data transmission and reception proceeds. T201 is the first 1 byte data received by the device as basic command data. After the data is interpreted by the command decoder 205 (see FIG. 3), data transmission and reception is performed from T202 according to the command. Data transmission and reception is completed at the point T203, and if each byte is the low-level device ready status indication signal line BUSY in the transmission interval, the next byte is transmitted and received.

The system flow of the extended synchronous serial transmission in the apparatus according to the present invention will be described with reference to FIG. First, when the low level change of the device control signal line CS is detected, the control unit 102 makes the device ready state display signal line BUSY low level in step S200. The control unit 102 reads data from the transmit and receive data clock signal line CLK and the bidirectional data signal line DIO in step S201, and then sets the device ready state display signal line BUSY to high level in step S202. The control unit 102 determines whether the read data is an instruction in step S203, and decodes the instruction in step S204. In step S205, it is determined whether the next data is required by the method defined according to the instruction. The control unit 102 decides to write and read data in step S206, and if it is selected to read data, makes the device ready status indication signal line BUSY low in step S207 and then bidirectionally with the transmit and receive data clock signal lines CLK. Data is received from the data signal line DIO, and then the device ready state display signal line BUSY is made high, and then in step S210 a read / write of the next data is determined. If the next data is written in step S206, the control unit 102 makes the device ready state display signal line BUSY low, and then in step S212, the transmit and receive data clock signal lines CLK and the bidirectional data signal lines DIO are used. Then, data writing is executed, and when this execution is completed, the device ready state display signal line BUSY is made high in step S123. Next, the control unit 102 determines whether further read and write states are necessary in step S214, and then repeatedly performs step S204. In the above-described steps S210 and S214, the control unit 102 determines whether the device control signal line CS is at a low level, and if the device control signal line CS is at a high level, it means that there is no further data transmission or reception.

The serial data read in step S201 (A) of FIG. 7 is performed by the flow as shown in FIG. First, the control unit 102 initializes the data and count variables in step SA100, makes the device ready status indication signal line BUSY low in step SA101, and then in step SA102 whether the device control signal line CS is low level. Judge. If the device control signal line CS is at the high level, further reception is stopped, and the flow proceeds to step S202 to make the device ready state display signal line BUSY high, and then the serial data reading is finished.

If the device control signal line CS is at the low level in step SA102, the control unit 102 determines whether the transmit and receive data clock signal line CLK is at the low level in step SA103. If the data clock signal line CLK is high level, the process proceeds to step S202. If the data clock signal line CLK is high level, the process goes to step SA104 to read data from the bidirectional data signal line DIO and reads the bit of the bidirectional data signal line DIO. . Then, the control unit 102 determines whether the bit of the bidirectional data signal line DIO is high level or low level in step SA105, and if it is low level, the control unit 102 moves to step SA107 to zero the least significant bit (LSB bit) of the data variable. If it is a high level, the process moves to step SA106 to make the least significant bit of the data variable one. In step SA108 the control unit 102 moves the bits of the data variable to the left and adds 1 to the count variable. The control unit 102 then determines in step S109 whether the count variable is 8, if less than 8, moves to step SA101 and receives the next bit data. If the count variable is 8, the device ready state display signal line BUSY is made high and then the process proceeds to the next step S203.

Writing of serial data in step S212 (B) of FIG. 7 is performed by the flow as shown in FIG. First, the control unit 102 initializes the count variable to zero in step SB100, and makes the device ready status indication signal line BUSY low in step SB101. In step SB102, the control unit 102 checks whether the device control signal line CS is at a low level. If it is high level, the control unit 102 proceeds to step S213 to make the device ready status indication signal line BUSY high and to proceed to the next step S214. do. If the device control signal line CS is at low level in step SB102, the control unit 102 moves to step SB103 to bring the transmit and receive data clock signal line CLK to low level. Subsequently, in operation SB104, the operation data value 1 and the logic value 1 are calculated using AND logic, and if the operation value is 1, the process moves to step SB105 to bring the bidirectional data signal line DIO to a high level. If zero, the process moves to step SB106 to bring the bidirectional data signal line DIO to a low level. Subsequently, the control unit 102 moves each bit Bit of the data value to the right in step SB107, and adds 1 to the count variable. Thereafter, the control unit 102 sets the data clock signal line CLK to high level in step New 108 and checks whether the count variable is 8 in step New 109. If the count variable in step SB109 is not 8, the control unit 102 moves to step SB101 described above and outputs the next bit. If the count variable is 8, the control unit 102 proceeds to step S213 to make the device ready status indication signal line BUSY high, and then to step S214.

Next, a memory format structure and operation of the compressed file storage / reproducing apparatus according to the present invention will be described with reference to FIGS. 10 to 16.

Referring to FIG. 10, the total memory size L100 in the memory structure of the apparatus is divided into blocks, and the block address L101 records the header of the music file from the top to the bottom of the memory structure. Data consecutive from the block address L103 is constructed. The offset (maximum block-current block) of each header block is stored in the information storage unit 110 (E2PROM). The offset of the music file at the position of the information storage unit 110 of L104 is stored after the address of the 256 information storage unit E2PROM. The L100 can allocate up to the maximum size of two NAND-type flash memories. L102 is a block memory fragment created after file deletion.

Referring to Fig. 11, one logical file starts from block L200 obtained from an offset stored by information storage unit E2PROM L201. Each block stores the location of the next block on page 0 after the data is written. Therefore, the block of L200 stores the position of the L202 block, L202 stores the block position of L103, and L103 stores the last block L104 of the file. The last block L104 marks the end of file. This technique is a structure in which arbitrary random data can be written without using specific positional data.

Referring to FIG. 12, each block is composed of 16896 bytes, a block is composed of 32 pages, and 528 bytes constitutes one page. Therefore, TA102, where the page of each block TA101 is 0, allocates space as much as TA100 = 528Byte to record the characteristics of the block.

Referring to FIG. 13, the header information page TA200 records each information as follows. Each TA201 and TA202 allocates 1 byte, and indicates whether the block is a bad block or a normal block with data loss in a NAND flash memory. TA203 is used as a mark to determine whether data is a written block and allocates 1 byte. TA204 indicates whether the current block is a block including a header starting from a sound source (using one page of the current block) or a block in which only data is recorded. TA205 indicates whether the current block written is a music header block or a continuous data block, and allocates 1 byte. TA206 and TA207 allocate 1 byte each, and use both to indicate the block number of the next connecting block of 2 bytes. Since 2 bytes are allocated, up to 1.1 Gbytes of memory can be connected. TA207 indicates that the file is ending. The remaining data TA208 is a dummy code.

Referring to FIG. 14, the music file header block is allocated by the size of one page TA300 after the block display page of the TA303. Therefore, page 0 exists in both the header block and the data block, but the header information of TA302 exists only in the header block.

The header page TA303 is allocated as follows. Referring to FIG. 15, the TA400 may allocate an arbitrary value as a dummy code and allocate 1 byte. The TA401 and TA402 display the number of blocks used by the music file in 2 bytes. TA403 allocates 1 byte, displays the number of equalizer used, and allocates 1 byte. TA404 indicates the type of music, prohibits the performance of music, and allocates 1 byte. The TA405, TA406, and TA407 allocate 3-band equalizers and allocate 3 bytes. TA408 records the actual size of the current file and allocates 4 bytes. TA409 displays the file name of the current file and allocates 150 bytes. TA410 indicates the file recording time and allocates 14 bytes. TA411 stores music file information (MPEG Header) and allocates 26 bytes. TA412 displays guitar music information.

Referring to FIG. 16, a structure TA500 of an information storage unit 110 (E2PROM) for storing music header information storage and system information and user information is as follows. TA501 displays the status of system initialization and allocates 1 byte. The TA502 records the volume information of the music currently playing and uses 1 byte. TA503 enables read and write by user information and user. TA504 indicates the offset (total block-header block position) of the header of the music file. The TA505 allocates 256 bytes, and the TA506 uses a size obtained by subtracting 256 bytes from the size of the information storage unit 110 (E2PROM). The structure of the TA505 consists of a series of memories allocated for each byte of TA506. The TA506 stores the header offset of the first music. Music number 2 is stored in the memory location after TA505. The block offset stores a value obtained by subtracting the position TA509 of the current header from the upper memory TA508 of the NAND flash memory TA507. That is, Offset = TA508-TA509.

Next, a system operation flow of the compressed file storage / playback apparatus according to the present invention will be described with reference to FIGS. 17 to 21.

Music file performance in the compressed file storage / playback apparatus according to the present invention is implemented in the flow as shown in FIG.

First, in step S101 the control unit 102 reads the music header information for the music file to be played, and in step S102 the number of blocks used by the music file is read. Thereafter, the control unit 102 determines whether to stop the current performance for the next performance by an external key or the like in step S103. If the control unit 102 stops, the control unit 102 moves to step S111 after confirming the number of music to be played. If there is no play interruption in step S103, the process moves to step S104 to read page 0 of the block and read the address of the next linked block. Thereafter, in step S105, it is determined whether the current block has an End of File (EOF) mark. If there is an EOF mark, the flow moves to step S112 to confirm the music number to be played, and then the flow goes to step S101. If there is no EOF mark in the current block, the flow advances to step S106 to calculate the actual page by multiplying the current block by 32 to specify the current address. Then, the count variable is initialized to 0. Then, in step S107, after setting the address based on the page variable, 1 byte data is read from the NAND type flash memory from step S108. In step S109, the signal line D_READY of the decoder 105 is inspected, and in step S110 it is determined whether there is a data request D_REQ, and if there is no data request, the flow moves to step S109. If there is a request for data in step S110, the process moves to step S112 and 1 byte is transmitted to the decoder 105. After the transfer, go to step S113 to add 1 to the count variable, and determine whether the count is 528 in step S114. If the count value is 528, go to step S115 and add 1 to the Page variable, Otherwise go to step S116. In step S116, it is determined whether to stop playing, and if there is a stop request, the flow advances to step S101.

If it is determined in step S116 that there is no interruption request, the flow proceeds to step S117 by dividing the current page variable by 32 and moving to step S108 if the remainder is not 0, and moving to step S118 if the remaining block is 0, and then connecting blocks. Is set to the current block, and the flow proceeds to step S103. This flow provides a function of automatically delivering the music file to the decoder 105 in accordance with the connected block.

Next, in the compressed file storage / playback apparatus according to the present invention, the flow of data writing by the extended synchronous serial transmission method is shown in FIG.

First, after reading the serial data in step S300, it is determined in step S301 whether this command is a data write, and if this command is a data write, it moves to step S302 to divide the page by 32 to determine whether the remainder is zero. To judge. If it is determined in step S302 that it is not 0, the process moves to step S310. If it is determined in step S302 that it is 0, the process moves to step S303 to read the next unused block position from the current block position. Then, after setting the page variable from the current block address in step S304, the current address is set in step S305. Next, in step S306, the address of the next unused block is designated as the current block address. Next, in step S307, it is determined whether the current block is a music header or a data block. If it is a header block, go to step S308 to record the header format on page 0 of the block, and if it is a data block, go to step S309. Record the data format on page 0 of the page.

Subsequently, the iPage variable is initialized to 0 in step 310, and the current page address is set in step S311. After the device ready state display signal line BUSY is made low in step S311, serial data is read in step S312. The data variable Data read in step S315 is written to the NAND flash memory buffer, and in step S316, 1 is added to the iPage variable. In step S317, it is determined whether the i page is 528, and if not, it moves to step S312.

If it is determined in step S317 that it is not 528, the flow advances to step S318 to determine whether the device control signal line CS is at a low level. If the device control signal line CS is at a high level, the flow goes to step S321 and EOF ( End of File) and finish writing. If it is determined in step S318 that the device control signal line CS is at a low level, the process moves to step S319 to perform a page write of data currently in the buffer. In step S320, 1 is added to the page variable, and the flow advances to step S302. Through such a series of operations, music files are written in an extended synchronous serial transmission method so that file writing is automatically performed according to a prescribed format.

Next, in the compressed file storage / playback apparatus according to the present invention, a space allocation technique for allocating a storage space by determining whether data to be stored is a music header or data is performed by the flow of FIG.

First, it is determined whether the block not used in step SC100 is a block for writing a music header or a block for writing data. If the block to be written is a data block, the process moves to step SC101, where the current page is obtained by multiplying the position of the current block by 32, and in step SC102, an address is set on a page basis. In step SC103, it is determined whether the current block is a valid data block. If the current block is not a valid data block, the process moves to step SC106, adds 1 to the block variable, and then moves to step S101.

If it is determined in step SC103 that the current block is a valid block, it is determined in step SC104 whether the current block is an unused block. If it is determined that the block used in step SC104 is moved to step SC105, it is determined whether the total number of blocks t blocks (Block) variable is equal to the current block. If it is determined to be the same in step SC105, it is determined that there are no more writeable blocks, and the process moves to step SC107 to indicate that there is no write memory. If it is determined that it is not the same in step SC105, the process proceeds to step SC106, where 1 is added to the current number of blocks, and then the process goes to step SC101.

If it is determined in step 104 that the block is not used, the process moves to step SC115, the current block is designated as a writable block, and the data header is writable.

On the other hand, if the block to be written in the above step SC100 is a header block, go to step SC108 to set the current block number variable (Block) to the total block number variable t block (Block), and to the position of the current block in step SC109 Multiply by 32 and set the result to the current Page variable. Thereafter, in step SC110, the address is set based on the page. In step SC111, it is determined whether the current block is a valid block. If it is not a valid block, the process moves to step SC114, subtracts 1 from the block variable, and then moves to step S109.

If the current block is determined to be a valid block in step SC111, it is determined whether the current block is an unused block in step SC112. If it is determined that the block used in step SC112 is determined to go to step SC113, it is determined whether the block variable is 0. If it is determined that the block variable is 0, it is determined that there are no more writeable blocks. Indicates none. If it is determined in step SC113 that the block is not 0, step 1 is performed after subtracting 1 from the block variable in step SC114.

If it is determined that the block is not used in step 112, the process moves to step SC115, the current block is designated as a writable block, and the header is writable.

As described above, in the flow of FIG. 19, data can be written from a lower block, and a header can be written from an upper block.

The device of the present invention makes it possible to use two physical NAND flash memories in succession. For this structure, the control unit 102 may use two chips using a virtual memory address as shown in the flow of FIG. 20.

That is, in step S600, the first NAND flash memory chip is turned on and the block size of the logical block number vBlock and the first NAND flash memory are compared in step S601. If the variable of vBlock is smaller than tBlock1, go to step S607 and the current physical page variable is obtained by multiplying this block value by 32. In step S608 the current address is specified and the flow ends. However, if the vBlock variable is larger than the tBlock variable, the second NAND flash memory is selected in step S602, and in step S603 the tBlock1 is subtracted from the current logical block number vBlock and the result is set to the relative block rBlock. In step S605, the relative block rBlock is multiplied by 32 to set the current page, and in step S606 this address is set.

Next, the operation of deleting a music file in the compressed file storage / playback apparatus according to the present invention will be described with reference to FIG.

The deletion of the music file reads the music file information for the music file number iHeader to be deleted in step S701. In step S702, the total number of blocks used by the music file is read. In step S703, the number of blocks of the next block associated with this block is read. In step S703, a value obtained by multiplying the current number of blocks by 32 is set as a page value, and in step S705, an address is set. Thereafter, the current block is deleted in step S706, and it is checked in step S707 whether the current block has an indication of End of File (EOF). If there is no indication, the next block connected in step S708 is substituted into the current block, and in step S709 it is determined whether there is a NAND type flash memory error, and if there is an error, block headers TA200 and TA201 cannot be written further from step S710. A bad BAD block is displayed, and the flow advances to step S703. If there is no error, go to step S703.

If there is an indication of End of File (EOF) in step S707, it means that all blocks of the current music file have been deleted, and the flow moves to step S711. In step S711, the address variable Addr of the information storage unit 110 (E2PROM) is assigned to the current music file number, and in step S712, 1 is added to the Addr variable. Then, the value is read into the music header position data variable data in step S713 and 1 is subtracted from the address variable Addr in step S714. Subsequently, in step S715, the data variable Date is recorded in the address value, and after going to step S716, 1 is added to the address variable Addr of the information storage unit 110 (E2PROM). Then, if the value of Data read in step S717 is the maximum value (the maximum value is 255 if the offset of the block is 255), the deletion flow ends.

On the other hand, the present invention is not limited only to the above-described embodiment, but can be modified and modified within the scope not departing from the gist of the present invention, the technical idea to which such modifications and variations are also applied to the claims Must see

As described in detail above, according to the present invention, the extended synchronous serial communication method is applied to enable the control with various external devices more easily than the conventional method. It has a low-cost, high-speed data write structure, and uses two internal memories to optimally use the memory without fragments. It is possible to improve the security of the data by not physically separating the memory and each component, and to form a file type for optimizing the performance of the control unit, and to reduce the production cost and the number of parts in the production. There is.

Claims (17)

A music compressed file storage / playback apparatus for downloading and storing a digital music compressed file from an external device and playing the stored music compressed file, The device control signal line through which the device control signal for controlling the device flows, the device ready state display signal line through which the device readiness indication signal flows to indicate that the device is ready for operation, and the data for clocking data transmitted and received. And a data clock signal line through which a clock signal flows, and a data signal line through which data flows in both directions, wherein data transmission / reception with the external device is performed. The method of claim 1, And the data is transmitted using a synchronous serial transmission method. A music compressed file storage / playback apparatus for downloading and storing a digital music compressed file from an external device and playing the stored music compressed file, Connecting means for connecting to the external device; Storage means for storing the music compressed file and its information; Reproducing means for reproducing the stored music compressed file; The device control signal line through which the device control signal for controlling the device flows, the device ready state display signal line through which the device readiness indication signal flows to indicate that the device is ready for operation, and the data for clocking data transmitted and received. And a control means connected to said connection means via a data clock signal line through which a clock signal flows and a data signal line flowing in both directions, and controlling means for controlling the storage and reproduction of the music compressed file. Device. The method of claim 3, wherein Further comprises a battery, The connecting means includes the device control signal line, the device ready state display signal line, a data clock signal line and a data signal line, a power signal line for supplying power, a battery signal line for supplying battery power from the battery, and two audios. And a 9-pin connector for connecting an output line and a ground line to the external device. The method of claim 3, wherein And the storage means comprises at least one NAND flash memory for storing the compressed music file, and an information storage for storing state and song information of the device. The method of claim 3, wherein The reproducing means comprises a decoder for decoding a music compressed file stored in the storage means under control of the control means, and a digital / analog converter for converting the digital music data decoded by the decoder into analog data and outputting the analog data. Music compressed file storage / playback device. The method according to any one of claims 1 to 6, The music compressed file storage and playback device, characterized in that the MPEG1 Layer 3 form. A music compressed file storage / playback apparatus for downloading and storing a digital music compressed file from an external device and playing the stored music compressed file, Connecting means for connecting to the external device; At least two NAND flash memories for storing the music compressed file; Reproducing means for reproducing the stored music compressed file; It comprises a control means for controlling the storage and playback of the music compressed file, And the NAND flash memory designates a lower address of the memory as a page variable and an upper address of the memory as a block variable. The method of claim 8, It further comprises an information memory for storing the state and song information of the device, In the NAND flash memory, the header of the music file is recorded from the highest block address, and continuous data is recorded from the lowest block. An offset (maximum block-current block) of each header block and an offset of a music file are recorded in the information memory. The method of claim 9, One logical file starts with a block obtained from an offset stored by the information memory, and each block is configured to store the position of a block next to page 0 after data is written. Compressed file storage / playback device. The method of claim 9, The header information page of the NAND flash memory includes information indicating whether a corresponding block is defective, information indicating whether data is written, information indicating a data attribute recorded in the block, and A music compressed file storage / playback apparatus, characterized by being recorded including information indicating a block number. The method of claim 9, The music header page of the NAND flash memory includes a number of blocks used by a music file, a number of used equalizers, an actual size of a current file, a file name of a current file, a file recording time, and an MPEG header of a music file. Music compressed file storage / playback device, characterized in that. The device control signal line through which the device control signal for controlling the device flows, the device ready state display signal line through which the device readiness indication signal flows to indicate that the device is ready for operation, and the data for clocking data transmitted and received. A data clock signal line through which the clock signal flows and a data signal line flowing through the data in both directions, and perform data transfer with an external device to download and store the digital music compressed file from the external device, and to reproduce the stored music compressed file. In the compressed file storage / playback device, Detecting a low level switching of the device control signal line; A second step of bringing the device ready state indication signal line to a low level during a one-byte clock period upon detecting a low level transition in the first step; A third step of performing input / output of data through the data signal line when the data clock signal line advances to a low level state; A fourth step of confirming switching of the device ready status indication signal line to a high level; A fifth step of confirming the high level switch of the device control signal line when the high level switch is confirmed in the fourth step; A sixth step of repeating the second to fifth steps when the switching of the high level is not confirmed in the fifth step; And terminating the input / output of the data through the data signal line when the switching of the high level is confirmed in the fifth step. The device control signal line through which the device control signal for controlling the device flows, the device ready state display signal line through which the device readiness indication signal flows to indicate that the device is ready for operation, and the data for clocking data transmitted and received. A data clock signal line through which the clock signal flows and a data signal line flowing through the data in both directions, and perform data transfer with an external device to download and store the digital music compressed file from the external device, and to reproduce the stored music compressed file. In the compressed file storage / playback device, A first step of switching a device ready state display signal line to a low level when a low level change of the device control signal line is detected; A second step of reading one byte of data from the data clock signal line and the data signal line and bringing the device ready state indication signal line to a high level; Determining whether the read data is an instruction and deciphering the instruction; And a fourth step of determining data writing and reading according to the command and repeating data writing and reading until high level switching of the device control signal line. And write control method. The method of claim 14, If it is determined in step 4 that the data is read, the data read and write control method for recording and reproducing the music compressed file comprises receiving data from the data signal line after making the device ready state signal line low. . The method of claim 14, And if it is determined in the fourth step that the data is read, the device ready state display signal line is set at a low level, and then data writing is performed to the data signal line. The method according to any one of claims 13 to 16, The music compressed file is a control method characterized in that the MPEG1 Layer 3 form.