KR20030055326A - Data processor - Google Patents

Abstract

The present invention relates to a data processing apparatus capable of realizing a lower cost AV data transmission / reception system. The reception buffer monitoring circuit 21 monitors the data amount of the received data stored in the reception buffer 6, and when the accumulated data amount is larger than the upper threshold value, the reception clock generation circuit 8 generates the received clock. Set the frequency to a higher frequency. In addition, when the accumulation amount becomes smaller than the lower reference value, the reception clock frequency is set to a lower frequency. The AV decoder 7 decodes the AV data supplied from the reception buffer 6 based on the reception clock supplied from the reception clock generation circuit 8. The present invention can be applied to a television transmission / reception system for transmitting and receiving television broadcast signals.

Description

Data Processing Unit {DATA PROCESSOR}

1 shows the overall configuration of a conventional AV data transmission / reception system. On the transmission side, transmission AV data for transmission is input to the AV encoder 1. The AV encoder 1 compresses the input transmission AV data into, for example, an MPEG format based on the clock frequency generated by the transmission clock generation circuit 2. The transmission clock generation circuit 2 is constituted by a crystal oscillator or the like. The compressed data is stored in the transmission buffer 3 for clock exchange, and sent to the transmission device 4 whenever the transmission device 4 sends data. The transmitter 4 performs code conversion, modulation, etc. on transmission data, and sends it to a receiver side.

On the receiving side, the receiving device 5 receives the transmission data from the transmitting device 4, performs demodulation, code inverse conversion, and the like, restores the transmitted data, and stores the received data in the receiving buffer 6. . The data transfer rate between the transmitter 4 and the receiver 5 is sufficiently faster than the rate of AV data. The data stored in the reception buffer 6 is passed to the AV decoder 7 according to the timing processed by the AV decoder 7. The AV decoder 7 decodes (extends) the clock frequency generated by the reception clock generation circuit 8.

In the case of the system shown in Fig. 1, since the transmission clock input to the AV encoder 1 and the reception clock input to the AV decoder 7 do not become exactly the same frequency due to variations in manufacturing or the like. And a difference occurs in the processing speed. As described later with reference to FIGS. 2 and 3, overflow and underflow occur in the reception buffer 6, and as a result, the AV decoder 7 causes an excessive or insufficient processing data. This caused deterioration of the image and sound.

An example of overflow is shown in FIG. The AV encoder synchronous clock (FIG. 2A) is generated inside the AV encoder 1 by the transmission clock generated by the transmission clock generation circuit 2. As shown in FIG. In synchronization with the rise of this clock, encoded fixed-length AV data Dn (Fig. 2B) is stored in the transmission buffer 3 (size for two packets).

The transmission data Dn is received by the reception apparatus 5 after an arbitrary transmission delay (Fig. 2C) and stored in the reception buffer 6 (Fig. 2D). The received data Dn is sent from the reception buffer 6 to the AV decoder 7 (Fig. 2F) in accordance with the AV decoder synchronization clock (Fig. 2E), decoded, and output as received AV data.

The AV decoder synchronous clock (FIG. 2E) is generated inside the AV decoder 7 by the reception clock generated by the reception clock generation circuit 8. As shown in FIG. The data input in synchronization with the rise of this clock is decoded by the AV decoder 7. In this example, since the AV decoder synchronization clock (FIG. 2E) is slower than the AV encoder synchronization clock (FIG. 2A), the data overflows when the received data Dn + 5 is stored in the reception buffer 6 and overflows. Occurs.

3 shows an example of the case of underflow. As in the case of FIG. 2, AV data is processed. In this case, since the AV decoder synchronization clock (FIG. 3E) is faster than the AV encoder synchronization clock (FIG. 3A), the reception buffer 6 becomes empty before the reception data Dn + 3 is received (FIG. 3D). The buffer 6 cannot pass data to the AV decoder 7 when the AV decoder synchronization clock (Fig. 3E) rises, and underflow occurs.

<Start of invention>

This invention is made | formed in view of such a situation, and it is a simple structure, and it is possible to prevent an overflow and an underflow in a low cost system.

The data processing apparatus of the present invention includes a receiving means for receiving data, a storage means for storing data received by the receiving means, a processing means for processing data received by the receiving means, and a processing means. Generating means for generating a clock for use in processing the data received by the controller; and control means for controlling the frequency of the clock generated by the clock generating means based on the data amount of the data stored by the storage means. It features.

The processing means can cause the data received by the receiving means to be decoded.

The control means may control the clock to increase in frequency when the data amount is greater than the first reference value, and control the clock frequency to decrease when the data amount is smaller than the second reference value.

Separating means for separating the data received by the receiving means into first data and second data, wherein the storage means includes first storage means for storing the first data and second memory for storing the second data. Means, and the processing means may have first processing means for processing the first data and second processing means for processing the second data.

In the time difference between the entire processing time of the transmission system and the reception system of the first data and the second data, the amount of data that the first processing means can process is Buf1, and the average value of the first reference value and the second reference value is Bfu2. In doing so, the control means can make the value of the center of the range of the control target of the data amount stored in the first storage means correspond to the sum of Buf1 and Buf2.

The first data may be audio data, and the second data may be image data.

The data processing method of the present invention includes a receiving step of receiving data, a storage step of storing data received by the processing of the receiving step, a processing step of processing data received by the processing of the receiving step, and a processing step Is generated in the processing of the clock generating step based on the data amount of the data stored by the processing of the storing step and the amount of data stored by the processing of the storing step. And a control step of controlling the frequency of the clock.

The program of the recording medium of the present invention includes a receiving step of receiving data, a storing step of storing data received by the processing of the receiving step, a processing step of processing data received by the processing of the receiving step, and processing In the processing of the step, in the processing of the clock generating step, the generating step of generating a clock used when processing the data received by the processing of the receiving step and the amount of data of the data stored by the processing of the storing step And a control step of controlling the frequency of the generated clock.

In the data processing apparatus of the present invention, the frequency of the clock is controlled based on the data amount of the stored data.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly, to a data processing apparatus capable of processing data with a simple configuration.

1 is a block diagram showing a configuration example of a conventional AV data transmission / reception system.

2 illustrates an overflow that occurs in the system of FIG.

3 illustrates underflow occurring in the system of FIG.

4 is a block diagram showing a configuration example of an AV system transmission and reception system to which the present invention is applied.

5 is a flow chart describing the operation of the system of FIG.

FIG. 6 is a diagram for explaining a frequency of a reception clock generated in the reception clock generation circuit of FIG. 4. FIG.

FIG. 7 is a view for explaining the accumulation amount in the reception buffer of FIG. 4; FIG.

8 is a block diagram showing another configuration example of an AV data transmission / reception system to which the present invention is applied.

FIG. 9 is a diagram for explaining a difference between delay time of audio data and image data in the system of FIG. 8; FIG.

10 is a diagram showing a specific configuration of a system to which the present invention is applied.

FIG. 11 is a block diagram illustrating a configuration example of a channel selection device in FIG. 10. FIG.

12 is a block diagram illustrating an exemplary configuration of the display device of FIG. 10.

<Best Mode for Carrying Out the Invention>

4 shows a first embodiment of the AV data transmission / reception system of the present invention. This system basically has a configuration similar to the conventional system shown in FIG. In this system, however, the reception buffer monitoring circuit 21 is added, and the reception clock generation circuit 8 controls the generated clock frequency based on the output of the reception buffer monitoring circuit 21. The other structure is the same as that of the system in FIG.

Since the basic operation of the system of FIG. 4 is the same as that of the system shown in FIG. 1, the description thereof is omitted. In this system, since the method of generating the reception clock is different from that in the system of FIG. 1, this will be described below.

The reception buffer monitoring circuit 21 monitors the amount of data stored in the reception buffer 6, and when the reception buffer generation circuit 8 becomes larger than an arbitrary amount, for example, one field or the like. Raises the clock frequency that occurs at a rate of once per frame. In addition, when the amount of data stored in the reception buffer 6 is less than a certain amount, the clock frequency generated by the reception clock generation circuit 8 is lowered.

As a method of varying the frequency of the clock by the reception clock generating circuit 8, a clock having a frequency higher than that of the clock supplied to the voltage control oscillator VCO or the AV decoder 7 is counted by a counter to generate a clock. It is possible to change the counter value.

5 shows an actual control flowchart executed by the reception buffer monitoring circuit 21. First, in step S1, it is compared whether or not the data DataSize stored in the reception buffer 6 is less than a predetermined threshold Threshold LowThresh, and if less, then in step S4. In step S5, if it is determined that the clock is below the upper limit frequency HighLimit, the clock frequency is lowered in step S5. If the data amount DataSize stored in the reception buffer 6 is larger than the lower limit Threshold LowThresh, in step S2, it is compared whether or not it is larger than the upper limit Threshold HighThrcsh. In addition, if it is determined in step S6 that the clock is above the lower limit frequency LowLimit, then in step S7 the clock frequency is raised. If the amount of data stored in the reception buffer 6 is in the range of LowThresh <DataSize <HighThresh, nothing is done. Here, the frequencies of the upper and lower limits of the clock are determined for the following reasons.

1. In order not to deviate from the operating clock range of the AV decoder

2. To prevent sudden changes in the amount of data in the buffer

3. To operate in the event of an abnormality (for example, when data is not reached).

In step S3, it is determined whether or not the stop of control is commanded, and if not commanded, the process returns to step S1 and the subsequent processing is repeated. When the stop of control is commanded, the process ends.

6 shows the relationship between the clock inputted to the AV encoder 1 and the clock inputted to the AV decoder 7. Here, the clock input to the AV encoder 1 is referred to as ftx, and the clock input to the AV decoder 7 is referred to as frx. The clock input to the AV decoder 7 generated by the reception clock generation circuit 8 is controlled by the reception buffer monitoring circuit 21 in the range of the lowest clock frequency fl and the highest clock frequency fh. . The AV decoder 7 here operates in the range of fll <frx <fhh. For this reason, fl and fh are in this range, and fl <ftx should just satisfy ftx <fh.

Next, FIG. 7 shows a transition image of the data amount in the reception buffer 6. In this example, as in the example of FIG. 6, the clock frequency is controlled to be fh for increasing the clock and fl for decreasing the clock. In the initial state B1, since the reception buffer 6 is empty, it operates in the direction of storing data as frx = fh. Thereafter, the data storage amount of the reception buffer 6 determines that the clock is lowered at the time point B2 exceeding HighTresh, and is controlled in the direction of decreasing data with frx = fl. Thereafter, at the time B3 at which the data amount is lower than the value of LowTresh, it is determined that the clock is turned up, and frx = fh, the operation is again performed in the direction in which the data is stored, and the operation is continued in a repeated manner.

8 shows a second embodiment. In this example, the AV encoder 1 on the transmission side is composed of an audio encoder 1A and a video encoder 1V. In connection with this, the transmission clock generation circuit 2 is comprised by the transmission clock generation circuit 2A and the transmission clock generation circuit 2V. The output of the audio encoder 1A is supplied to the packet generation circuit 32 through the transmission buffer 31A, and the output of the video encoder 1V is input to the packet generation circuit 32 through the transmission buffer 31V. It is.

On the reception side, the packet decomposition circuit 41 provided in correspondence with the packet generation circuit 32 on the transmission side decomposes data input from the reception buffer 6 into audio packets and video packets, and decomposes the audio packets into the reception buffer. It outputs to the audio decoder 7A via 42A, and outputs a video packet to the video decoder 7V via the reception buffer 42V.

The reception buffer 21 is constituted by a reception buffer monitoring circuit 21A for monitoring the output of the reception buffer 42A and a reception buffer monitoring circuit 21V for monitoring the storage amount of the reception buffer 42V. have. The reception clock generation circuit 8 generates a reception clock based on the output of the reception buffer monitoring circuit 21A and outputs the reception clock to the audio decoder 7A, and the reception buffer monitoring circuit 21V. The reception clock generation circuit 8V generates a reception clock on the basis of the output of the &lt; RTI ID = 0.0 &gt;

The rest of the configuration is the same as in the case of FIG. 4.

The audio encoder 1A compresses the input transmission data (audio data) into MPEG transmission, for example, and passes it to the transmission buffer 31A. The audio encoder 1A operates based on the transmission clock generated by the transmission clock generation circuit 2A. On the other hand, the video encoder 1V compresses the transmission data (image data), for example, into MPEG or the like, based on the transmission clock generated by the transmission clock generation circuit 2V, and passes the result to the transmission buffer 31V. . The packet generation circuit 32 multiplexes the audio data from the transmission buffer 31A and the image data from the transmission buffer 31V, adds header information and the like necessary for decomposition on the receiving side, and generates a transmission packet. . The generated transmission packet is stored in the transmission buffer 3 and each time the transmission device 4 sends data, the next data is passed.

On the receiving side, the receiving device 5 receives the data and stores it in the receiving buffer 6. Next, the packet decomposition circuit 41 divides the audio data and the image data into the reception buffer 42A or the reception buffer 42V, respectively. In the audio system, the reception buffer monitoring circuit 21A varies the clock frequency generated by the reception clock generation circuit 8A in accordance with the amount of data stored in the reception buffer 42A. The audio decoder 7A decodes the received audio data on the basis of the clock supplied from the reception clock generation circuit 8A and outputs it as received data.

Similarly, in the image system, the reception buffer monitoring circuit 21V controls the reception clock generation circuit 8V in accordance with the amount of data stored in the reception buffer 42V to vary the clock frequency to the video decoder 7V. In this embodiment, the audio data and the image data are configured to be processed by each of the encoders 1A and 1V or the decoders 7A and 7V. Since the respective processing paths are different, there is a difference in the processing time. On the receiving side, it is necessary to match the delay times of the audio data and the image data.

9 shows an example of the delay relationship in each block of audio data and image data. In this case, it is assumed that synchronization is performed on the transmission data at the time of being input to the audio encoder 1A or the video encoder 1V. In the audio data processing path, the delay time excluding the common portion includes the delay time Tdae in the audio encoder 1A, the delay time Tdat in the transmission buffer 31A, and the delay in the reception buffer 42A. The sum of the time Tdar and the delay time Tdad at the audio decoder 7A is Tda. Here, Tdar is taken as the delay time in the average value ABufAve of LowThresh (step S1 of FIG. 5) and HighThresh (step S2 of FIG. 5) in audio data.

Next, in the image processing path, the delay time excluding common parts is similar to the delay time Tdve at the video encoder 1V, the delay time Tdvt at the transmission buffer 31V, and the reception buffer 42V. Let Tdv be the sum of the delay time Tdvr and the delay time Vdvd at the video decoder 7V. Here, Tdvr is set as the delay time in the average value VBufAve of LowThresh (step S1 of FIG. 5) and HighThresh (step S2 of FIG. 5) in image data. In this case, the processing path (processing time) of the image data is longer than the audio data (Tda < Tdv), and the difference is Tdav.

In order to synchronize the audio data with the image data, it is necessary to slow down the processing of the audio data by the time Tdav minutes. This delay can be realized by setting a threshold value stored in the reception buffer 42A. Specifically, if the data amount of audio data processed at time Tdav is ABufTdav, synchronization can be achieved by setting the center of the amount for storing audio data to ABufTdav + ABufAve. HighThresh and LowThresh are set above and below the center.

In the second embodiment, the reception side compensates for both the delay time difference between the audio data and the image data. However, the delay time difference may be adjusted to some extent in the buffer on the transmission side. In addition, although both audio data and image data have a clock adjustment function, in a system in which synchronization of audio data and image data is not a problem, a clock adjustment function for synchronizing audio data and image data is added to either system. You may take a structure to make.

FIG. 10 shows a specific application of the system of FIG. 4. As shown in Fig. 10, this television reception system is constituted by a channel selection device 101 and a display device 102 connected by wireless communication. Tuning device 101 is a stationary device according to the present invention is applied, for example, installed indoors in the home. In addition, the display device 102 is a display device according to the present invention, and is used in the vicinity of the user.

10, an antenna cable 111cb connected to a reception antenna 111 for receiving a television broadcast signal installed outdoors and connected into the indoor from the outdoors is connected to the channel selection device 101. The telephone line L connected to the telephone network and drawn indoors from the outdoors is connected.

The channel selection device 101 demodulates the television broadcast signal received and tuned by the antenna 111 and wirelessly transmits it to the display device 102 through the transmission / reception antenna 118 or through the telephone line L. FIG. It receives and demodulates the transmitted signal and wirelessly transmits it to the display device 102 via the transmission / reception antenna 118.

In addition, the channel selection device 101 receives transmission information such as indication information or electronic mail from the display device 102 through the transmission / reception antenna 118, and changes the television broadcast signal to be tuned in accordance with the received indication information. The transmission information can be transmitted via the telephone line L. FIG.

The display device 102 receives a signal of a television broadcast program that is wirelessly transmitted from the tuner device 101, and displays a picture according to the picture signal included in the received signal on the LCD (Liquid Crystal Display) 125. In addition to this, the sound of the audio signal included in the received signal is soundproofed from the speaker, thereby enabling viewing of a television broadcast program.

In addition, the display device 102 receives a signal such as, for example, an e-mail or a homepage of the Internet, which the channel selection device 101 receives through the telephone line L and transmits wirelessly, and forms a display signal from the received signal. In addition, an image corresponding to the display signal can be displayed on the LCD 125 and provided to the user.

In addition, a touch panel 351 is attached to the display screen of the LCD 125 of the display device 102 of this embodiment, and the display information displayed on the display screen of the LCD 125 and the touch panel 351 are used. For example, input of information such as various instruction inputs from a user can be accepted. By using the touch panel 351, various operations such as creating and sending an e-mail or receiving and displaying an e-mail to the user can be performed.

In this manner, the channel selection device 101 incorporates a television broadcast signal or various information provided through the telephone line L into the television reception system of the present embodiment, or transmits the information from the television reception system of the present embodiment to the communication network through the telephone line L. It has a function as an interface for sending a. In addition, the display device 102 has a function as a user interface that provides the user with information incorporated into the television reception system of the present embodiment by the channel selection device 101 or receives information from the user.

And as shown in FIG. 10, the channel selection apparatus 101 can be reliably connected to both according to the position where the connection terminal T1 with the antenna cable 111cb and the connection terminal T2 with the telephone line L were provided. Install and use at location. As shown in FIG. 10, since the channel selection device 101 and the display device 102 are connected wirelessly, the display device 102 can be used in any area where radio signals can be received from the channel selection device 101. ), The target television broadcast program can be watched, or an electronic mail can be transmitted and received by connecting to the Internet.

11 is a block diagram showing the configuration of the channel selection device 101 in more detail. Each unit of the channel selection device 101 is controlled by the control unit 200.

As shown in FIG. 11, the control unit 200 includes a CPU (Contral Processing Unit) 201, a ROM (Read Only Memory) 202, a RAM (Random Access Memory) 203, and an EEPROM (Electrically Erasable Programmable Read). Only Memory) 204 is a microcomputer configured and connected via the CPU bus 206.

Here, the ROM 202 records various processing programs to be executed by the channel selection device 101 of the present embodiment, data necessary for processing, and the like. The RAM 203 is mainly used as a work area for various processes, such as temporarily storing and storing data obtained in various processes.

The EEPROM 204 is a so-called nonvolatile memory. Even when the power is turned off, the stored information is not lost. For example, the EEPROM 204 stores the information of the broadcast channel that was tuned until immediately before the main power supply of the tuner 101 was turned off. After the power is turned on, the so-called last channel memory function can be realized to tune the broadcast signal of the channel that was tuned until the last time the power was turned off.

And as shown in FIG. 11, in the tuning device 101 of this embodiment, the antenna cable 111cb from the receiving antenna 111 for receiving the television broadcast signal installed in the outdoors is the line of the tuning device 101. As shown in FIG. The television broadcast signal, which is connected to the local section 112 and received by the receiving antenna 111, is supplied to the selecting section 112.

The tuner 112 tunes the television broadcast signal according to the tune instruction instruction signal from the control unit 200 among the television broadcast signals from the reception antenna 111, and transmits the tuned television broadcast signal to the demodulator 113. Supply. The demodulator 113 demodulates the television broadcast signal supplied thereto, and supplies the demodulated signal (signal of the television program) to the input terminal a of the switch circuit 114.

The switch circuit 114 is switched-controlled by the switching control signal from the control unit 200 and outputs a signal of a television program supplied from the demodulator 113 to the input terminal a, or supplied from the control unit 200 to the input terminal b. Switch whether or not to output the signal. In addition, the signal supplied from the control unit 200 to the switch circuit 114 is supplied to the channel selection device 101 via the telephone line L, as will be described later, of the electronic mail or the Internet received through the modem unit 210. It is a signal of so-called homepage information.

The signal output from the switch circuit 114 is supplied to the compression processing unit 115. The compression processing unit 115 compresses the data supplied thereto using a predetermined compression method. The compression processing unit 115 performs data compression on the signal from the switch circuit 114 using, for example, a data compression scheme such as a moving picture expert group (MPEG) scheme or a wavelet scheme.

The transmission clock generation circuit 401 is controlled by the CPU 201, generates a transmission clock, and supplies the transmission clock to the compression processing unit 115. As described above, the compression processing unit 115 performs compression processing in synchronization with this transmission clock.

The data compressed by the compression processing unit 115 is supplied to the transmission signal forming unit 116. The transmission signal forming unit 116 forms a transmission signal based on a predetermined communication protocol. In this embodiment, a transmission signal conforming to the IEEE (Institute Electrical and Electronics Engineers) 802.11 scheme or the power generation protocol is formed.

The transmission signal formed by the transmission signal forming unit 116 is supplied to the transmission processing unit 117S of the radio unit 117. The transmission processing unit 117S performs modulation processing and amplification processing of the transmission signal in accordance with the control signal from the control unit 200. The transmission signal processed by the transmission processing unit 117S is wirelessly transmitted through the common unit 117K and the transmission / reception antenna 118.

The common part 117K prevents the transmission signal and the reception signal from interfering with each other. In other words, as described above, the channel selection device 101 of the present embodiment is configured to be able to receive, via the transmit / receive antenna 118, instruction information or the like transmitted wirelessly from the display device 102. Therefore, the common unit 117K prevents the transmission signal from the transmission processing unit 117S from interfering with the reception signal received through the transmission / reception antenna 118.

Then, for example, a signal such as a channel selection instruction from the display device 102 received through the transmission / reception antenna 118 is supplied to the reception processing unit 117R through the common unit 117K. The reception processing unit 117R performs a process such as demodulating the signal supplied thereto, so as to be a signal that the control unit 200 can process, and supplies the signal to the control unit 200.

When the signal from the reception processing unit 117R is an instruction signal such as a channel selection instruction, the control unit 200 controls each unit in accordance with the instruction signal. Therefore, when the signal supplied from the reception processing part 117R to the control part 200 was a tuning instruction, the control part 200 supplies the tuning instruction signal according to the supplied tuning instruction to the tuning part 112, and performs tuning. The television broadcast signal can be changed.

In addition, when the signal supplied from the reception processing part 117R to the control part 200 was transmission information, such as an electronic mail, the control part 200 through the modem part 210 and the telephone line L, as mentioned later, It connects to a telephone line, sends out transmission information to the connected telephone line, and transmits it to the target counterparty.

As shown in FIG. 11, the modem unit 210 includes an interface (described as I / F in FIG. 11) unit 211 and a communication unit 212. The I / F unit 211 is a communication line connected between the other party and the channel selection device 101 via a telephone network, and a signal transmitted through a telephone line (phone line L) as an interface between the channel selection device 101. Is received or a signal from the channel selection device 101 is transmitted.

The communication unit 212 demodulates a signal received through the I / F circuit 211 and supplies it to the control unit 200, or modulates a transmission signal from the control unit 200, and modulates the received signal from the I / F circuit 211. Supplies). As a result, various data can be transmitted and received between the other party to which the telephone line is connected.

Therefore, as described above, the channel selection device 101 of the present embodiment connects to the Internet through the modem unit 210, the telephone line L, and a predetermined Internet Service Provider (ISP), and provides various kinds of information through the Internet. Receive or send or receive e-mail.

For this reason, the control unit 200 can control the modem unit 210 so that it can be off-hook or on-hook, and when the modem unit 210 is controlled to be off-hook, the control unit 200 transmits a dial signal to the telephone line. It also has a function as a so-called dialer.

11, the control part 200 is connected with the key input part 215 provided with the on / off key of a power supply, and the various setting keys, and the on / off of the main power supply of the tuner apparatus 101, and the like. Various setting inputs can be made via this key input unit 215.

In this manner, the channel selection device 101 according to the present embodiment can receive, tune, and demodulate a television broadcast signal, perform data compression on the demodulated television broadcast program, and transmit it wirelessly in accordance with a predetermined communication protocol. In addition, it is possible to receive and demodulate information provided through a telephone line, to compress the data as in the case of a television broadcast signal, and to wirelessly transmit it according to a predetermined communication protocol.

In addition, the channel selection device 101 according to the present embodiment receives instruction information such as a channel selection instruction that is wirelessly transmitted from the display device 102, which will be described later, performs processing according to the information, or transmits from the display device 102. The transmission information such as the e-mail, etc., which have been made, can be transmitted via the modem unit 210.

Next, the display device 102 wirelessly connected to the above-described channel selection device 101 will be described. 12 is a diagram for explaining the display device 102. The display device 102 is controlled by the control unit 300 of the microcomputer, in which the CPU 301, the ROM 302, the RAM 303, and the EEPROM 304 are connected via the CPU bus 305. have.

In the ROM 302, various processing programs executed by the display device 102, data necessary for processing, and the like are recorded. The RAM 303 is mainly used as a work area for various processes, such as temporarily storing and storing data obtained in various processes.

The EEPROM 304 is a so-called nonvolatile memory that does not lose its stored information even when the power is turned off. For example, the EEPROM 304 can store and store various setting parameters, created e-mails, received e-mails, and the like. .

First, the operation of the display device 102 in the case of receiving the radio signal from the channel selection device 101 will be described. The radio signal conforming to the predetermined communication protocol from the channel selection device 101 is received by the transmission / reception antenna 121 and supplied to the reception processing unit 122R through the common unit 122K. The reception processing unit 122R performs processing such as demodulating the signal supplied thereto, and supplies the demodulated signal to the decompression processing unit 123 through the reception buffer 501.

The reception buffer monitoring circuit 502 monitors the data amount of the reception buffer 501 and controls the reception clock generation circuit 503 in accordance with the data accumulation amount. The reception clock generation circuit 503 generates a reception clock of a frequency corresponding to the amount of data stored in the reception buffer 501 and supplies it to the decompression processing unit 123. The decompression processing unit 123 performs decompression processing in synchronization with the reception clock.

As described above, since the signal to be transmitted wirelessly is transmitted after data is compressed, the decompression processing unit 123 of the display device 102 decompresses the demodulated signal from the channel selection device 101. Restore the original signal. When the restored signal is a signal of a television broadcast program or the like, since the restored signal is composed of an image signal and an audio signal, the image signal is supplied to the image signal processing unit 124, and the audio signal is an audio signal processing unit. 126 is supplied.

The image signal processing unit 124 forms a display signal from the image signal from the decompression processing unit 123 and supplies it to the LCD 125. As a result, the LCD 125 displays an image corresponding to the image signal wirelessly transmitted from the channel selection device 101. On the other hand, the audio signal processing unit 126 forms an audio signal supplied to the speaker 127 from the audio signal supplied thereto, and supplies this to the speaker 127. As a result, the sound from the speaker 127 in accordance with the sound signal transmitted wirelessly from the channel selection device 101 is soundproofed.

In this way, the display device 102 receives a signal such as a television broadcast program that is wirelessly transmitted from the channel selection device 101, and reproduces and outputs an image signal or an audio signal of the received signal to provide to the user. It can be.

The series of processes described above can be executed by hardware, but can also be executed by software.

In addition, in this specification, the step of describing the program recorded on the recording medium includes not only the processing performed in time series according to the described order, but also the processing executed in parallel or separately, without necessarily being processed in time series. will be.

In addition, in this specification, a system shows the whole apparatus comprised by several apparatus.

By using the present invention, even if there is no time information in the packet of AV data, data of the transmitting side and the receiving side can be synchronized. In addition, it is possible to synchronize audio and images as necessary. Therefore, for example, an AV data transmission / reception system capable of stable operation can be constructed without using a packet such as an MPEG transport stream. This eliminates the need for circuits such as time stamp information addition processing on the transmitting side and the clock regeneration circuit on the receiving side. As a result, the circuit scale can be reduced and a low cost system can be realized.

Claims (8)

Receiving means for receiving data, Storage means for storing data received by the receiving means; Processing means for processing data received by the receiving means; Generating means for generating a clock which said processing means uses when processing data received by said receiving means; Control means for controlling the frequency of the clock generated by the clock generating means based on the data amount of data stored by the storage means Data processing apparatus comprising a. The method of claim 1, And said processing means decodes the data received by said receiving means. The method of claim 1, The control means controls the frequency of the clock to increase when the data amount is greater than a first reference value, and to control the frequency of the clock to decrease when the data amount is less than a second reference value. Device. The method of claim 3, Separating means for separating the data received by the receiving means into first data and second data, The storage means, First storage means for storing the first data; Second storage means for storing the second data With The processing means, First processing means for processing the first data; Second processing means for processing the second data Data processing apparatus having a. The method of claim 4, wherein In the time difference between the total processing time of the transmission system and the reception system of the first data and the second data, the amount of data that can be processed by the first processing means is Buf1, and the average value of the first reference value and the second reference value is When setting it as Bfu2, the said control means makes a value of the center of the range of the control object range of the amount of data memorize | stored in the said 1st memory means correspond to the sum of said Buf1 and Buf2. The method of claim 5, The first data is voice data, And said second data is image data. A receiving step of receiving data, A storage step of storing data received by the processing of the reception step; A processing step of processing data received by the processing of the receiving step; A generating step of generating a clock which is used when processing data received by the processing of the receiving step, in the processing of the processing step; A control step of controlling the frequency of the clock generated by the processing of the clock generation step based on the data amount of data stored by the processing of the storage step Data processing method comprising a. A receiving step of receiving data, A storage step of storing data received by the processing of the reception step; A processing step of processing data received by the processing of the receiving step; A generating step of generating a clock which is used when processing data received by the processing of the receiving step, in the processing of the processing step; A control step of controlling the frequency of the clock generated by the processing of the clock generation step based on the data amount of data stored by the processing of the storage step And a computer readable program recorded thereon.