KR20030054886A - Semiconductor memory device with block-unit refresh function - Google Patents

Abstract

PURPOSE: A semiconductor memory apparatus having a block-base refresh function is provided to reduce the power consumption upon performing a refresh operation by combining a control signal and a decoded row address signal to assign a memory block. CONSTITUTION: A semiconductor memory array(360) has a region that is divided into blocks. A refresh operation generator(310) receives control signals to generate a refresh signal and an entry signal. A mode resistor(370) receives the control signals and an external address to generate a starting signal. A refresh counter(330) counts a row address to be refreshed upon performing a refresh operation. A low address buffer(320) buffers the external address to output it or buffers the low address generated in the refresh counter(330) to output it. A low decoder(340) decodes the low address generated from the low address buffer(320). A block selector(350) combines the output signal of the low decoder(340), the refresh signal, the entry signal, and the starting signal to assign a memory block.

Description

Semiconductor memory device with block unit refresh function {SEMICONDUCTOR MEMORY DEVICE WITH BLOCK-UNIT REFRESH FUNCTION}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of reducing power consumption during a refresh operation.

In general, semiconductor memory devices are classified into dynamic memory devices (Dynamic RAM, hereinafter referred to as DRAM) and static memory devices (Static RAM, hereinafter referred to as SRAM). SRAM implements a base cell with four transistors that form a latch, so the stored data is intact and preserved unless the power source is removed. Thus, no refresh operation to recharge the data is required. However, DRAM constitutes a basic cell with one transistor and one capacitor, and stores data in the capacitor. However, leakage current may be generated in the capacitor in the integrated circuit, and data may be damaged. Therefore, in the case of DRAM, a refresh operation for periodically recharging data in a memory cell is required.

In recent years, according to the trend of high integration and large capacity, semiconductor memory devices are divided into a plurality of memory banks in a single chip. In the case of portable products such as cordless phones and PDAs (Personal Digital Assistance), only a small portion of the entire internal memory of the product is often used. Research has been conducted to reduce power consumption by only refreshing.

Japanese Laid-Open Patent Publication No. 2000-113667 includes a register corresponding to a row address, and writes a write operation access history therein to stop the refresh operation of the row address in which the write operation has not been executed, thereby reducing power consumption. Techniques for reducing are disclosed.

1 is a block diagram showing a conventional DRAM device disclosed in Japanese Patent Laid-Open No. 2000-113667, and FIG. 2 is a block diagram specifically showing a row register section in FIG.

Hereinafter, a DRAM device according to the prior art will be described with reference to FIGS. 1 and 2.

The access requesting unit 101 receives the refresh command for holding the internal data of the DRAM, the write command for writing the data in the DRAM, or the READ command for reading the data held in the DRAM, and receives the refresh command. To the refresh operation generating unit 102 and the row address buffer unit 104, to notify the row address buffer unit 104 via the line L5, and to the row register unit 106 through the line L1. Notice).

The refresh operation generating unit 102 generates a refresh operation at a time interval in which a refresh operation is required to maintain the internal data of the DRAM, and notifies the refresh counter 103 and the row address buffer unit 104. The refresh counter 103 stores the row address of the initial value for refreshing the DRAM and counts the row address when the refresh request is notified. The row address buffer unit 104 selects a row address generated by the refresh counter unit during the DRAM refresh operation, selects an external row address input by the line L4 in other cases than the refresh operation, and selects the row decoder unit ( 105, a row address is notified. The row decoder unit 105 decodes the row address notified from the row address buffer unit 104 by corresponding to a word line in the DRAM array, and notifies the row register unit 106 via the line L2.

The row register section 106 checks the presence or absence of a write operation with respect to the notified request, and if there is a write operation, writes the execution history into the row register corresponding to the access request of the write command, and then executes the access request. In addition, the read request is checked for the presence or absence of a read operation, and when there is a read operation, the access request is executed without writing the execution history into the row register corresponding to the access request of the read instruction. In addition, if there is a refresh operation, it checks whether or not there is a refresh operation. If there is a refresh operation, the execution history of the write instruction of the row register corresponding to the access request of the refresh instruction is referred to. Do not run.

Next, the operation of the row register section 106 will be described with reference to FIG. As shown in FIG. 2, the row register section 106 includes a latch circuit 210 and an AND circuit 220. The latch circuit 210 receives data from the latch circuit data input unit 230 for inputting data into the latch circuit 210 and the latch circuit control signal input unit 250 and the latch circuit 210 for controlling the latch circuit 210. And a latch circuit data output unit 240 for outputting the signal. The data output from the latch circuit 210 forms the logical product of the signal input from the line L2 and is output to the line L3. At the start of the DRAM operation, the internal data of the latch circuit 210 shown in Fig. 2 is initialized to " 0 ".

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of reducing power consumption by refreshing only a block including a memory cell having a history of previously writing data in the refresh mode.

Another object of the present invention is to provide a semiconductor memory device which designates a memory block by combining a refresh signal, a write signal, and a start signal and a decoded row address signal, which are control signals generated using control signals.

Still another object of the present invention is to provide a semiconductor memory device capable of initializing a register containing information indicating that data has been written using a signal generated from a mode register.

1 is a block diagram illustrating a conventional memory device performing refresh operations in row address units.

FIG. 2 is a block diagram specifically illustrating a row register unit in FIG. 1.

FIG. 3 is a block diagram illustrating a memory device of the present invention performing refresh operation in block units.

FIG. 4 is a circuit diagram illustrating the block selector in FIG. 3 in detail.

<Description of the symbols for the main parts of the drawings>

310: refresh operation generator 320: row address buffer

330: refresh counter 340: low decoder

350: block selector 360: memory array

370: mode register 401, 407, 408: NAND gate

402, 404, 409, 416, 426, 436: inverter

403: pull-down transistor 405: pull-up transistor

406: latch circuit

A semiconductor memory device of the present invention for achieving the above object, the semiconductor memory array having a region divided into blocks; A refresh operation generator that receives the control signals and generates a refresh signal and a write signal; A mode register configured to receive the control signals and an external address to generate a start signal; A refresh counter for counting row addresses to be refreshed during a refresh operation; A row address buffer for buffering and outputting the external address or for buffering and outputting a row address generated by the refresh counter during a refresh operation; A row decoder for decoding a row address generated from the row address buffer; And a block selector for designating a memory block by combining the output signal of the row decoder with the refresh signal, the write signal, and the start signal, wherein the memory cell has previously written data during the refresh operation. It is characterized by refreshing only blocks.

The refresh operation generator is configured to provide the write signal generated in the write mode to the row decoder and the block selector, and the refresh signal generated in the refresh mode to the row address buffer, the refresh counter, the row decoder, and the It is characterized by providing a block selector.

The mode register is characterized by initializing a register containing information indicating that data has been written among the registers in the block selector by generating and providing the start signal to the block selector.

The row address buffer selects a row address generated by the refresh counter when the semiconductor memory device is in a refresh operation, and buffers a row address input to the semiconductor memory device from outside from the refresh operation to the row decoder. It is characterized by providing a row address.

The row decoder may decode a row address provided from the row address buffer so as to correspond to a word line inside the semiconductor memory device, and provide the row address to the block selector.

The block selector includes: a first AND circuit for performing an AND operation on the decoded row address signal and a write signal; A pull-down transistor configured to receive an output signal of the first AND circuit and pull down a voltage of an output node; An inverter circuit for receiving the start signal and outputting an inverted signal; A pull-up transistor configured to receive an output signal of the inverter circuit and pull up a voltage of the output node; A latch circuit for latching a voltage of the output node; A NAND circuit which non-logically outputs the output signal of the latch circuit and the refresh signal; And a second AND circuit for performing an AND operation on the output of the NAND circuit and the decoded row address signal, and outputting a signal for selecting a corresponding block of the semiconductor memory array.

Example

Hereinafter, a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a block diagram illustrating a memory device according to an embodiment of the present invention for refreshing block by block. FIG. 4 is a circuit diagram illustrating the block selector of FIG. 3 in detail.

A block-by-block refreshable semiconductor memory device of the present invention has a plurality of memory blocks. In the present specification, for convenience of description, a semiconductor device having a memory array including eight memory blocks will be described.

In FIG. 3, 310 is a refresh operation generator for generating a refresh signal, a write signal, and a start signal to provide to a DRAM device. 320 is a row address buffer that buffers a row address input to the memory device and a row address generated by the refresh counter. 330 is a refresh counter that counts the row addresses to refresh the memory device. 340 is a row decoder that decodes the row address generated in the row address buffer. 350 is a block selector that designates a memory block by combining the output signal of the row decoder with the refresh signal, the write signal, and the start signal. 360 is a memory array. 370 is a mode register for generating a start signal for initializing the register in the block selector 350.

As shown in FIG. 3, the refresh operation generator 310 includes a clock signal CLK, a clock enable signal CKE, a chip select signal CSB, a row address strobe signal RABB, and a column address strobe signal CASB. ), Control signals such as the write enable signal WEB are input, and the refresh signal pREF and the write signal pWR are generated and provided to the memory device. The refresh signal pREF is provided to the row address buffer 320, the refresh counter 330, the row decoder 340, and the block selector 350, and the write signal pWR is provided to the row decoder 340 and the block selector ( 350 is provided.

The mode register 370 generates a start signal pSTART to provide to the block selector 350 to initialize a register containing information indicating that data has been written among the registers in the block selector 350. The start signal pSTART is the clock signal CLK when the chip select signal CSB, the row address strobe signal RABS, the column address strobe signal CASB, and the write enable signals WEB are all low when the mode is set. Is generated by receiving an external address at the high edge of.

When the refresh counter 330 receives the refresh signal from the refresh operation generator 310, the refresh counter 330 counts the row address to be refreshed and provides the result to the row address buffer.

The row address buffer 320 selects a row address generated by the refresh counter 330 during the refresh operation, and selects a row address externally input to the row decoder 340 in a case other than the refresh operation.

The row decoder 340 decodes the row address received from the row address buffer 320 by corresponding to a word line in the memory array and provides the block address to the block selector 350.

The block selector 350 may include the refresh signal pREF and the write signal pWR received from the refresh operation generator 310, the start signal pSTART received from the mode register 370, and the decoded row address signal (FIG. 3). Block selection signals (BLS (0) to BLS (7) in FIG. 3) are generated by the combination of DRAi (0) to DRAi (7).

Hereinafter, the block selector 350 of the present invention will be described in detail with reference to FIG. 4.

As shown in FIG. 4, the block selector 350 of the present invention non-logically outputs the decoded row address signal DRAi (0) and the write signal pWR and outputs the NAND circuit 401 and the NAND circuit 401. An inverter circuit 402 for receiving the output of the output signal and outputting the inverted signal, a pull-down transistor 403 for receiving the output signal of the inverter 402 and pulling down the voltage of the output node N1, and receiving the start signal pSTART. The inverter circuit 404 for outputting the inverted signal, the pull-up transistor 405 for receiving the output signal of the inverter circuit 404 and pulling up the voltage of the output node N1, and the inverter circuits 416, 426, 436. And a latch circuit 406 for latching the voltage of the output node N1, an NAND circuit 407 and an NAND circuit 407 for non-logically outputting the output signal of the latch circuit 406 and the refresh signal pREF. NAND for outputting a non-logically multiplied output and the decoded row address signal DRAi (0) An inverter circuit 409 for inverting the output of the circuit 408 and the NAND circuit 408 and outputting the block selection signal BLS (0).

The block selector 350 of the present invention receives the row address signal DRAi (0), the refresh signal pREF, the write signal pWR, and the start signal pSTART as inputs, and receives the block select signal BLS (0). Output)). Here, the write signal pWR is a signal that becomes "high" in the write operation mode, and the refresh signal pREF is a signal that becomes "high" in the refresh operation mode. The start signal pSTART is a "high pulse" which is generated once when the memory is first used. Generally, the start signal pSTART is generated and transmitted to the memory only once when the system uses the memory.

When using the memory for the first time, if the start signal pSTART of "high pulse" is transmitted to the memory, the output node N1, which is the drain terminal of the pull-up transistor 405, is driven by the "low" signal passing through the inverter 404. Latched "high".

If a write operation is performed to the corresponding block during the operation, a section in which DRAi (0) becomes “high” and the write signal pWR is also “high” occurs in a corresponding cycle, and a NAND gate and an AND gate are generated. The pulled-out transistor 403 is turned on because the output passed is " high ", so that the state of the output node N1 is latched to " low ". When the output node N1 becomes " low ", the output of the latch circuit 406 becomes " low ", and the output of the NAND circuit 407 becomes " high " and this value is maintained and the block select signal BLS (0) is controlled only by the row address signal DRAi (0) as in the conventional operation.

If the block has never performed a write operation, the output node N1 is latched "high" and the output of the latch circuit 406 becomes "high". At this time, in the case of no refresh operation, the refresh signal pREF becomes " low " and is controlled only by the row address signal DRAi (0), as in the conventional operation. On the other hand, in the case of the refresh operation, since the refresh signal pREF is " high ", the output of the NAND circuit 407 is determined by the state of the output node N1, and if the write operation has not been performed once in the past, the output The node N1 remains " high, " the output of the NAND circuit is " low ", and the block select signal BLS (0), which is the output of the block selector 350, is " low " Operation is prohibited.

In the refresh operation, there is a method of performing one refresh with a single command and a method of automatically repeating the refresh operation by a timer in the memory when the command is issued and waited. The present invention is applied to both of them. .

When booting a system that uses memory, during cell testing, initialization is required because every block of memory is written once. The start signal pSTART is a signal initialized when the memory is used for the first time. In the present invention, the chip select signal CSB, the row address strobe signal RASB, the column address strobe signal CASB, and the writing are performed in the mode register 370. When the enable signals WEB are all low, they are generated by receiving an external address at the high edge of the clock signal CLK.

The less the portion of the total memory array is used, that is, the fewer cells have a history of write operations, the less power is consumed during the refresh operation. Assuming that the memory array of the memory device as shown in FIG. 3 is one memory bank, in the case of a memory array having four memory banks, the memory array may be composed of 32 small blocks. If only the first block of the first bank in this memory has a write history, according to the configuration of the present invention, the refresh operation of the memory cell is performed only for 1/32 hours of the total refresh time, thereby reducing power consumption. .

Although the present invention describes a method of controlling a memory block, the present invention can be applied to a device for selecting a memory bank, and in this case, the peripheral portion of the memory can also be controlled, so that a process such as address decoding can be omitted. There is this.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, in the semiconductor memory device according to the present invention, a refresh operation is performed by designating a memory block by combining a refresh signal, a write signal, and a start signal and a decoded row address signal, which are control signals generated using control signals. In this case, since only a block including a memory cell having a history of writing data can be refreshed, power consumption in the memory device can be reduced. In addition, the semiconductor device according to the present invention can initialize a register containing information indicating that data has been written using a signal generated from the mode register.

Claims (6)

A semiconductor memory array having regions divided into blocks; A refresh operation generator that receives the control signals and generates a refresh signal and a write signal; A mode register configured to receive the control signals and an external address to generate a start signal; A refresh counter for counting row addresses to be refreshed during a refresh operation; A row address buffer for buffering and outputting the external address or for buffering and outputting a row address generated by the refresh counter during a refresh operation; A row decoder for decoding a row address generated from the row address buffer; And A block selector for designating a memory block by combining the output signal of the row decoder with the refresh signal, the write signal, and the start signal; And in the refresh operation, only a block including a memory cell to which data was previously written is refreshed. The method of claim 1, wherein the refresh operation generator Providing the write signal generated in the write mode to the row decoder and the block selector, and providing the refresh signal generated in the refresh mode to the row address buffer, the refresh counter, the row decoder, and the block selector. A semiconductor memory device characterized by the above-mentioned. The method of claim 1, wherein the mode register is And generating the start signal to the block selector to initialize a register containing information indicating that data has been written among the registers in the block selector. The method of claim 1, wherein the row address buffer is When the semiconductor memory device is in a refresh operation, a row address generated by the refresh counter is selected, and in a case other than the refresh operation, a row address input to the semiconductor memory device is buffered to provide a row address to the row decoder. A semiconductor memory device, characterized in that. The method of claim 1, wherein the row decoder And decoding a row address provided from the row address buffer so as to correspond to a word line inside the semiconductor memory device and providing the block address to the block selector. The method of claim 1, wherein the block selector A first AND circuit for performing an AND operation on the decoded row address signal and a write signal; A pull-down transistor configured to receive an output signal of the first AND circuit and pull down a voltage of an output node; An inverter circuit configured to receive the start signal and output an inverted signal; A pull-up transistor configured to receive an output signal of the inverter circuit and pull up a voltage of the output node; A latch circuit for latching a voltage of the output node; A NAND circuit which non-logically outputs the output signal of the latch circuit and the refresh signal; And And a second AND circuit for performing an AND operation on the output of the NAND circuit and the decoded row address signal, and outputting a signal for selecting a corresponding block of the semiconductor memory array.