KR20030054802A - Method for Fabricating of Semiconductor Device - Google Patents
Method for Fabricating of Semiconductor Device Download PDFInfo
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- KR20030054802A KR20030054802A KR1020010085214A KR20010085214A KR20030054802A KR 20030054802 A KR20030054802 A KR 20030054802A KR 1020010085214 A KR1020010085214 A KR 1020010085214A KR 20010085214 A KR20010085214 A KR 20010085214A KR 20030054802 A KR20030054802 A KR 20030054802A
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- film
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- organic antireflection
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- polysilicon
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims description 10
- 229910001423 beryllium ion Inorganic materials 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract description 10
- 230000005465 channeling Effects 0.000 abstract description 8
- 239000002019 doping agent Substances 0.000 abstract description 5
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 5
- 238000011109 contamination Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Ceramic Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
본 발명은 반도체 소자에 관한 것으로 특히, 이온 주입 공정시 채널링(Channeling)을 방지하고 도펀트(Dopant) 농도를 균일하게 분포시키기 위한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for preventing channeling and uniformly distributing a dopant concentration during an ion implantation process.
이하, 첨부된 도면을 참조하여 종래 기술에 따른 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
고속 소자 공정에서 사용되는 폴리 실리콘(Poly-Si)은 매우 높은 저항을 갖는 저항체 물질로서 불순물 주입 공정을 통해 게이트 전극을 포함한 전도층 및 기타 여러 가지 용도로 이용되고 있다.Poly-Si (Poly-Si) used in a high-speed device process is a resistor material having a very high resistance, and is used for a conductive layer including a gate electrode and various other applications through an impurity implantation process.
폴리 실리콘은 아래 식 1과 같은 반응식에 따라 사일렌(Silane) 가스의 열분해 반응으로 증착되며 일반적인 증착 온도는 600∼650℃이다.Polysilicon is deposited by the pyrolysis reaction of Silane (Silane) gas according to the following reaction formula 1, and the general deposition temperature is 600 ~ 650 ℃.
(식 1)(Equation 1)
SiH4(g) → Si(s) + 2H2(g)SiH 4 (g) → Si (s) + 2H 2 (g)
이때, 얻어지는 폴리 실리콘은 주상형(Columnar) 구조를 갖는 다결정 상태이다.At this time, the obtained polysilicon is in a polycrystalline state having a columnar structure.
이와 같은 주상형 폴리 실리콘은 차후에 주입되는 이온에 의해 채널링(Channeling) 현상이 빈번히 발생되는 문제점을 갖는다.Such columnar polysilicon has a problem in that a channeling phenomenon is frequently generated by ions injected later.
채널링이란, 불순물 주입 공정인 임프란테이션(Implantation) 공정에서 주입된 이온들이 어떤 결정 구조를 갖는 타겟(Target) 속으로 진행하여, 이온의 진행 방향이 결정 내부의 틈(Interstitial Site)으로 연속적으로 연결된 채널 방향으로 입사될 때 일어나는 현상으로, 예상되는 주입 범위(Rp: Projection Range)보다 훨씬 깊은 지점까지 도달되는 불순물 분포를 가리킨다.Channeling means that the ions implanted in the implantation process, which is an impurity implantation process, proceed into a target having a certain crystal structure, and the direction of movement of the ions is continuously connected to the interstitial site within the crystal. Phenomenon that occurs when incident in the channel direction, refers to the distribution of impurities reaching a point far deeper than the expected injection range (R p : Projection Range).
종래에는 이를 방지하기 위한 방법으로 도 1에 도시된 바와 같이, 랜덤 임플란테이션(Random Implantation)이 되도록 이온 빔(Ion Beam)과 웨이퍼(Wafer)(11)의 결정축을 틸트(Title)시키거나, 도 2에 도시된 바와 같이, 웨이퍼(11)와 이온주입 물질층(13) 사이에 산화막과 같은 비정질층(12)을 형성하거나, 도 3에 도시된 바와 같이, 매트릭스 원자(Matrix atom) 등의 이온 빔(Ion Beam)을 이용하여 이온 주입 물질층(13)의 표면을 미리 비정질화시키는 방법 등을 사용하고 있다.In the related art, as shown in FIG. 1, as shown in FIG. 1, the crystal axes of the ion beam and the wafer 11 are tilted to be random implantation. As shown in FIG. 2, an amorphous layer 12, such as an oxide film, is formed between the wafer 11 and the ion implantation material layer 13, or as shown in FIG. 3, such as a matrix atom. A method of pre-amorphizing the surface of the ion implantation material layer 13 using an ion beam is used.
그러나, 상기와 같은 종래의 반도체 소자의 제조방법은 다음과 같은 문제점이 있다.However, the conventional method of manufacturing a semiconductor device as described above has the following problems.
첫째, 산화막과 같은 비정질층을 형성하거나, 이온주입 물질층을 비정질화하기 위한 공정을 추가적으로 실시해야 하므로 제조 비용이 증가되며, 공정이 복잡해진다.First, since a process for forming an amorphous layer such as an oxide film or an amorphous layer of an ion implantation material layer has to be additionally performed, manufacturing cost increases and the process becomes complicated.
둘째, 틸트각을 가지고 이온 주입을 실시하므로 소자 특성을 변화시키게 된다.Second, since ion implantation is performed with a tilt angle, device characteristics are changed.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 소자 특성 변화 및 제조비용 증가 없이 채널링을 방지할 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device that can prevent channeling without changing device characteristics and increasing manufacturing costs.
도 1 내지 도 3은 종래 기술에 따른 채널링 방지를 위한 방법을 나타낸 도면1 to 3 illustrate a method for preventing channeling according to the prior art.
도 4a 내지 도 4d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 나타낸 도면4A to 4D illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 5는 본 발명을 이용하여 형성된 반도체 소자의 표면 깊이에 따른 주입되는 이온의 농도를 나타낸 도면5 is a view showing the concentration of ions implanted in accordance with the surface depth of the semiconductor device formed using the present invention
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings
21 : 반도체 기판 22 : 폴리 실리콘막21 semiconductor substrate 22 polysilicon film
23 : 유기 반사방지막 24 : 레지스트23 organic antireflection film 24 resist
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은 반도체 기판상에 폴리 실리콘막을 형성하는 단계와, 상기 폴리 실리콘막상에 유기 반사방지막을 형성하는 단계와, 상기 유기 반사방지막상에 감광막을 도포하는 단계와, 상기 감광막를 선택적으로 패터닝하여 이온 주입될 영역의 유기 반사방지막을 노출하는 단계와, 상기 감광막를 마스크로하여 상기 폴리 실리콘막에 이온을주입하는 단계와, 상기 감광막과 유기 반사방지막을 제거하는 단계를 포함하여 형성함을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a polysilicon film on a semiconductor substrate, forming an organic antireflection film on the polysilicon film, on the organic antireflection film Applying a photoresist film, selectively patterning the photoresist film, exposing an organic antireflection film in a region to be ion implanted, implanting ions into the polysilicon film using the photoresist film as a mask, the photoresist film and the organic antireflection film Forming comprising the step of removing.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
도 4a 내지 도 4d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 나타낸 도면이고, 도 5는 본 발명을 이용하여 형성된 반도체 소자의 표면 깊이에 따른 주입되는 이온의 농도를 나타낸 도면이다.4A to 4D are views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 5 is a view showing concentrations of ions implanted according to the surface depth of a semiconductor device formed using the present invention.
본 발명에 따른 반도체 소자의 제조방법은 우선, 도 4a에 도시된 바와 같이 반도체 기판(21)상에 폴리 실리콘막(22)을 형성하고 상기 폴리 실리콘막(22)상에 유기 반사방지막(Orgnic BARC : Orgnic Bottom Anti Reflectory Coting)(23)을 형성한다.In the method of manufacturing a semiconductor device according to the present invention, first, as shown in FIG. 4A, a polysilicon film 22 is formed on a semiconductor substrate 21 and an organic antireflection film is formed on the polysilicon film 22. Form Orgnic Bottom Anti Reflectory Coting) (23).
이때, 상기 유기 반사방지막(23)의 두께는 이후 포토 공정에서의 기판 반사도를 최소화하고 이온 주입 공정시 문제가 되지 않도록 200∼2000Å의 두께로 형성한다.At this time, the thickness of the organic anti-reflection film 23 is formed to a thickness of 200 ~ 2000Å so as to minimize the reflectivity of the substrate in the subsequent photo process and not become a problem during the ion implantation process.
이어, 180∼240℃로 베이킹(Baking) 공정을 실시한다.Subsequently, a baking process is performed at 180 to 240 ° C.
이어, 도 4b에 도시된 바와 같이 상기 유기 반사방지막(23)상에 레지스트(24)를 도포한다.Next, as shown in FIG. 4B, a resist 24 is coated on the organic antireflection film 23.
이어, 도 4c에 도시된 바와 같이, 노광 및 현상 공정으로 상기 레지스트(24)를 패터닝한다.Next, as shown in FIG. 4C, the resist 24 is patterned by an exposure and development process.
이어, 패터닝된 레지스트(24)를 마스크로 상기 폴리 실리콘막(22)에 이온 주입 공정을 실시한다.Subsequently, an ion implantation process is performed on the polysilicon layer 22 using the patterned resist 24 as a mask.
이때, 상기 주입된 이온들은 상기 유기 반사방지막(23)의 원자들과 충돌하여 랜덤(Random)한 방향으로 분산되게 된다.In this case, the implanted ions collide with the atoms of the organic anti-reflection film 23 to be dispersed in a random direction.
따라서, 상기 유기 반사방지막(23)은 상기 폴리 실리콘막(22)으로 채널링되는 이온을 막기 위한 일종의 보호막의 역할의 역할을 함과 동시에 얕은 접합(Shallow Junction) 형성시 도펀트가 균일하게 분포할 수 있도록 하며, 다른 물질로부터의 오염 및 이온 주입에 따른 표면 오염을 방지하는 역할을 한다.Therefore, the organic anti-reflection film 23 serves as a kind of protective film to prevent ions channeled into the polysilicon film 22 and to uniformly distribute the dopant when forming a shallow junction. It also serves to prevent surface contamination due to contamination from other materials and ion implantation.
이어, 도 4d에 도시된 바와 같이, 상기 포토레지스트(24)와 유기 반사방지막(23)을 제거한다. 상기 유기 반사방지막(23)은 별도의 제거 공정없이 포토레지스트(24)의 스트립(Strip) 공정시 함께 제거되게 된다.Next, as shown in FIG. 4D, the photoresist 24 and the organic antireflection film 23 are removed. The organic anti-reflection film 23 is removed together during the strip process of the photoresist 24 without a separate removal process.
이와 같이 형성된 본 발명에 따른 반도체 소자는 도 5에 도시된 바와 같이, 0.28㎛ 이하의 깊이로는 이온이 거의 주입되지 않게 되므로 채널링 현상이 발생되지 않음을 알 수 있다.As shown in FIG. 5, in the semiconductor device formed as described above, since the ions are hardly implanted at a depth of 0.28 μm or less, the channeling phenomenon does not occur.
상기와 같은 본 발명의 반도체 소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing a semiconductor device of the present invention as described above has the following effects.
첫째, 별다른 추가공정 없이도 채널링을 방지할 수 있다.First, channeling can be prevented without any additional steps.
둘째, 얕은 접합에서 균일한 도펀트 분포를 얻을 수 있다.Second, a uniform dopant distribution can be obtained at shallow junctions.
셋째, 유기 반사방지막을 이용하여 다른 불순물에 의한 오염 및 이온 주입에 따른 표면 오염을 방지할 수 있다.Third, the organic antireflection film may be used to prevent contamination by other impurities and surface contamination due to ion implantation.
Claims (3)
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| KR100206923B1 (en) * | 1996-07-23 | 1999-07-01 | 구본준 | Method of manufacturing semiconductor device |
| KR100439770B1 (en) * | 1997-12-26 | 2004-09-18 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device to prevent channeling phenomenon caused by ldd ion implantation and reduce resistance of silicide |
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