KR20030051996A - RAID Controller and Parity Operator Method having Disk Cash Memory Controller and Parity Operator Device - Google Patents

Abstract

PURPOSE: An RAID(Redundant Arrays of Inexpensive Disks) controller having a disk cache memory controller and a parity operation device, and a method for operating a parity are provided to respectively optimize the entire stripe write and the partial stripe write in order to remove the unnecessary data transfer on a new parity data calculation process accompanying to the write of new data blocks. CONSTITUTION: The RAID controller includes the parity operation device(220) taking an independent control architecture for each stripe write mode, and a memory control part(210) transferring the data received from a host system to the parity operation device(220) without passing an input/output bus. The memory control part(210) includes a memory controller(211) receiving the data from the host system, a read buffer(215) storing the read data from the host system, and a write buffer(213) storing the write data from the host system. The parity operation device(220) includes an entire stripe write mode controller(223), a partial stripe write mode controller(221), a parity data buffer(225), and an XOR device(227) operating the parity data.

Description

RAID Controller and Parity Operator Method Having Disk Cash Memory Controller and Parity Operator Device

The present invention relates to a RAID (Redundant Arrays of Inexpensive Disks) controller and a parity calculation method, and more particularly, to a disk cache memory controller and a parity computing device capable of calculating parity data along with data transfer. It relates to a RAID controller and a parity calculation method.

In general, a RAID system provides a large amount of storage space to meet a user's needs, employs redundancy techniques to ensure the reliability of the stored data, and to speed up access to the stored data. The purpose is to improve. If some of the disks in the RAID system fail, the data of the failed disk can be recovered without loss due to the redundancy of restoring the image data of the failed disk to the disk defined as the spare disk.

Although such a RAID system is composed of a plurality of disks, it can be recognized as one large disk by a user by RAID management technique. In addition, the RAID controller constituting the RAID system generally includes a disk data cache, and various methods of RAID systems are implemented to enable fast data response of the RAID system. Various methods of implementing a RAID system include RAID level 1, which is a method of ensuring data recovery from disk failure and ensuring reliability by maintaining an identical copy of data on two or more disks, and other commonly used methods. RAID level 3, RAID level 4, RAID level 5, and so on.

An implementation using these three (RAID level 3, RAID level 4, RAID level 5) stores data and parity information on multiple disk drives. A specified number of data blocks is divided into one disk and stored in each disk. Parity data is calculated from these unit data blocks, and the result is stored in the parity data blocks. In this case, a fixed parity disk is designated and used in RAID level 3 and RAID level 4, and a parity data is distributed and stored in all disks in RAID level 5. However, in such RAID level 3, RAID level 4, and RAID level 5 configurations, performance is degraded due to the overhead of calculating and storing parity information in addition to the disk data.

RAID system is largely composed of host system, RAID controller and disk drives. The RAID controller is located between the host system and the disk drive to process data input / output required by the host system as a disk drive. In general, a RAID controller uses a portion of a local memory for storing program data of a RAID controller or a separate memory area mounted on an input / output bus to cache disk data in order to respond quickly to an input / output request of a host system. In the case of the RAID level 3, the RAID level 4, and the RAID level 5, the parity information is stored on the disk in order to guarantee the reliability as described above. An apparatus for performing the XOR operation is used for this purpose.

Meanwhile, a RAID level 5 system performs the following steps for write and read requests of the host system. When the host system requires a write operation, the RAID controller receives data to be stored in the disk drive from the host system, divides the data into a predetermined number of unit data blocks, and stores the divided data in the disk cache. . If there is a stripe to which the data blocks of the address belong to the disk data cache, the data blocks are updated and the parity cache data for the stripe is updated by recalculating the parity data.

If the strip to which the block belongs does not exist, all data blocks and parity blocks constituting the strip are read from the disk, stored in the disk cache, updated with the corresponding data blocks, the parity data is calculated, and the corresponding parity of the parity cache. Update the data. If the host system requires a read operation, the RAID controller examines the disk cache and sends the requested data block to the host system if a block of data at that address exists, and if it does not exist, the disk drive configures all the strips to which it belongs. It reads the blocks, stores them in the disk cache, and sends them to the host system.

In general, there are two ways to store a new data block and a new parity data disk cache computed from the data blocks to handle write requests from the host system. One is a full stripe write and the other is a partial stripe write. The entire stripe write is a case where the entire stripe write occurs. In this case, the entire stripe is written to the disk cache, so that each stripe unit is XORed to calculate new parity data.

Partial stripe write is a case of writing only some data blocks of the stripe. In this case, new parity data is calculated by performing a read-modify-write operation on only data blocks that are changed. do. The read-update-write operation reads (reads) the old data of the block in which the write operation is performed, the old parity data and the new data of the corresponding block of the strip to which the block belongs, and reads the new data of the parity data by XORing the three data blocks. The process of calculating (update) and writing it back to the parity cache area. This requires three reads, one update, and one write operation.

However, in the existing general RAID controllers, even if only partial write writes or full write writes are supported, the entire stripe writes the disk cache memory area during the parity operation during the entire write write process. Since the parity operation is performed by reading this data into the parity data buffer after storing it in the direct memory access (DMA) controller, it requires a lot of direct memory access operations.

In addition, in the case of partial write write, the operation of writing the new data to the disk cache and transferring the data to the parity data buffer after XORing the previous data and parity was performed separately. This process also includes many direct memory access operations. Hassle to ask.

Accordingly, Korean Patent Registration No. 10-0205072 "VRAM Substrate Parity Engine in Disk Array Controller" develops an invention that speeds up parity calculation by using VRAM to overlap read-update-write operations of memory during parity calculation. It is. However, it is cumbersome to use the read-update-write operation unnecessarily even when performing the entire stripe write considering the XOR operation on the partial stripe write.

Accordingly, the present invention has been made to solve the conventional problems as described above, and an object of the present invention is to eliminate unnecessary data transfer in the process of calculating new parity data associated with the writing of new data blocks in a RAID system. An object of the present invention is to provide a parity operation controller optimized for write and partial write writes.

1 is a schematic control block diagram of a RAID system including a RAID controller according to the present invention,

FIG. 2 is a control block diagram specifically illustrating a memory controller and a parity calculating device configuring the RAID controller of FIG. 1;

3 is a block diagram showing the state of the disk cache according to the operation of the entire stripe write controller in the entire stripe write control mode of the present invention.

4 is a block diagram showing the state of the disk cache according to the partial write write controller operation in the partial write write control mode of the present invention.

♣ Explanation of symbols for the main parts of the drawing ♣

50: host system 100: RAID controller

101: central processing unit 102: local memory

103: process bus 104: I / O bus bridge

105: input and output bus 106: host interface controller

107: disk interface controller 108: disk cache memory controller

109: disk cache memory 200: I / O bus interface

210: memory controller 211: memory controller

220: parity calculator 221: partial stripe write mode controller

223: whole stripe write mode controller

120, 130, 140, 150, 160: Disk Drive

The present invention for achieving the above object, in a RAID controller connected to a host system, and configuring a RAID system with the host system, independent of each write write mode according to the mode of the write write operation And a memory controller configured to receive a command from the host system and to transmit data with the parity calculator without receiving an input / output bus.

On the other hand, according to another field of the present invention, the present invention for achieving the above object, relates to a parity calculation method for performing the entire write operation of the RAID controller constituting the RAID system, which is written to the disk cache memory Recording (1) the start address and size information of each stripe unit in the entire stripe write mode controller in the disk cache in which the entire stripe is to be stored; (2) checking the address of the data in progress through the entire stripe write mode controller to determine whether the data block belongs to the stripe; If it is determined that the address of the data belongs to the corresponding stripe, transmitting (3) a block corresponding to the data to a parity data buffer; (4) performing an XOR operation on the data transmitted to the data buffer and existing data existing in the parity data buffer and storing the result back in the parity data buffer; Checking (5) whether all strip units of the stripe have been transmitted; If it is confirmed in the checking step that all the strip units of the corresponding stripe have been transmitted, transmitting the final result to the parity cache region of the disk cache memory through direct memory access (6). It is done.

In addition, according to another aspect of the present invention, the present invention for achieving the above object relates to a parity calculation method for performing a partial write write operation of the RAID controller constituting a RAID system, a new write to the disk cache memory Writing (I), to the partial stripe write mode controller, the start address and size information of each data block in the disk cache in which the data blocks are to be stored; Transmitting (II) the old data from the disk cache to the parity data buffer by direct memory access in the partial write write mode controller; Transferring previous parity data from the parity cache region of the disk cache memory to the parity data buffer through direct memory access, performing an XOR operation, and storing the result back into the parity data buffer (III); Performing a write of a new data block by the central processing unit (IV); (V) checking, by the partial stripe mode write controller, whether a new data block currently being written is a start address and size information stored in the controller and transmitting to the parity data buffer; (VI) performing an XOR operation with an intermediate parity result stored in the parity data buffer and transmitting the result transferred to the data buffer to the parity data buffer; Confirming whether all data blocks in progress of writing have been transmitted (iii); And (i) transmitting the calculated data of the final parity data buffer to the parity cache area of the disk cache memory by direct memory access when it is confirmed that all the data blocks have been transmitted.

Hereinafter, a preferred embodiment of a RAID controller and a parity calculation method according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic control block diagram of a RAID system including a RAID controller according to the present invention. As shown in this figure, the RAID system 10 of the present invention includes a host system 50, a RAID controller 100, and a plurality of disk drives 120, 130, 140, 150, and 160. The host system 50 constituting the RAID system 10 is connected to the RAID controller 100 by an input / output dedicated channel 110 such as a fiber channel or a small computer system interface (SCSI) bus. The RAID controller 100 connected to the host system 50 includes the CPU 101, the local memory 102, the I / O bus bridge 104, the host interface controller 106, the disk interface controller 107, and the disk cache memory. Controller 108, disk cache memory 109. In addition, the RAID controller 100 includes a processor bus 103 connecting the central processing unit 101, the local memory 102, and the input / output bus bridge 104, which are the respective components, the host interface controller 106, and the disk interface. A standard input / output bus 105, such as a PCI bus, for connecting the controller 107 and the disk cache memory controller 108 is provided.

The central processing unit 101 constituting the RAID controller 100 serves to execute a program for configuring, managing, and operating the RAID system 10, and the local memory 102 is executed by the central processing unit 101. Provides space to store program, data and temporary variables. The central processing unit 101 and the local memory 102 mounted on the processor bus 103 are connected to the input / output bus 105 via the input / output bus bridge 104 mounted on the process bus 103. As such, using a standard input / output bus 105, such as a PCI bus, can benefit from the use of many PCI devices currently commercially available.

Meanwhile, the host interface controller 106 mounted on the input / output bus 105 performs a role of receiving a disk input / output request from the host system 50. As described above, the host interface controller 106 receives a disk input / output request transmitted from the host system 50 through an input / output dedicated channel 110 such as a fiber channel or a SCSI bus, so that the RAID controller 100 receives The central processing unit 101 is notified of an interrupt. The central processing unit 101 interprets the transmitted disk I / O request and performs appropriate processing for each request such as read and write.

The disk cache memory controller 108 may include a memory controller 210 and a parity calculator 220 to temporarily store disk data reconstructed by a RAID management technique in the disk cache memory 109. Enables fast parity data operations at various RAID levels. In this case, the parity calculator 220 takes an independent control structure for each write write mode (eg, a partial write write mode and an entire write write mode) according to the mode of the write write operation, and performs parity data operation. Do this. The memory controller 210 directly transmits data received from the host system 50 through the host interface controller 106 to the parity computing device 220 described above.

In addition, the disk interface controller 107 mounted on the input / output bus 105 transmits the input request and output request data to the disk drives 120, 130, 140, 150, and 160 which store data configured by the RAID controller 100.

FIG. 2 is a control block diagram specifically showing a disk cache memory controller 108 constituting the RAID controller of FIG. As shown in FIGS. 1 and 2, the disk cache memory controller 108 includes an input / output bus interface 200, a parity calculator 220, and a memory controller 210 connected to the input / output bus 105. As shown in FIG. 2, the memory controller 210 includes a memory controller 211, a write buffer 213, a read buffer 215, and a write data MUX (Multiplex: 217). The parity calculator 220 may perform a partial stripe write mode controller 221, a full stripe write mode controller 223, a parity data buffer 225, an XOR (Exclusive-OR: 227), and an XOR data MUX 229. It is configured to include. The detailed description of FIG. 2 will be described after schematically describing FIGS. 3 and 4 for convenience of description.

3 is a block diagram showing a state of the disk cache according to the controller operation in the entire stripe write control mode of the present invention, Figure 4 is a state of the disk cache according to the controller operation in the partial stripe write control mode of the present invention. A block diagram is shown. Among these drawings, first of all, FIG. 3 illustrates changes in the contents of the disk cache memory 109 in the entire write mode of the write operation performed by the entire write write mode controller 221 of the disk cache memory controller 108 of FIG. It is shown through. 4 illustrates the operation of the partial stripe write mode performed by the partial stripe write mode controller 223 of the disk cache memory controller 108 of FIG. 2 through the contents of the disk cache memory.

Hereinafter, operations of the memory controller 210 and the parity calculator 220 of FIG. 2 will be described in more detail with reference to FIGS. 3 and 4.

First, the overall stripe mode controller 221 will be described with reference to FIG. 3.

The entire stripe write is a case where the entire stripe is written to the disk cache memory 109 as described above. The data blocks of the stripe coming in through the I / O bus interface 200 are written to the disk cache memory 109 by the memory controller 211 through the write buffer 213. The data blocks input in this process are transferred to the write buffer 213 and transferred to the input of the XOR device 227 via the XOR data MUX 229. The XOR device 227 also receives as input the data provided to the parity data buffer 225 from the entire stripe mode controller 223. These inputs are computed through the XOR device 227 to produce parity as an intermediate result of the parity operation. Data buffer 225 is provided. When all write operations are performed, the parity data buffer 225 stores final parity data, that is, parity data of the stripe.

Each of these processes will be described with reference to FIG. 3.

Firstly, in step S301, the first stripe unit of the stripe arrives. The stripe unit D00 is written to the first stripe unit position of the stripe 0 area of the disk cache and simultaneously written to the parity data buffer 225 in step S301. The second step S302 indicates the arrival of the second stripe unit. The second stripe unit D01 is written to the disk cache and transferred to the parity data buffer 225 at step S301. After the X00 operation with D00 contained in the), the operation result is stored in the parity data buffer 225.

Next, the third step S303 is the content of the third stripe unit D02, and S304 is a step in which the final stripe unit D03 is written to the disk cache and passed to the parity data buffer 225 to generate final parity data. appear. As a result, all data blocks of the stripe are written to the disk cache, and at the same time, parity data can be calculated using Equation 1 below.

P0 = (D00) xor (D01) xor (D02) xor (D03) [Equation 1]

Finally, S305, which is the last step of the entire stripe write process, indicates a process of writing the final parity data in the parity data buffer 225 to the parity cache through direct memory access (DMA).

On the other hand, in order to perform the above-described processes, before starting the entire stripe write, the start address of each stripe unit written in the disk cache memory 109 and the size of each stripe unit are set in the entire stripe write mode. Stored in the controller 221. In this case, the entire stripe write mode controller 221 may be provided with a separate storage unit for storing the start address of the unit and the size of the unit. The entire stripe write mode controller 221 further uses this information to identify whether the data currently being written to the disk cache memory 109 is an entire stripe write data block.

Next, a partial stripe writing process through the partial stripe mode controller 221 will be described with reference to FIG. 4. As shown in FIG. 4, the partial stripe write process will be described as an example in which a write occurs in a new D02 for a strip consisting of D00, D01, D02, D03, and P0.

First, S401 indicates a situation in which a strip corresponding to D02 already exists in the disk cache and the parity cache, and writes occur in the area D02 where the stripe already exists. Then, the central processing unit 101 of FIG. 1 does not immediately write D02. Accordingly, the central processing unit 101 transmits the D02 write data to the data cache after passing through the step S402 and the step S403. In step S402, data existing in the area D02 of the current disk cache (old D02) is transmitted to the parity data buffer 225 through direct memory access (DMA). In step S403, the previous parity data P0 (old) of the parity cache is transferred. P0) is transmitted to the parity data buffer 225 to perform an XOR operation with old D02 (ie, (old DO2) xor (old PO)). After the step S403 is performed, the central processing unit 101 writes a new D02 (new DO2) to the disk cache. After this step, in step S404, (new D02) is written to the disk cache and transferred to the parity data buffer 225, and the result of performing the XOR operation on the result calculated in step S403, that is, the final parity data is generated. The situation is shown by the following [Formula 2].

(new P0) = (old D02) xor (old P0) xor (new D02) [Equation 2]

Finally, S405 represents a step in which new parity data (new P0) is stored in the parity cache through direct memory access. In the partial stripe write, unlike the entire stripe write, the partial stripe write mode controller 221 only needs to transfer the data to the parity data buffer 225 when new data (new D02) is written to the disk cache. old D02, old P0 Two direct memory access operations and one identification process. Of course, at this time, a storage unit for storing the starting address and data size of the new data may be provided for one identification process, and the data is stored in the storage unit.

As described above, according to the RAID controller and the parity operation control method according to the present invention, eliminating unnecessary data transfer in the process of calculating the new parity data accompanying the writing of new data blocks in the RAID system, and eliminates the entire stripe write and partial stripe. By providing a parity operation controller optimized for each write, the number of input / output operations required for parity operations can be minimized to improve the performance of the entire RAID system.

In addition, according to the RAID controller and the parity calculation method of the present invention, in the case of the write write, the parity calculation device identifies data transmitted to the disk cache memory area through the I / O bus in the process of writing the entire write to the disk cache memory. The data is stored in the disk cache memory and at the same time, it is stored as a parity data buffer through the XOR operation device, so that there is no need to perform XOR operation separately through direct memory access.

Claims (14)

A RAID controller connected to a host system and configuring a RAID system with the host system, A parity computing device that takes an independent control structure for each stripe write mode according to the mode of the stripe write operation, A memory controller which receives data from the host system and transmits the provided data to the parity computing device without passing through the input / output bus; RAID controller comprising a. The method of claim 1, wherein the memory control unit, A memory controller connected to the input / output bus to receive data from the host system, a read buffer connected to the memory controller to store read data provided from the host system, and connected to the memory controller and provided from the host system RAID controller comprising a write buffer for storing the write data. The apparatus of claim 1, wherein the parity calculating device is An entire stripe write mode controller controlling a whole stripe write, which is a method of storing new parity data connected to the memory controller, a partial stripe write mode controller controlling a partial stripe write, and storing the parity data And a parity data buffer and an exclusive OR (XOR) device for calculating the parity data. The method of claim 3, wherein the entire stripe write mode controller, And a storage unit which stores a start address and size information of each stripe unit. The method of claim 3, wherein the entire stripe write mode controller, When writing to the entire stripe occurs, while each stripe unit is written to the disk cache memory, it is determined whether to transfer to the parity data buffer by checking the start address and size information of the stripe unit. RAID controller. The method of claim 3, wherein the entire stripe write mode controller, RAID is characterized by performing a direct memory access function for transferring the final parity data stored in the parity data buffer and calculated for the transmitted stripe in the process of writing to the entire stripe to the disk cache memory. Controller. The method of claim 3, wherein the partial stripe write mode controller, And a storage unit for storing the start address and the size information of the stripe units to which new data blocks to be written to the disk cache memory belong when a write occurs to only a portion of the stripe unit. The method of claim 3, wherein the partial stripe write mode controller, In the process of writing to the partial stripe, a direct memory access function for transferring previous data and previous parity from the disk cache memory to the parity data buffer, and a direct transfer of the calculated final parity data to the disk cache memory. RAID controller characterized in that performs a memory access function. The method of claim 3, wherein the partial stripe write mode controller, When a write occurs only in some units of the stripe, it is determined whether to transfer to the parity data buffer by checking start addresses and size information of stripe units to which new data blocks to be written to the disk cache memory belong. RAID controller. The method of claim 3, wherein the parity data buffer is And a parity operation result of data blocks of each stripe unit. In the parity calculation method for performing the entire write write operation of the RAID controller constituting the RAID system, Writing (1) the start address and size information of each stripe unit in the entire stripe write mode controller in the disk cache in which the entire stripe written to the disk cache memory will be stored; (2) checking the address of the data in progress through the entire stripe write mode controller to determine whether the data block belongs to the stripe; If it is determined that the address of the data belongs to the corresponding stripe, transmitting (3) a block corresponding to the data to a parity data buffer; (4) performing an XOR operation on the data transmitted to the data buffer and the data present in the parity data buffer and storing the result back in the parity data buffer; Checking (5) whether all strip units of the stripe have been transmitted; If it is confirmed in step (5) that all of the strip units of the corresponding strip have been transferred, transmitting (6) the final result to the parity cache region of the disk cache memory via direct memory access; Parity calculation method, characterized in that. The method of claim 11, In the step (5), repeating the step (3) and step (4) until the mode stripe units are transmitted. A parity calculation method for performing a partial write write operation of a RAID controller constituting a RAID system, Writing (I), to the partial stripe write mode controller, the start address and size information of each data block in the disk cache in which new data blocks written to the disk cache memory are to be stored; Transmitting (II) the old data from the disk cache to the parity data buffer by direct memory access in the partial write write mode controller; Transferring previous parity data from the parity cache region of the disk cache memory to the parity data buffer through direct memory access, performing an XOR operation, and storing the result back into the parity data buffer (III); Performing a write of a new data block by the central processing unit (IV); (V) checking, by the partial stripe mode write controller, whether a new data block currently being written is a start address and size information stored in the controller and transmitting to the parity data buffer; (VI) performing an XOR operation with an intermediate parity result stored in the parity data buffer and storing the result in the parity data buffer after transmitting the result transmitted to the data parity buffer; Confirming whether all data blocks in which writing is in progress have been transmitted; And (i) transferring the calculated data of the final parity data buffer to the parity cache region of the disk cache memory when direct data access is confirmed when all the data blocks have been transmitted. The method of claim 13, And said step (iii) repeats steps (V) and (VI) until all of the data blocks in writing are transmitted.