KR20030049205A - Semiconductor memory device using commomn bus in normal mode and test mode - Google Patents

Abstract

PURPOSE: A semiconductor memory device using a common bus at a test mode and a normal mode is provided to reduce an area of a chip by sharing a wire for a test mode. CONSTITUTION: A semiconductor memory device includes the first bus(300a), the second bus(500a), a selection portion(700), a test signal storage portion(900), and a signal processing portion(600). The first bus is used for transmitting a signal of a normal mode. The second bus is used for transmitting a signal of a test mode. The selection portion outputs selectively one of the signals of the normal mode and the test mode to the third bus(800) according to a control signal. A test signal storage portion receives a signal of the third bus in response to the control signal, latches the received signal, and outputs the latched signal. A signal processing portion is connected to the third bus in order to process the signal of the normal mode.

Description

Semiconductor memory device using commomn bus in normal mode and test mode}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a wiring of signals required for a test operation in testing a memory device in a DRAM.

The semiconductor memory device refers to a device capable of reading and writing data by implementing a transistor and a passive device on a silicon wafer. Among the semiconductor memory devices, a DRAM memory semiconductor is the most widely used technology.

The memory semiconductor is largely composed of a cell array area for storing data and various control logic providing functions for reading and writing data to the cell array.

How small a semiconductor memory chip is formed is directly related to productivity and profits, and microfabrication technology is the center of semiconductor memory manufacturing technology. In addition to the microfabrication technology, the design technology for designing the chip is also very important for manufacturing a small area chip.

In order to reduce the area of the semiconductor chip, there is a method of reducing the area of the memory cell or reducing the remaining areas except the memory cell. In general, the ratio of the memory cell array to the total chip area is called cell efficiency.

The high cell efficiency means that the area occupied by devices other than memory cells is small, which means high productivity. If the cost of processing a single silicon wafer is fixed, the number of chips that can be calculated from a single wafer increases when the chip area is small and the cell efficiency is high.

The minimum area of a memory cell determines the area of the memory cell array. The larger the cell area, the larger the chip area will be if the array of cells is arranged to form a large amount of storage capacity. However, since the core of semiconductor manufacturing technology is cell manufacturing technology, an area for constructing a cell is an essential and inevitable space. However, if a logic circuit and an interface device having the same function can be configured in a small area except for the memory cell area, the space utilization efficiency will be increased.

FIG. 1 is a diagram illustrating a configuration of such a general DRAM memory device, and a conventional technology will be described with reference to the drawing.

The semiconductor memory device may include a memory cell 100 for storing information, a data amplifier 200 for amplifying the stored data to read and write data stored in the cell, an input / output logic 600, and a data bus for transmitting the data to the input / output logic ( 300, a logic circuit arrangement (not shown), a power wiring (not shown), a test signal decoder 400 for receiving a test code and outputting a test signal, and a test bus 500 for transmitting the test signal to all regions of the chip. ) And the like.

The number of data buses 300 that transmit data among chip components other than the memory cell 100 serves as an important factor that governs the area of the chip.

A plane of a general semiconductor memory device may have a square shape and may have a square or rectangular shape. The length of the long axis and the short axis of the rectangle determine the area of the memory chip. In the rectangular semiconductor memory chip, all wiring is evenly arranged. no.

As shown in Fig. 2, in some regions there is a bottleneck, particularly where a large number of wires gather, which usually happens at the center of the chip. The center of the chip is the central point of the signals in which almost all the signals are collected, and the number of wires formed in the center of the chip determines the length of one axis that governs the chip area. In other words, it can be seen that increasing the number of buses is a burden on the shorter length of the chip.

Therefore, in order to reduce the area of the chip by reducing the length of one axis of the chip, it is necessary to reduce the pitch of the wiring or give up some of the wiring. If the pitch of the wiring is reduced, the delay time of the signal increases, and it cannot be reduced. Also, giving up the wiring cannot be done because it is the result of giving up a certain function.

Looking at the type of wiring used in the semiconductor memory device as follows. The amplified data in the memory cell array is transferred to the buffer of the input / output logic via the internal data bus. The necessary wiring is the data bus. In addition, an address for specifying where to store or write data in a cell array also defines a group of buses. This is called the address bus. Such data buses or address buses are connected across the chip.

In addition, small groups of signals that perform special functions may serve as some local connections within the chip, but they are more likely to traverse the entire section of the chip, such as the address bus or data bus.

The operation of a semiconductor memory device can be divided into two operations, a normal operation and a test operation. The normal operation means a read operation or a write operation that is normally performed when a memory device is mounted in a system.

In the case of a DRAM memory device, in order to perform a read or write operation, a part of data held in a memory cell array of a region is selected and amplified by a row address, and a column address is applied to output the corresponding data. The process of input is repeated irregularly.

In addition to the normal operation described above, the test operation means that an operation for evaluating the operating state of the memory chip or logic specially configured to increase the productivity of the memory chip is operated. Test all cases that control the operation of the internal supply voltage generator, provide a means to access redundant cells, reduce the test time by compressing the entire data bus, or have special control signals for testing purposes only It is called an action.

This test operation provides a number of convenient features. Any activity done to increase the productivity of semiconductor devices or to reduce production costs will eventually lead to the competitiveness of the enterprise. However, from the standpoint of chip design, the test behavior requires some sacrifice.

Designing to reduce the area of the chip is also one method of cost reduction, and as the number of necessary wirings increases as the test operation method is retained, this is one cause of the increase in the chip area.

In the case of a memory chip having a rectangular planar shape, pads are generally arranged in the center of the chip, and memory cell arrays are disposed in each quadrant of the chip, and a global bus is arranged in the same direction as the center pad array of the chip. .

The width of the bus thus arranged serves as an element that determines the length of one axis of the chip. If the number of wires added for the test function increases, the area of the chip increases by the number of wires increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an invention that solves the problem of increasing the chip area by sharing the wiring used in the test mode with another wiring in the semiconductor memory device.

1 is a view showing the configuration of a semiconductor memory device according to the prior art;

2 illustrates a bottleneck of signals in a memory device;

3 is a diagram illustrating a configuration of a memory device according to an embodiment of the present invention;

4 is a diagram showing the configuration of a test signal decoder;

5 is a diagram showing the configuration of a test register;

* Explanation of symbols for main parts of drawings *

100: memory cell 200: data amplifier

300a: data bus 400: test signal decoder

500a: test signal bus 600: input / output logic

700: Multiplexer 800: MIO Bus

900: test signal register

The present invention for achieving the above object, the first bus for transmitting a signal used in the normal operation mode; A second bus for transmitting a signal for use in a test mode of operation; Selecting means for inputting the first bus and the second bus and outputting a signal used in the normal operation mode or a signal used in the test operation mode to a third bus according to a control signal; Test signal storage means for receiving and latching a signal of the third bus in response to the control signal; And means for processing signals used in said normal mode connected to said third bus.

In order to solve the problems of the prior art, the present invention proposes a method of using some wiring in common. In particular, it is a technical gist of the present invention to provide a temporary path so that signals used in the test mode can be transmitted by using some buses used in the normal operation mode. In other words, it may be referred to as a multiplexed bus structure.

In one embodiment according to the present invention, if the number of test signals required in the test mode is eight, eight data buses used in the normal mode are used to transmit the eight test signals. The eight data buses borrowed in normal mode are not a problem at all because they are not used in test mode. The bus signals required in test mode are only required in test mode, so they can be returned to their original function when operating in normal mode.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

In one embodiment according to the present invention, the data bus is shared with the test signal bus, but in addition to the data bus, the address bus may be shared with the test signal bus. 3 is a view showing an embodiment according to the present invention with reference to this description as follows.

According to an embodiment of the present invention, a semiconductor memory device includes a memory cell 100 and a data amplifier 200 for reading or writing data to a memory cell, a control logic for a read operation or a write operation (not shown in FIG. 3), A data bus 300a carrying data from the data amplifier 200 to the multiplexer, a test signal decoder 400 receiving a test code and outputting a test signal, a multiplexer for a test signal output from the test signal decoder 400, and Multiplexer 700, bottleneck, which outputs any one of data and a test signal according to a control signal by inputting a test signal bus 500a, a data bus 300a and a test signal bus 500a to be transferred to one area of the chip MIO bus 800 passing through and delivering the output of the multiplexer 700 to the other side of the chip, if the output of the multiplexer is a data signal A data input / output circuit 600 for receiving a data signal and connecting it to the outside, and a test signal register 900 for receiving the output of the multiplexer when the output of the multiplexer is a test signal.

In one embodiment according to the present invention, the data bus 300a refers to a bus used to transfer data from the data amplifier 200 to the multiplexer 700 and the test signal bus 500a refers to the multiplexer at the test signal decoder 400. A bus is used to transmit a test signal to 700 or to transmit a test signal to one region of the chip without passing through the center portion of the chip.

The MIO bus 800, which is the output of the multiplexer 700, is a bus used to transmit test signals or data through the center of the chip, which is the bottleneck of signals, to the other area of the chip.

FIG. 4 is a diagram illustrating a test signal decoder 400 and a multiplexer 700 on the assumption that the number of test signals is eight.

The test signal decoder 400 is configured based on a NAND gate having three test codes c0, c1, and c2 and an inverter which receives and inverts the output of the NAND gate as a basic unit. , c1, c2 are decoded to generate eight test signals of t0 to t7.

Eight test signals are used to test one area of the chip as a signal representing each test mode of operation, or to input the multiplexer to test the other area of the chip opposite the bottleneck of the signals.

In response to the test mode control signal Testmode, the multiplexer 700 transmits the first fast transistor 710 and the test mode control signal (t), which transmits the output signal t (n) of the test signal decoder to mio (m), the MIO bus. And a second fast transistor 720 which transmits a signal of the data bus io (m) to the mio (m) in response to the test mode. The first fast transistor and the second fast transistor are selective according to a test mode control signal. It is configured to be enabled.

FIG. 5 is a diagram illustrating the configuration of the test signal register 900. The configuration and operation of the test signal register will be described below with reference to the drawing.

The test signal register 900 is located on the opposite side of the multiplexer, that is, on the opposite side of the multiplexer 700 with a bottleneck of signals therebetween. The test signal register 900 includes an input unit 910 for receiving the MIO bus 800, which is the output of the multiplexer 700, and a test mode control signal (testmode), and a latch unit 920 that latches the output of the input unit 910. ), A driver 930 for driving the output of the latch unit 920 and a test reset signal input unit 940 for receiving a test reset signal.

The input unit 910 includes a 911 NAND gate receiving the MIO bus 800 and a test mode control signal (testmode), which are outputs of the multiplexer 700, and a 912 inverter and an 912 NAND inverting output of the 911 NAND gate. 912 is composed of an output of the inverter and a test mode control signal (testmode) NAND 913 NAND gate for outputting to the 914 inverter, the latch unit 920 is the 921 inverter and 921 receiving the output of the 914 inverter And a 922 NAND gate that receives an output of the inverter and an inverted test reset signal and feeds back the 921 inverter.

The driving unit 930 includes two inverters 931 and 932 connected in series to receive and output the output of the 921 inverter. The test reset signal input unit receives the test reset signal and inverts the output to the 922 NAND gate. It is composed of an inverter.

The test signal register is latched by receiving Mio (m) according to the test mode control signal (Testmode). If the test reset signal (testrst) is at the 'low' level, the test signal register is kept in the latched state. When the test reset signal testrst is at the 'high' level, it can be seen that the outputs of the test signal register 900, tt0 to tt7, become 'low' levels to enter the inactive state.

When the test reset signal testrst is 'low' level and the test mode control signal testmode is 'high' level, the test signals t0 to t7 input to the test signal register 900 shown in FIG. 5 are tested. Each of the output signals tt0 to tt7 of the signal register 900 is generated. The test signals t0 to t7 and the outputs of the test signal register 900 tt0 to tt7 are the same signals and the test reset signal testrst is 'high'. The test signals will remain in that state unless they are activated to the level to reset the test signals.

The operation of the semiconductor memory device according to the exemplary embodiment of the present invention configured as described above is as follows.

In the normal operation mode, the operation mode reads data stored in the memory cell or writes data in the memory cell. The test mode control signal testmode becomes 'low' level, indicating the normal operation mode.

Data stored in the memory cell is amplified by the data amplifier 200 and loaded onto the data bus and input to the multiplexer. When the test mode control signal testmode is 'low' level as a normal operation mode, referring to the structure of the multiplexer 400 shown in FIG. 4, since the first pass transistor is not conducting, the input test signals t0 to t7 ) Cannot be the output of the multiplexer 400 and the data signal passes through the second pass transistor and is loaded on the MIO bus which is the output of the multiplexer.

The MIO bus passes through the center of the chip and is connected to the input / output logic, which normally operates to read or write data to the memory cells.

The test mode control signal (testmode) is 'high' level to indicate that the operation of the memory device is a test mode as follows.

The test signal decoder 400 receiving the test codes c0, c1, and c2 decodes the three test codes, generates eight test signals t0 to t7, and outputs them to the test signal bus 500a. The test signal bus 500a is transferred to the multiplexer 700 or to the opposite side of the region where the test signal register 900 is located with respect to the center of the chip to perform a test operation.

When the test signals t0 to t7 input to the multiplexer 700 refer to the structure of the multiplexer shown in FIG. 4, since the test mode control signal testmode is 'high' level, the second pass transistor is turned on so that the test signal t0 is performed. T7) is loaded on the MIO bus and the data signal is not output from the multiplexer because the first pass transistor is not conducted.

The test signals t0 to t7 which are loaded on the MIO bus 800 and pass through the center portion of the chip, which are the bottlenecks of the signals, are input to the test signal register 900. The input test signals t0 to t7 are thus input to the test signal register. The tt0 to tt7 signals, which are outputs of the tt0 to tt7 signals, are generated and operate differently according to the test reset signal testrst and the test mode control signal testmode.

According to an embodiment of the present invention, the MIO bus 800, which is an output of the multiplexer 700, transmits data information in a normal mode and a test signal in a test mode. In other words, in the section passing through the bottleneck of the signals to prevent the increase of the chip area by using the data bus in common without using a test signal bus for transmitting the test signal separately.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

The capacity of semiconductor memory devices is rapidly expanding, and thus, a phenomenon in which logics representing various test-related functions are added in order to reduce test costs and improve productivity of a chip is inevitable. However, this causes a problem of increasing the area of the chip. If a memory device that has to implement 50 test operations applies the idea of the present invention, a significant amount of axis length will be reduced, which leads to a reduction in the overall chip area. Therefore, when the present invention is applied, the number of net dies calculated from one wafer is also increased, thereby reducing production costs and improving productivity.

Claims (13)

A first bus transmitting a signal used in a normal operation mode; A second bus for transmitting a signal for use in a test mode of operation; Selecting means for inputting the first bus and the second bus and outputting a signal used in the normal operation mode or a signal used in the test operation mode to a third bus according to a control signal; Test signal storage means for receiving and latching a signal of the third bus in response to the control signal; And Means for processing signals used in said normal mode connected to said third bus Semiconductor memory device configured to include. The method of claim 1, And the selecting means and the test signal storing means are located in regions opposite to each other with respect to a central portion of the memory device chip. The method of claim 2, And the first bus is a data bus. The method of claim 2, And the first bus is an address bus. The method of claim 1, The means for selecting A first fast transistor transferring a signal of the second bus to the third bus in response to a test mode control signal; And A second fast transistor transferring the signal of the first bus to the third bus in response to a test mode control signal; A semiconductor memory device comprising a. The method of claim 1, The storage means An input unit configured to receive a third bus and a test mode control signal output from the selection unit; A latch unit for latching an output of the input unit; A driving unit driving an output of the latch unit; And Test reset signal input unit for receiving a test reset signal A semiconductor memory device, characterized in that comprising a. The method of claim 6, A first NAND gate configured to receive the third bus and a test mode control signal; A first inverter for inverting and outputting an output of the first NAND gate; A second NAND gate NAND outputting an output of the first inverter and a test mode control signal; and A second inverter for inverting and outputting the output of the second NAND gate A semiconductor memory device comprising a. The method of claim 6, The latch portion A third inverter receiving an output of the input unit; A third NAND gate that receives a test reset signal inverted from the output of the third inverter and feeds back to the third inverter A semiconductor memory device comprising a. The method of claim 6, The driving unit A fourth inverter receiving the output of the third inverter, which is the output of the latch unit, and inverting the output; A fifth inverter that inverts and outputs the output of the fourth inverter A semiconductor memory device comprising a. The method of claim 6, And a test reset signal input unit configured to receive the test reset signal from the sixth inverter. A memory device having a plurality of memory cells and a data amplifier for amplifying data stored in the memory cells, A data bus for transmitting the data signal amplified by the data amplifier to a multiplexer; A test signal decoder which generates a test signal and transmits the test signal to one area around the center of the memory device or the test signal to a multiplexer; A multiplexer located in a central region of the memory device, the multiplexer being configured to input the data signal and the test signal and output the test signal or the data signal according to a control signal; A test signal register positioned in an area opposite to an area where the test signal decoder is located around a central portion of a memory device, and receiving and storing the test signal which is an output of the multiplexer; And Input / output means for receiving the data signal which is the output of the multiplexer and outputting it to the outside Semiconductor memory device configured to include. The method of claim 11, And the output of the multiplexer is transmitted to the test signal register and the input / output means through a single bus. The method of claim 11, And the test signal register receives a signal for resetting a stored test signal.