KR20030048631A - Crypto Processing apparatus for Elliptic Curve Cryptosystem - Google Patents

Abstract

PURPOSE: An apparatus for encoding an elliptic curve is provided to enhance the security and the performance of electronic commercial transaction, electronic cash, identification and key management of an user, and an approval process system by using various elliptic curve protocols. CONSTITUTION: An elliptic curve encoding apparatus includes a register file portion(200), an elliptic curve processor calculation portion(400), an order comparator portion(500), an NAF(Non Adjacent Format) converter portion(100), and an elliptic curve processor control portion(300). The register file portion stores input data and output data to encode an elliptic curve. The elliptic curve processor calculation portion performs a calculation operation for the elliptic curve by using the stored data of the register file portion. The order comparator portion searches and compares the orders necessary for the calculation operation. The NAF converter portion supports the scalar multiplication calculation. The elliptic curve processor control portion generates a control signal to control a calculation operation mode of the elliptic curve processor.

Description

Crypto Processing apparatus for Elliptic Curve Cryptosystem

The present invention relates to an elliptic curve encryption device.

The cryptosystem is largely divided into a secret key cryptosystem and a public key cryptosystem. The secret key cryptosystem has a secret key shared by a secret channel, so that the sender and receiver perform encryption and decryption by the same key in a manner of mutually encrypted communication with each other, thus making it difficult to securely transmit and store the key. The public key cryptographic algorithm solves such a problem of key distribution. In public key cryptography, a cipher system having a different encryption key and a decryption key receives a public key of a counterpart who wants encryption communication, encrypts it, and transmits it. The receiving side can decrypt the cipher text with its own private key. The public key cryptographic algorithm solves the problem of key distribution and provides the function of simultaneous digital signature. However, the public key cryptography algorithm has a disadvantage in that the computation amount of encryption and decryption is very large. Therefore, the public key cryptography algorithm is used for applications requiring secret key distribution, digital signature, or authentication rather than data encryption.

A representative public key cryptosystem is RSA. RSA is the most commonly used public key cryptosystem, but has a disadvantage of using a large bit of key for sufficient security. Larger key lengths mean more computation time and more hardware.

The elliptic curve cryptographic system is a public key cryptographic system proposed by N. Koblitz and V. Miller in 1985 and is based on the safety of discrete algebraic difficulties on elliptic curves. The discrete algebra problem on the elliptic curve is known to be more difficult than the prime factorization problem, which is the basis of the safety of the RSA public key cryptosystem. This fact is closely related to the key length used in the cryptographic system. The higher the security of the cryptographic system, the shorter the key value is, the more secure it is. That is, the elliptic curve cryptographic system guarantees an equivalent security even if the key is much shorter than the key length used in the RSA public key cryptosystem. In fact, an elliptic curve cryptosystem with a key length of 160 bits provides the same security as an RSA cryptosystem with 1024 bits. However, elliptic curve cryptosystems cannot be used as real-time encryption / decryption protocols due to the large amount of computation, and mainly used protocols such as Diffe-Hellman, EC Elgamal, ECDSA for key exchange and secret message encryption / decryption, digital signature and authentication. do. Each protocol uses scalar multiplication (nP) operations of elliptic curves in common, and a hardware device is required to implement a fast cryptographic system. In addition, slightly different elliptic curve operations are required for each protocol. Hardware devices that can support these operations improve overall cryptographic system performance.

In this way, the elliptic curve cryptographic system is based on the safety of the discrete algebra on the elliptic curve, which ensures high security with short key lengths. It means less, but the elliptic curve calculation itself is complicated, which makes it difficult to implement the hardware. In addition, the elliptic curve protocols using the elliptic curve cryptographic system have a slightly different operation required for each protocol. Therefore, an elliptic curve cryptographic apparatus capable of supporting various operations required by these protocols is required to implement a more efficient elliptic curve cryptographic system. .

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and an object thereof is to provide an elliptic curve encryption device that can easily implement various elliptic curve protocols.

1 is a block diagram of an elliptic curve encryption apparatus according to the present invention;

2 is a block diagram illustrating a register file unit of FIG. 1;

3 is a block diagram illustrating an elliptic curve processor of FIG. 1;

4 is a block diagram illustrating an order comparison unit of FIG. 1.

FIG. 5 is a block diagram illustrating a NAF converter of FIG. 1. FIG.

* Explanation of symbols for the main parts of the drawings

10: I / O data bus 100: NAF converter

200: register file unit 300: elliptic curve processor control unit

400: elliptic curve processor operation unit 500: order comparison unit

According to one aspect of the elliptic curve encryption device according to the present invention for achieving the above object, a register file portion for storing the input data and output data for the elliptic curve encryption, and a plurality of elliptic curves for the data stored in the register file portion An elliptic curve processor calculating unit performing an operation, an order comparing unit performing an order search and comparison necessary for the operation of the elliptic curve processor calculating unit, an NAF transform unit for supporting a scalar multiplication operation in the elliptic curve processor calculating unit, and an elliptic curve And an elliptic curve processor controller for generating a control signal for controlling the operation mode of the processor.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of an elliptic curve encryption device according to an embodiment of the present invention.

As shown in FIG. 1, an elliptic curve encryption apparatus according to the present invention includes an input / output data bus 10, a NAF converter 100 for efficient scalar multiplication operation, and a register for storing input / output values of an elliptic curve operation. The file unit 200, an elliptic curve processor control unit 300 for controlling each register and an operator, an elliptic curve processor calculating unit 400 for performing various operations of an elliptic curve, and an order search required for an elliptic curve operation. An order comparison unit 500 for comparison is provided.

Referring to the operation of the elliptic curve encryption apparatus of FIG. 1, when an input of an elliptic curve operation is input to the register file unit 200 and a value is input to a control register of the elliptic curve processor control unit 300, the operation is started. The elliptic curve processor control unit 300 may perform a scalar multiplication operation, an elliptic curve coordinate addition operation, a polynomial multiplication operation, and the like using the elliptic curve processor operation unit 400, the order comparison unit 500, and the NAF conversion unit 100 according to an operation mode. Controls an operation to perform a polynomial inverse multiplication operation and a polynomial inverse function operation. When the operation is completed, the final result is stored in the register file unit 200 to indicate that the operation is completed.

FIG. 2 is a diagram illustrating an embodiment of a register file unit shown in FIG. 1.

As shown in FIG. 2, the register file unit 200 according to the present invention includes an N register 202 for storing a scalar multiplication constant, an N multiplexer 201, and an N register 201 for determining an input thereof. Lr block 203 for rotating the value of a bit left, X1 register 204 and Y1 register 205 for storing the input value of the elliptic curve base point or operation, and another coordinate of the elliptic curve. An X2 register 207 and a Y2 register 209 for storing the inputs or outputs of the X2, and an X2 multiplexer 206 and a Y2 multiplexer 208 for determining the input of these registers.

Referring to the operation of each block of FIG. 2, the N register 202 outputs only the upper 4 bits as a register that stores a scalar multiplication constant. The N multiplexer 201 controls the input from the system bus 10 to be the input of the N register 202 when the initial constant value is input. During the scalar multiplication operation, the output value of the N register 202 again becomes the N register ( Control to be the input of 202). At this time, the output value of the N register 202 is rotated one bit to the left. This operation is done via Lr block 203, which is implemented with simple bit mapping. X1 register 204 and Y1 register 205 are registers for storing a base point for a scalar multiplication operation or for storing a coordinate value for an elliptic curve coordinate addition operation. The X1 register 204 is also used as an input register for other polynomial operations. The X2 register 207 and the Y2 register 209 are used to store the intermediate result and the final output value during the scalar multiplication operation, and to store the input and final output of the other coordinates during the elliptic curve coordinate addition operation. Is the register used. The X2 register 207 is used as an input or output register in other polynomial operations. X2 multiplexer 206 and Y2 multiplexer 208 determine each register input in accordance with operation. The elliptic curve encryption apparatus according to the present invention has a total of five operation modes, the operation of the cryptographic processor and the input / output of the register file according to each mode are as follows. Each operation mode depends on a control register allocation value of the elliptic curve processor control unit 300.

Mode 1: scalar multiplication mode

Behavior: Q = nP (n: random constant, P: elliptic curve base)

Input: n-> N register 202, P (x)-> X1 register 204, P (y)-> Y1 register (205)

Output: Q (x)-> X2, Q (y)-> Y2

Mode 2: Elliptic Curve Coordinate Addition

Behavior: Q = P + G (P, G: any point on the elliptic curve)

Input: P (x)-> X1 register (204), P (y)-> Y1 register (205),

G (x)-> X2 register (207), G (y)-> Y2 register (209)

Output: Q (x)-> X2 register (207), Q (y)-> Y2 register (209)

Mode 3: Polynomial Multiplication

Behavior: c (x) = a (x) * b (x)

Input: a (x)-> X1 register (104), b (x)-> X2 register (207)

Output: c (x)-> X2 register (207)

Mode 4: Polynomial Inverse Multiplication

Behavior: c (x) = a (x) / b (x)

Input: b (x)-> X1 register (204), a (x)-> X2 register (207)

Output: c (x)-> X2 register (207)

Mode 5: Polynomial Inverse Function Operation

Behavior: c (x) = a (x) -1

Input: a (x)-> X1 register (204)

Output: c (x)-> X2 register (207)

3 is a configuration diagram of an elliptic curve processor operation unit 400 shown in FIG. 1.

As shown in FIG. 3, the elliptic curve processor operation unit 400 according to the present invention includes four registers, such as an F register 402, a G register 405, a C register 408, and a B register 410. F multiplexer 401, G multiplexer 404, C multiplexer 407, B multiplexer 409, ADD0 413, ADD1 417, ADD2 for polynomial addition operations to control their input. (419) operation block and multiplexers 415, 416, 418, 420 for controlling the input of the operation block, MUL 414 operation block for bit product, Rs block 403 for one bit right shift and left shift ) And Ls block 406. Internally, a minimum polynomial value 411 and an A parameter 412 which is an elliptic curve coefficient are stored. These two values may be initially input from the system bus.

The elliptic curve processor operator of FIG. 3 may perform operations such as polynomial addition operations, polynomial multiplication operations, polynomial inverse multiplication operations, and polynomial inverse function operations using respective registers and operators. In addition, an elliptic curve addition operation can be performed by combining these various operations.

The polynomial addition operation in the elliptic curve processor operation unit 400 according to the present invention is performed using the F register 402, the G register 405, and the ADD0 413 operator, and the operation result is the F register 402 or the G operator. Stored in register 405. It is also possible to perform calculations using the C register 408, B register 410 and the ADD1 417 operator, and store the result in the C register 408 or the B register 410 again.

The polynomial multiplication operation in the elliptic curve processor operator according to the present invention is performed in units of bits. The polynomial multiplication operation of the G register 405 value and the C register 408 value is output to the B register 410. Looking at the operation in detail, first, a value for polynomial multiplication operation is stored in the G register 405 and the C register 408, and the B register 410 is initialized to '0'. Thereafter, after performing the bit multiplication operation using the MUL 214 operator on the last bit value of the G register 205 and the value of the C register 208, the result of the multiplication operation and the value of the B register 410 are ADD1 (417). Perform a polynomial addition operation using the arithmetic operator. The result of ADD1 417 is a minimum polynomial value 411 and again a polynomial addition operation in the ADD2 419 operator. At this time, the polynomial addition of the ADD2 419 is selectively performed only when the most significant bit value of the input value from the ADD1 417 is '1', unlike the polynomial addition in the ADD0 413 or the ADD1 417 operator. At this time, the operation result is shifted by one bit to the right, and the result is stored in the B register 410 again. This operation is repeated by the bit length of the register to perform a polynomial multiplication operation. After the operation ends, the result value of the B register 410 becomes the result of the final polynomial multiplication operation. The input multiplexers 415 and 416 of the ADD1 417 control the input to be the output of the MUL 414 operator and the value of the B register 410 during the polynomial multiplication operation, and the input multiplexers 418 of the ADD2 419. , 420 controls the output of the ADD1 417 operator and the minimum polynomial value to be input. The G multiplexer 404 then controls the input of the G register 405 to be Gl, which is the value of the one bit shifted G register 405 through the Ls block 406. The B multiplexer 409 controls the B register 410 input to be ADD2 419. The C register 408 does not change value during operation.

In the elliptic curve processor according to the present invention, polynomial inverse arithmetic operations are implemented as modified modified most inverse algorithms.

Input: a (F2m, a (0.

Output: a (1 mod f (x) (minimum polynomial).

1.B <-1, C <-0, F <-a, G <-f

While x divides F do:

2.1 F <-F / x.

2.2 If x divides B then B <-B / x, else B <-(B + f) / x.

3.If F = 1 the return (B).

4.If deg (F) <deg (G) then: F "G, B" C.

5.F <-F + G, B <-B + C.

6.Goto step 2.

Where F, G, B, and C represent the F register 402, the G register 405, the C register 408, and the B register 410, respectively, a being the input value of the polynomial inverse function operation, and f (x ) Means the minimum polynomial.

Looking at the operation of the above algorithm in the elliptic curve processor operator, first, the value to be inversed is stored in the F register 202, the B register 410, the C register 408, and the G as in step 1 of the algorithm. The register 405 is initialized to '1', '0', and 'f', respectively. Then, to search for the condition of the While statement of Step 2, it is searched whether the least significant bit of the value of the F register 402 is '0'. If the least significant bit value of the F register 402 is '0', the value of the F register 402 is shifted one bit to the right as in step 2.1. This operation is accomplished by controlling the F multiplexer 401 such that the F register 402 output value through the Rs block 403 is stored in the F register 402 again. Step 2.2 The operation is performed by selectively performing a polynomial addition operation with the minimum polynomial only if the lowest value of the B register 410 output in the ADD2 419 operator is '0'. At this time, the operation result is shifted one bit to the right, and the result is stored in the B register 410 again. Steps 4 and 5 are performed simultaneously, and an order comparison of the F register 402 and the G register 405 for step 4 is made in the order comparator 15. When the order of the F register 402 is large, the F multiplexer 401 is controlled so that the input of the F register 402 becomes ADD0 413, which is the result of the polynomial addition of the F register 402 and the G register 405. Otherwise, the F multiplexer 401 is controlled so that the value of the G register 405 is input. Similarly, if the order of the F register 402 is large, the B register 410 input becomes the value of ADD1 417, which is the result of the polynomial addition of the B register 410 and the C register 408, otherwise the C register 408 The B multiplexer 409 is controlled so that the value is input. The inputs of the G register 405 and the C register 408 control the G multiplexer 404 and the C multiplexer 407 to be the values of the F register 402 and the B register 410 regardless of the comparison result. These series of operations are repeated until the value of the F register 402 becomes '1' as in step 3, where the order comparison unit 500 searches whether the F register 402 becomes '1'. . When the polynomial inverse operation is completed, the value of the B register 410 becomes the polynomial inverse function output value.

A polynomial inverse multiplication operation is a combination of such a polynomial inverse operation and a polynomial multiplication operation. First, a polynomial inverse operation is performed to store a result in the C register 408, and then a value to be multiplied is input to the G register 405. Performs a polynomial multiplication operation. The result of the final polynomial inverse multiplication operation is output to the B register 410.

In the elliptic curve processor multiplier according to the present invention, the elliptic curve addition operation is implemented by a combination of the above-mentioned operations. The elliptic curve addition operation is divided into elliptic curve double operation and elliptic curve coordinate addition operation according to the input value, and is implemented by polynomial multiplication operation, polynomial inverse multiplication operation, and polynomial addition operation like the following elliptic curve addition operation algorithm.

Input: P ₁ = (x ₁ , y ₁ ), P ₂ = (x ₂ , y ₂ ).

Output: P ₃ = P ₁ + P ₂ = (x ₃ , y ₃ ).

1.If P ₁ = P ₂ (double elliptic operation)

x ₃ = (λ ² + λ + a, y ₃ = x ₁ ² + (λ + 1) x ₃

where (λ = x ₁ + y ₁ / x ₁ )

2.Else if P ₁ (P ₂ (add elliptic curve coordinates)

x ₃ = (2 + λ + x ₁ + x ₂ + a, y ₃ = λ (x ₁ + x ₃ ) + x ₃ + y ₁

where (λ = (y ₂ + y ₁ ) / (x ₂ + x ₁ ))

3.Return (x ₃ , y ₃ )

Where P ₁ = (x ₁ , y ₁ ), P ₂ = (x ₂ , y ₂ ) correlate with the registers X 1, Y 1, X ₂ , and Y ₂ of the register file unit 200 (204, 205, 207, 209). It simply has the meaning as an input to the algorithm.

Both the elliptic curve doubling operation and the elliptic curve coordinate addition operation calculate λ and compute the value from x ₃ , and then calculate the y ₃ value using λ and x ₃ . The intermediate result values are stored in registers that are used for the next operation or are not used for the operation, and are used again when needed. The final result is stored in X2 register 207 and Y2 register 209 of the register file.

The elliptic curve double operation is performed only in the scalar multiplication operation mode, and performs the double operation of the values of the X2 register 207 and Y2 register 209 of the register file, and stores the result in the X2 register 207 and the Y2 register. . To this end, first, the value of the X2 register 207 is brought into the F register 402 to perform a polynomial inverse function operation. Move the result of the polynomial inverse function from the B register 410 to the C register 408, bring the Y2 register 209 value into the G register 405, perform a polynomial multiplication operation with the value of the C register 408, and then register the X2 register. When the value is stored in the C register 408 and the polynomial multiplication result and the polynomial addition operation are performed, the lambda value of the algorithm is calculated. Saving this λ value G in the register 405 and the C register 408 and again performs a polynomial multiplication operation is calculated λ ^2. At this time, since the value of the C register 408 does not change during the polynomial multiplication operation, the lambda value remains in the C register 408. Therefore, when the polynomial addition operation of the B register 410 and the C register 408 is performed, (λ ² + λ) is calculated, and finally, the A parameter value is multiplied using the ADD2 219 operator to perform x3 You get The x3 value of the B register 210 is moved to the F register 402 and the G register 405 for output to the X2 register 207 and y ₃ calculation, and the B register 410 is initialized to '1'. Then a polynomial addition operation of the C register 408 and the B register 410 is performed and stored in the C register 408. By performing the polynomial multiplication operation of the value of the C register 408 and the G register 405, (λ + 1) x ₃ of the algorithm can be obtained. The result is stored in the F register 402 again. At this time, x ₃ stored in the F register 402 is stored in the X2 register 207, and the value of the X2 register 207 is stored in the G register 405 and the C register 408 for x ₁ ² calculation. Transferred to a G register 405, and then performs a polynomial multiplication operation result of the operation of x ₁ ² G register 405, the C register 408, performs the F register 402 and polynomial addition operation to G register 405 If you store at, the final y ₃ is computed. When the result of the polynomial addition operation is stored in the Y2 register 209, the elliptic curve doubling operation is completed.

Elliptic curve coordinate addition is computed in much the same way as an elliptic curve doubling operation. However, before the polynomial multiplication operation or the polynomial inverse function operation, a polynomial addition operation for addition of two coordinates is performed. The series of operations required for elliptic curve doubling or coordinate addition is accomplished by controlling the multiplexers and register load signals in the elliptic curve processor controller. In addition, since the elliptic curve processor operator according to the present invention provides various operations and data paths, the elliptic curve addition operation may be performed by other procedures in addition to the above-described method.

4 is a diagram illustrating an embodiment of a degree comparison unit illustrated in FIG. 1.

As shown in Fig. 4, the order comparator according to the present invention is a multiplexer 501 for selecting an input of the F order register 502 and the F order register 502 for storing the order of the value of the F register 402. ), A G order register 503 for storing the order of the value of the G register 405, an order finder 504 for searching the order of the input value, and a comparator 505 for comparing the two register orders. .

The order comparison operation block is used to compare the order of the value of the F register 402 and the order of the value of the G register 405 when performing a polynomial inverse function operation. It is also used to determine the completion of an operation of a polynomial inverse function or to check the infinite origin of an elliptic curve addition operation.

Looking in detail at the operation of the order comparator 505, when the polynomial inverse function operation is started, the order of the value of the F register 402 is retrieved from the order finder 504 and stored in the F order register 502, and the G order register ( 503 is initialized to the order of the value of the G register 405. The order of this G register 405 is predetermined when the parameters of the elliptic curve cryptosystem to be implemented are selected. As the operation progresses, the comparator 505 has two outputs, and the comp signal is higher than the G register 405 order when the value is '1' as a result of comparing the F register 402 order and the G register 405 order. Indicates. It is input to an elliptic curve processor controller to affect controller operation. The other output of the comparator 505 is the result of the subtraction of the G order register 503 value from the actual F order register 502 value, so that the F order register 302 is updated with this output value in accordance with the comp signal. In addition, when the F register 402 performs a one-bit right shift operation, the comparator 505 outputs a value obtained by subtracting '1' from the order value of the F register 402 to update the value of the F order register 402. do. Completion of the polynomial inverse operation and infinite origin check result from the order finder 504. The D_F signal of the two outputs of the order finder 504 completes the polynomial inverse function operation when this value is '0' as the order result of the input value. The zero signal is a signal for determining whether the input value of the order finder 504 is '0' and determines the infinite origin using this signal.

FIG. 5 is a diagram illustrating an embodiment of a NAF converter of FIG. 1. FIG.

As shown in FIG. 5, the NAF conversion unit according to the present invention includes an operation mode setting unit 101 and a conversion unit 102.

If elliptic curve coordinates can be defined for '-', 7 (111 ₂ ) P can be calculated as 8 (1000 ₂ ) P + (-P). In the case of 7 (111 ₂ ) P, two elliptic curve double operations and three elliptic curve coordinate addition operations are performed.In the case of 8P + (-P), three elliptic curve double operations and one elliptic curve coordinate subtraction operation are performed. Can be calculated as If the coordinate of one point P of the elliptic curve is (x, y), '-P' is defined as (x, x + y), and as a result, the operation amount of the elliptic curve doubling operation and the elliptic curve addition operation is similar. 8P + (-P) rather than 7P can reduce the overall computation. The technique of changing the representation of numbers in the form of '-1' when there is a continuous '1' is called non-adjacent format (NAF) transformation. The advantage is better efficiency. In particular, the elliptic curve processor operator according to the present invention can perform an elliptic curve coordinate subtraction operation in substantially the same process as an elliptic curve coordinate addition operation. It only involves one more polynomial addition operation when calculating λ and when calculating y3.

Referring to the operation of the NAF converter for this purpose, the operation mode setting unit 101 is a block that stores the mode for NAF conversion, when the operation mode is '0', the output of the converter is expressed as '0' and '1' If the operation mode is '1', the NAF conversion is performed in the conversion unit. In the NAF conversion mode, the representation of numbers is represented by three values: '0', '1', and '-1'. The operation mode setting unit 101 is composed of a sequential circuit to store these mode values. When the operation mode is '0' and the lower 3 bits of the new input are consecutive '1', the mode is set to '1'. The mode is inverted when the mode is '1' and the second bit is '0'. The operation mode setting unit 101 determines the start and end of the operation according to the state of the elliptic curve processor controller. The conversion unit 102 converts the value from the N register into a NAF number by referring to the mode value from the operation mode setting unit 101, and outputs the NAF. The operation mode is inverted from '0' to '1'. '1' is output when the operation mode is reversed from '1' to '0' and '-1' is output. If the operation mode is '1' and '0' otherwise, the output value is output as it is. The NAF converter 100 shown in the present invention is implemented to convert the number when there are three or more consecutive '1's. However, the NAF change technique is valid even when there are two consecutive '1's, and its implementation is almost similar to the above.

The elliptic curve encryption device developed in the above structure has the following effects.

First, the elliptic curve cryptographic system proposed by the present invention provides high security and high performance in electronic commerce, electronic money, user identification, user key management, payment system, and the like.

Second, the elliptic curve encryption device implemented by the method proposed in the present invention can be efficiently used for efficient key exchange, signature, user authentication, etc. in a limited memory capacity and low-performance processor computing environment such as IC card, PDA, portable terminal, etc. Can be used.

Third, the elliptic curve encryption apparatus proposed by the present invention uses a scalar multiplication operation, an elliptic curve coordinate addition operation, a polynomial multiplication operation, a polynomial inverse multiplication operation, and a polynomial inverse function operation that require a lot of time to process an elliptic curve encryption algorithm. Processing at high speed meets real-time processing requirements for implementing elliptic curve protocols in application systems.

Fourth, the elliptic curve encryption device proposed in the present invention can perform fast encryption and decryption, key exchange, signing, and authentication while using less memory than the conventional RSA asymmetric key encryption algorithm.

Fifth, the elliptic curve encryption device proposed in the present invention can be easily extended according to the safety and performance of the application system.

Claims (7)

In the elliptic curve encryption device, A register file section for storing input data and output data for elliptic curve encryption, An elliptic curve processor calculating unit which performs various operations of an elliptic curve on the data stored in the register file unit; An order comparison unit for performing order search and comparison required for the operation of the elliptic curve processor operation unit; A NAF converter for supporting a scalar multiplication operation in the elliptic curve processor calculator; And an elliptic curve processor controlling unit for generating a control signal for controlling an operation mode of the elliptic curve processor. The method of claim 1, wherein the register file unit, A first register section for storing a scalar multiplication constant; A first multiplexing unit for determining an input of the first register unit; A cycler for cycling the value of the first register portion one bit to the left; Second and third register portions for storing an elliptic curve base point or an input value of an operation; Fourth and fifth register portions for storing inputs and outputs of other coordinates of the elliptic curve, And an elliptic curve encryption device including second and third multiplexers for determining inputs of the fourth and fifth registers, respectively. The method of claim 1, wherein the elliptic curve processor calculation unit, A plurality of registers for storing input data and output data for elliptic curve encryption; A plurality of multiplexers for controlling the input of each register, A polynomial addition operation unit for performing a polynomial addition operation on the data input to the register unit; A multiplexer for controlling the input of the polynomial addition operator; A polynomial multiplication unit for performing bit multiplication, Elliptic curve encryption device including a shift unit for one bit left and right shift. The method of claim 1, wherein the order comparison unit, A first order register section for storing an order of values stored in a first register in the elliptic curve processor computing section; A first multiplexer for selecting an input of the first order register section; A second order register for storing an order of values stored in a second register in the elliptic curve processor; An order searching unit for searching an order of input values inputted to the first and second order registers; And an comparing unit for comparing the orders stored in the first and second order registers with each other. The method of claim 1, wherein the NAF conversion unit, An operation mode setting unit for storing a mode for NAF conversion; When the operation mode set in the operation mode setting unit is '0', the output is represented by '0' and '1', and when the operation mode is '1', an ellipse including a conversion unit that performs NAF conversion. Curved encryption device. The method of claim 5, wherein the operation mode setting unit, An elliptic curve that inverts the mode to '1' when the operation mode is '0' and the lower 3 bits of the new input are consecutive '1', and when the mode is '1' and the second bit is '0'. Encryption device. The method of claim 1, wherein the control signal of the controller, And an elliptic curve encryption apparatus controlling the elliptic curve processor to perform one of a scalar multiplication mode, an elliptic curve coordinate addition operation mode, a polynomial multiplication operation mode, a polynomial inverse multiplication operation mode, and a polynomial inverse function operation mode.