KR20030043798A - Nonvolatile memory - Google Patents

Abstract

In a nonvolatile memory in which the load of the boost circuit is changed by the number of rewrite bytes, the boost circuit is configured to step up at a predetermined relatively low speed irrespective of the number of rewrite bytes, thereby reducing the stress applied to the storage element to reduce the rewrite resistance. To improve.

Description

Nonvolatile Memory {NONVOLATILE MEMORY}

A memory element constituting a nonvolatile semiconductor memory device (hereinafter referred to as a nonvolatile memory), for example, a floating gate formed through a gate insulating film on a channel forming region between a drain and a source region, and an inter-gate insulating film on such a floating gate. There is a MOSFET having a so-called two-layered gate structure that has a control gate formed through and stores information depending on whether electrons are accumulated in the floating gate. In addition, a gate electrode is formed on the channel forming region through a three-layer gate insulating film made of an oxide film, a nitride film, and an oxide film, and a nonvolatile material made of a MOSFET of a so-called MONOS structure, which stores information by electrons or holes accumulated in the nitride film. There is a memory element.

These nonvolatile memory devices require a relatively low voltage for reading information, while a relatively high voltage is required for writing information and erasing information, resulting in injection of a hot carrier or generation of a tunnel current in the gate insulating film. . In a conventional nonvolatile memory, a built-in booster circuit for generating a high voltage used for writing or erasing is often configured to operate with a single power supply.

By the way, in a nonvolatile memory having a MONOS structure MOSFET which stores information by accumulating electrons or holes in a conventional nitride film as a storage element, at the time of writing, a positive voltage Vcc is applied to a gate, which is a storage element, and a well region ( Electrons are accumulated in the nitride film by applying a negative high voltage (-Vpp) to the back gate, while a negative high voltage (-Vpp) is applied to the gate and a positive voltage (Vcc) is applied to the gate during erasing. It accumulates in the nitride film to change the threshold of the memory device. Here, focusing on one memory element, the well region includes a source, a drain region, and a channel forming region, and is relatively large in size, while the gate electrode has almost the same size as the channel forming region. As a result, the load of the booster circuit is smaller for the gate electrode having a less parasitic capacitance than the well region, that is, the word line, when the boosted high voltage is applied, so that the boosting speed is faster than the write time. do. However, when the boosting speed is high, the stress applied to the memory element becomes large, so there is an unreasonable fact that there is a limit on the maximum number of times of rewriting (hereinafter, referred to as rewriting resistance).

Further, at the time of erasing, a negative high voltage (-Vpp), such as a gate electrode, is applied to the well region of the non-selective, non-erasing memory element to prevent holes from accumulating in the nitride film. In this case, the size of the load of the booster circuit changes according to the number of unselected wells, and as the number of unselected wells increases, the boosting speed decreases. This causes an irrationality that the rewrite resistance of the memory varies.

That is, in a memory that can be rewritten in units of bytes, the wells are common in units of bytes, and therefore, in addition to rewriting in units of bytes, the memory capable of rewriting in units of, for example, 64 bytes belonging to the same word line called page mode. In the rewrite mode, that is, the number of unselected wells is changed by rewriting in units of pages. Therefore, in a system with many accesses to the memory in the page mode with a small number of non-selected wells, the average boosting speed is faster than a system with many accesses to the byte-based memory, resulting in low memory rewrite resistance. Causes irrationality.

However, in the conventional nonvolatile memory design, the rewriting time is important, and the boosting speed is increased by increasing the capability of the boosting circuit so that rewriting is terminated within a predetermined time even in the rewrite of the byte unit where the number of unselected wells increases. The design to speed up was often performed. Therefore, in the nonvolatile memory capable of simultaneous rewriting of a plurality of bytes (including rewriting in page mode) and rewriting in units of bytes, there is a problem in that the rewrite resistance decreases when the rewriting of a plurality of bytes increases.

An object of the present invention is to provide a nonvolatile memory having a high rewrite resistance and a semiconductor integrated circuit such as a microcomputer incorporating the same.

Another object of the present invention is to provide a nonvolatile memory and a semiconductor integrated circuit such as a microcomputer incorporating the nonvolatile memory, which can avoid large fluctuations in rewrite resistance depending on the system or method of use.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

(Initiation of invention)

The outline | summary of the typical thing of the invention disclosed in this application is briefly described as follows.

In other words, the step-up speed in the boosting circuit is important for improving the rewrite resistance of the nonvolatile memory, and the slower the step-up speed is, the less stress is placed on the memory device and the higher the write-resistance is. The higher the speed, the greater the stress applied to the memory element and the lower the rewrite resistance. Therefore, it is preferable that the boost speed is slow and the boost speed is constant regardless of the number of rewrite bytes. The slower the boosting speed, the higher the rewrite resistance, but too slow the longer the rewriting time, the more important the balance between the two.

According to the present invention, in a nonvolatile memory in which the load of the booster circuit changes depending on the number of rewrite bytes, the booster circuit is configured to boost at a predetermined relatively inconsistent speed regardless of the number of rewrite bytes. More specifically, it has a power supply terminal, a ground terminal, a plurality of nonvolatile memory elements, a control circuit, and a boosting circuit for boosting the power supply voltage supplied to the power supply terminal. In a nonvolatile memory in which the magnitude of the load of the booster circuit is different at the time of writing or erasing the memory cell while being applied to the back gate of the nonvolatile memory element, the booster circuit is at the time of writing. It was configured such that the step-up speed at and the step-up speed at the time of erasing were substantially the same. As a result, the stress applied to the storage element at the time of writing or erasing becomes small, so that the rewrite resistance of the nonvolatile memory can be improved.

Also, a power supply terminal, a ground terminal, a plurality of nonvolatile memory elements, a control circuit, and a boosting circuit for boosting the power supply voltage supplied to the power supply terminal, wherein the high voltage generated by the boosting circuit is the nonvolatile memory. In a nonvolatile memory in which the load of the booster circuit changes in accordance with the number of data at the time of writing or erasing the memory cell while being applied to the back gate of the device, the booster circuit is at the time of writing. Alternatively, the boosting speed is made constant regardless of the number of data at the time of erasing. As a result, it is possible to improve the rewrite resistance of the nonvolatile memory by avoiding different stresses applied to the memory device depending on the number of data during writing or erasing.

In addition, according to the user's request, that is, when the user gives priority to the data guarantee time over the rewrite tolerance, the boosting speed is increased, and when the user gives priority to the rewrite tolerance over the data guarantee time, the boosting speed is increased. Configured to be low. More specifically, a clock generating circuit for generating a boosted clock signal for operating the boosting circuit and a setting circuit for setting a frequency of the boosted clock signal generated by the clock generating circuit are provided, and the clock is provided. The generating circuit is configured to generate a clock signal for boosting the frequency according to the value set in the setting circuit. The slower the boosting speed, the lower the stress applied to the memory element, which improves the rewriting resistance.However, in general, depending on the specification, the rewriting time is often determined by a certain value for each product. In such a case, the boosting speed is increased. If the speed is too slow, the high voltage application time will be short, and the data guarantee time to ensure that the data will not change even if left unchanged for a long time after rewriting will be shortened.However, by setting the boosting speed by the setting circuit, The user can select which of the data guarantee times is given priority.

And a clock generating circuit for generating an internal clock signal for operating the control circuit, and a second setting circuit for setting a frequency of the internal clock signal generated in the clock generating circuit, wherein the clock generating circuit is provided. Is configured to generate an internal clock signal having a frequency corresponding to the value set in the second setting circuit. As a result, the boosting speed can be increased when the user gives priority to the rewrite speed over the rewrite tolerance, and the boosting speed can be lowered when the user gives priority to the rewrite tolerance over the rewrite speed. It is possible to provide a highly versatile nonvolatile memory having such characteristics.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording and erasing method in a nonvolatile semiconductor memory device. For example, a nonvolatile memory device such as an electrically rewritable programmable read-only memory (EEPROM) and an LSI (large scale) such as a microcomputer incorporating the same. It is related with the effective technique used for a semiconductor integrated circuit).

1 is a block diagram showing an embodiment of an EEPROM as an example of a nonvolatile memory to which the present invention is applied.

Fig. 2 is a sectional view showing the structure of the memory cells constituting the memory array of the EEPROM of the embodiment.

Fig. 3 is a view for explaining an example of the circuit configuration of the memory cell and the voltage applied to the word line, the high voltage word line, the data line, and the source line in each of the EEPROM of the embodiment in the erase, write, and read operations.

Fig. 4 is a waveform diagram showing waveforms of voltage applied to the gate (word line) and the well of the rewrite of the EEPROM of the embodiment.

Fig. 5 is a characteristic diagram showing the gate voltage-drain current characteristics of each of the memory devices after the initial state, after erasing, and after writing in the EEPROM of the embodiment.

Fig. 6 is a circuit arrangement drawing showing an example of the configuration of a counter portion for counting the number of rewrite bytes in the EEPROM of the embodiment.

Fig. 7 is a circuit arrangement diagram showing an example of the configuration of a selector section for selecting a boosting clock to be supplied to the charge pump in the EEPROM of the embodiment.

8 is an explanatory diagram showing a boosting speed in a conventional EEPROM and a boosting speed in an EEPROM of the present invention.

Fig. 9 is a block diagram showing a second embodiment of an EEPROM as an example of a nonvolatile memory to which the present invention is applied.

Fig. 10 is a block diagram showing an example of a system for setting to a setting circuit (register) in the EEPROM of the second embodiment.

11 is an explanatory diagram showing a relationship between a boosting speed and a cycle time in an EEPROM according to another embodiment of the present invention;

Fig. 12 is a block diagram showing the third embodiment of the EEPROM as an example of the nonvolatile memory to which the present invention is applied.

Fig. 13 is a block diagram showing a configuration example of an IC card system as an example of an application system of an EEPROM to which the present invention is applied.

14 is a schematic diagram showing the appearance of an IC card.

(The best mode for carrying out the invention)

Fig. 1 shows a block diagram of an embodiment of an EEPROM as an example of a nonvolatile memory to which the present invention is applied. Although not particularly limited, in the memory device constituting the EEPROM of this embodiment, a gate electrode is formed through a three-layer gate insulating film made of an oxide film, a nitride film, and an oxide film on a channel formation region, and electrons or holes are accumulated in the nitride film. Is composed of MOSFETs of a so-called MONOS structure, which are arranged in matrix form, memory peripheral circuits for selecting, writing and reading memory arrays, and generating high voltages necessary for writing or erasing. A booster circuit or the like is formed on one semiconductor chip such as single crystal silicon.

In Fig. 1, 10 is provided in such a manner that the word line WL and the data line DL cross each other, and a nonvolatile memory device is provided at each intersection of each word line WL and the data line DL. It is a memory array in which a memory cell is included. Although not particularly limited, in the memory array 10 of this embodiment, control gates of 512 or 64 bytes of memory cells are connected to one word line WL, and memory cells of the same row are provided in units of eight, that is, byte units. It is formed on the same well region WELL0 to WELL63. In addition, memory cells of the same column connected to the same data line DL are formed on the same well WELL0 to WELL63. In the memory array 10, a high-voltage word line HWL for applying a write voltage or an erase voltage to the memory elements of each memory cell is parallel to the word lines WL and the common source line SL. It is arrange | positioned and arrange | positioned in parallel with this said data line DL, respectively.

More specifically, as shown in Fig. 3, the memory cells constituting the memory array 10 are connected so that the MONOS-MOSFET Qm as the nonvolatile memory element, the MOSFET Qm, and the channel are in series. And a gate and a drain (or source) of the dual selection switch MOSFET (Qs) are connected to the word line WL and the data line DL, respectively, and the MONOS-MOSFET Qm. Gate and source (or drain) are respectively connected to the high voltage word line HWL and the common source line SL. Vwell is a well potential applied to a substrate (back gate) of MOSFETs Qm and Qs.

In FIG. 1, reference numeral 11 denotes a well potential control circuit which applies a write voltage or an erase protection voltage to each well region WELL0 to WELL63 of the memory array 10, and 12 denotes each data line DL of the memory array 10. In FIG. Is a column latch circuit connected to the circuit board to amplify the potential read on the data line in the selected memory cell to latch the read data or to hold the write data loaded on the data line DL at the time of writing. A data input / output circuit for outputting or receiving write data input from the outside of the chip and transferring the write data to the data latch, 14 decodes the column address Ay input from the outside and applies a voltage by the well potential control circuit 11. A column decoder for selecting a well or selecting data latched in the column latch circuit 12 in units of bytes.

The column decoder 14 transfers the byte data corresponding to the address signal to the column latch circuit 12 between the data line DL and the data input / output circuit 13 in the byte read / write mode. At the same time, in the page mode, for example, 64 bytes of data are sequentially input to the data input / output circuit 13 or output to the data input / output circuit 13 in byte units while updating an internal address counter.

Further, 15 decodes the lower address signal Ax input from the outside to select one word line WL in the memory array 11 or to selectively apply an erase voltage to the high voltage word line HWL. The decoder 16 determines an operation mode based on the chip select signal (/ CS) indicating the chip selection state input from the outside, the read / write signal (R / W) for instructing the writing or reading operation of data, and the like. The timing control circuit generates an internal timing control signal according to a mode.

In the EEPROM of this embodiment, the clock generation circuit 17 which generates the internal clock signal? C required by the timing control circuit 16 based on the reference clock signal? A high voltage power supply circuit 20 for generating a high voltage (-Vpp) required at the time is provided. The high voltage (-Vpp) generated in the high voltage power supply circuit 20 is supplied to the well potential control circuit 11, the column latch circuit 12, and the lower address decoder 15 at a predetermined timing according to each operation mode. .

The high voltage power supply circuit 20 boosts a power supply voltage Vcc such as 5.5V, 3.3V, and 1.8V supplied from an external source, and high voltages such as -7V, -10V, and -11V required for recording and erasing (-Vpp). A booster circuit 21 composed of a charge pump or the like, an oscillator circuit 22 such as a ring oscillator for generating a booster clock required for the operation of the booster circuit 21, and a frequency divider circuit for distributing the booster clock. (23), a selector 24 for selecting a clock of a desired frequency as the divided clock, a clamp circuit 25 for clamping the boosted voltage to a desired potential, and the like. Since the power supply circuit of such a configuration is frequently used and known in a flash memory, the detailed description is omitted.

In addition to the high voltage (-Vpp) at the time of writing and erasing, the power supply circuit 15 generates a power supply voltage other than Vcc required in the chip such as a read voltage and a verify voltage, and at the same time, the memory The desired voltage is selected from these voltages in accordance with the operation state of and supplied to the well potential control circuit 11, the column latch circuit 12, the lower address decoder 15, and the like.

In this embodiment, a counter section 26 is provided which counts byte signals / LD2 having pulses corresponding to the number of rewrite bytes supplied from an external CPU or the like, and is counted by the counter section 26. The selector 25 is controlled in accordance with the number of bytes to control the boosting speed in the boosting circuit 21. Specifically, the selector 25 supplies a clock having a low frequency to the booster circuit 21 when the boosting speed is to be slowed down, and supplies a clock having a high frequency to the booster circuit 21 when the boosting speed is fastened. Is controlled. The byte signal / LD2 is a signal in which one pulse means one byte of rewritable data. For example, when eight pulses of the byte signal / LD2 are continuously supplied, eight bytes of data are rewritten. have.

Fig. 2A shows the structure of a nonvolatile memory device composed of MOSFETs of MONOS structure constituting the memory array 10. Figs. The MOSFET of the MONOS structure has a three-layer structure consisting of an oxide film 131, a nitride film 132, and an oxide film 133 on the surface of a P-type well region 120 surrounded by an N-type isolation region 110 on a semiconductor substrate 100. A gate electrode 140 made of polysilicon is formed through the gate insulating film 130 of the source insulating film 130, and a source region 151 made of an n-type diffusion layer is formed on the surfaces of the P-type well regions 120 on both sides of the gate insulating film 130. The drain region 152 is formed.

In the nonvolatile memory device Qm including the MOSFET of the MONOS structure, a negative high voltage (-Vpp) is applied to the gate electrode 140 at the time of erasing as shown in FIGS. 2B and 3A. A positive voltage Vcc is applied to the well region 120, and Vcc is applied to the source and the drain, and holes are accumulated in the nitride film. In this case, in the non-selective memory element having the word line in common, injection of holes is prevented by applying the same high voltage (-Vpp) as the high voltage word line HWL to the well as shown in FIG. .

On the other hand, at the time of writing, as shown in Figs. 2C and 3C, the positive voltage Vcc is applied to the gate electrode 140, the negative high voltage (-Vpp) is applied to the well region 120, and the source and the like. -Vpp is also applied to the drain to control electrons to accumulate in the nitride film. In this embodiment, at the time of erasing and writing, write data " 1 " corresponds to the erase operation, and write data " 0 " corresponds to the write operation. Therefore, in the memory element Qm which is rewritten from data "1" to "0", only erasing is performed, and at the time of data writing, the drain (data line side) potential is Vcc and the source as shown in Fig. 3D. By dislocation being floated, it controls so that injection of an electron may not be performed.

4 shows the voltage waveform A applied to the gate electrode of the memory element Qm and the voltage waveform B applied to the well at the time of data rewriting. As can be seen from the figure, a negative high voltage (-Vpp) is first applied to the gate electrode 140 and a positive voltage Vcc is applied to the well region 120. A voltage of + Vpp is applied to inject holes into the gate insulating film. Subsequently, a positive voltage Vcc is applied to the gate electrode 140 and a negative high voltage (-Vpp) is applied to the well region 120, so that the voltage of the writing depth Vcc + Vpp between the gates and the wells is opposite to that of erasing. Direction, and electrons are injected into the gate insulating film.

By the rewrite operation as described above, in the initial state, the memory device having the gate voltage-drain current characteristic as shown in curve A of FIG. 5 is changed as shown by curve B when holes are accumulated in the nitride film by erasing. The threshold is at a level equal to about -2V. When holes are accumulated in the nitride film by writing, the characteristics change as shown in the curve C, and the threshold value of the memory element is at a level equal to 2V. Although not particularly limited, the memory element having the characteristics such as curve B is turned on because the threshold is low when it is selected at the time of reading, and the precharged data line DL changes to low level, thereby storing the memory data "1". Is read as. On the other hand, the memory element having the characteristics such as curve C is turned off because the threshold value is high when it is selected at the time of reading, and the precharged data line DL remains at the low level and is read out as the storage data "0". .

3E shows the bias state of the memory cell at the time of reading. As shown in the figure, at the time of reading, the word line WL becomes Vcc after being precharged to Vcc so that the selection switch MOSFET Qs is turned on. In addition, the high voltage word line HWL becomes a potential such as 0 V, and is turned on or off depending on the threshold value 2V or -2V of the MOSFET Qm of the selected memory cell. Current flows toward the source line SL, and the potential of the data line DL changes to 0 V. When off, the current path is cut off from the data line DL toward the source line SL so that the data line DL is closed. The potential remains at Vcc. This potential is amplified and latched by the column latch circuit 12 connected to the data line. In this embodiment, the logic of this latched data is inverted and output.

6 shows an example of the configuration of the counter section 26 shown in FIG. As shown in Fig. 6, the counter section 26 includes a counter 261 and an output control signal generating section 262 that can count up to " 64 " in synchronization with the rising or falling of the byte signal / LD2. have. As shown in Table 1, the double counter 261 outputs the signal SEL1 to the high level ("1") when the pulse of the byte signal / LD2 is 1 to 16, and when the pulse is 17 to 32. The output signal SEL2 is at a high level, the output signal SEL3 is at a high level when the pulses are 33 to 48, and the output signal SEL4 is at a high level when the pulses are 49 to 64. .

The output control signal generator 262 may include NAND gates G1 to G4 that input the output signals SEL1 and SEL2 to SEL4 of the counter 261 or the signals / SEL2 to / SEL4 inverted by the inverter. And NOR gates G11 to G14 that input common enable signals EWP to the respective output signals of these NAND gates G1 to G4. As shown in Table 1, byte signals ( When the pulses of LD2) are 1 to 16, only the output signal CNT1 is at high level, when the pulses are 17 to 32, only the output signal CNT2 is at high level, and when the pulses are 33 to 48, the output signal CNT3 is Only at high level, when the pulse is 49 to 64, only the output signal CNT4 is configured to change to high level. These output signals CNT1 to CNT4 are supplied as a selection control signal to the selector section 24 which selects the clock divided by the division circuit 23.

7 shows an example of the configuration of the selector section 24. The selector 24 receives inputs of the clocks OSC1, OSC2, OSC3, and OSC4 having different frequencies output from the frequency dividers 23a to 23d of the frequency divider 23, respectively. Transmission gates G21 to G24 such as clock in buffers using the signals CNT1 to CNT4 supplied from the control signal as a control signal, a NOR gate G31 that takes a logic of the signals CNT1 to CNT4, and the NOR gate ( A pull-up MOSFET (Qp) that is controlled on and off by the output signal of G31).

When the signals CNT1 to CNT4 shown in Table 1 are supplied to the transfer gates G21 to G24 by the output control signal generator 262, any one of them is in a conductive state, and the clock in the frequency dividing circuit 23 is applied. One of (OSC1, OSC2, OSC3, OSC4) is supplied to the booster circuit 21 at the rear stage. Specifically, when the number of rewrite bytes is 1 to 16, the higher frequency clock (OSC1) is 17 to 32, when the frequency is slightly lower (OSC2), and when it is 33 to 48, the lower frequency clock (OSC3) is When 49 to 64, the clock OSC4 having the lowest frequency is supplied to the boosting circuit 21, respectively. On the other hand, when the signals CNT1 to CNT4 are all " 0 ", the transfer gates G21 to G24 are all shut off, and the output of the NOR gate G31 is at low level so that the pull-up MOSFET Qp is turned on and divided. While the clock in the circuit 23 is not supplied to the boosting circuit 21, the voltage supplied to the boosting circuit 21 is prevented from becoming constant. As a result, the boosting circuit 21 stops the boosting operation while not performing the rewrite operation or the like.

In the EEPROM having the configuration as shown in FIG. 1 using the MONOS-MOSFET having the structure shown in FIG. 2, a high voltage (-Vpp) is applied to an unselected well of the same word line at the time of erasing, depending on the number of rewrite bytes. Since the number of unselected wells changes and the size of the load of the booster circuit changes accordingly, if no countermeasures are taken, the boosting speed slows down as the number of unselected wells increases, and the boosting speed as the number of unselected wells decreases. In this embodiment, the boosting speed varies greatly as shown in Fig. 8A. However, in this embodiment, the frequency of the clock supplied to the boosting circuit 21 is changed in accordance with the number of rewrite bytes as described above. As shown in Fig. 8B, the fluctuation range of the boosting speed becomes small.

As a result, when there are many rewrites in byte units and when there are many rewrites in page mode, variations in the rewrite resistance can be avoided. However, in this embodiment, since the control for changing the boosting speed in accordance with the number of rewrite bytes is made to be on the slower side, the stress applied to the memory element at the time of erasing becomes smaller, compared to the case where the boosting speed is set to the faster side. Significantly improves resistance.

Further, in this embodiment, when the rewriting of data of 1 to 64 bytes is divided into four steps, and the step-up speed of the boosting circuit 21 can be controlled in four steps by changing the frequency of the clock according to the number of rewriting bytes. However, the present invention is not limited thereto, and may be divided into arbitrary stages such as eight stages and sixteen stages in relation to the circuit scale and the like.

Next, another embodiment of the present invention will be described with reference to FIG. In Fig. 9, the same circuit blocks as those in Fig. 1 are denoted by the same reference numerals and redundant description thereof will be omitted.

As described above, the slower the boosting speed during erasing, the smaller the stress applied to the memory element, and the higher the rewrite resistance. In general, however, depending on the specification, the rewrite time (TO in Fig. 8) is often set to a certain value for each product. In such a case, if the boosting speed is made too slow, the high voltage application time (T1 in Fig. 8) becomes short, and the data guarantee time for ensuring that the data does not change even if left for a long time after rewriting is shortened. However, there are users who actually value rewrite tolerance rather than data assurance time, and users who value data assurance time rather than rewrite tolerance.

Therefore, in the embodiment of Fig. 9, the oscillation frequency in the oscillation circuit 22 for generating the boosted clock signal is configured to be adjustable, and a setting circuit such as a register for setting the oscillation frequency to a degree ( 31) is being installed. It is possible to change the boosting speed by changing the value set in the setting circuit 31, so that it is possible to set whether to prioritize the rewrite resistance or the data guarantee time after the manufacture of the memory chip or after the memory is assembled in the system. do.

In addition, although the setting circuit 31 is not limited to a register, when the setting circuit 31 is comprised by a register, as shown in FIG. 10, the value of this register 31 is controlled by the external CPU 50 by a bus. It is preferable to configure so that it can set through 60. The oscillation frequency of the oscillation circuit 22 may be changed after chip fabrication by a setting circuit having a programmable element such as a fuse or a nonvolatile memory instead of a resistor. In that case, the frequency information may be set by a dedicated tester or recording device, or the CPU 50 may set the frequency information by accessing the nonvolatile memory.

In the embodiment of Fig. 9, a second setting circuit 32 made of a resistor or the like is provided correspondingly to the clock generation circuit 17 for generating the internal operation clock? C. When the set value of 32 is changed, the frequency of the internal clock phi c changes, the cycle time changes, and the rewrite time T0 itself changes.

As described above, the slower the boosting speed at the time of erasing, the smaller the stress applied to the memory element, and the better the rewriting resistance. However, if the boosting speed is too slow, the high voltage application time (T1 in Fig. 8) becomes shorter and the data becomes smaller. The warranty time becomes short. However, when the cycle time T0 is long, as shown in Fig. 11B, even if the boosting time Tu is increased by Δt, the cycle time T0 is also increased by Δt in accordance with this, before the T0 is lengthened (Fig. Since the erase voltage application time Te equal to 11 (A) is ensured, the rewrite resistance is improved and the data guarantee time can be further extended.

In addition, in the embodiment of Fig. 9, an example is provided in which the setting circuit 31 for changing the oscillation frequency of the step-up clock and the setting circuit 32 for changing the oscillation frequency of the internal operation clock? C are separately provided. Although shown, only the setting circuit 31 for changing the oscillation frequency of the step-up clock may be provided, or the setting circuit may be shared. Here, sharing the setting circuit means that when the oscillation frequency of the boosting clock is changed, the oscillation frequency of the internal operation clock?

The cycle time of the memory directly affects the access speed, which is an important factor in the characteristics of the memory. However, depending on the system, the rewrite tolerance and the data guarantee time are more important than the access speed. In some cases. According to this embodiment, changing the set value of the setting circuit 32 sets the clock frequency high when the access speed is important, and sets the clock frequency high when the rewrite resistance and data guarantee time are important. It can handle any request without having to design it.

Fig. 12 shows another embodiment of the present invention. In the embodiment of Fig. 12, a power supply circuit 20A for generating a high voltage (-Vpp) for well application and a power supply circuit 20B for generating a high voltage (-Vpp) of a high voltage word line are separately provided. Since other configurations are the same as those in FIG. 1, the same circuit blocks as in FIG.

In this embodiment, the power supply circuit 20A for generating a high voltage (-Vpp) for well application has the same configuration as the power supply circuit 20 shown in FIG. On the other hand, the power supply circuit 20B which generates the high voltage (-Vpp) of the high voltage word line has a constant load (only the selected high voltage word line HWL) regardless of the number of rewrite bytes, and no change in the boosting speed is required. In the power supply circuit 20 of this embodiment, the selector 24 and the counter 26 for counting the byte signal / LD2 are not necessary. In the embodiment as shown in Fig. 9 in which the power supply circuit 20 is common for the wells and the high-voltage word lines, and the setting circuit 31 for setting the frequency of the boosting clock is provided to adjust the boosting speed at the time of erasing. When the setting of the setting circuit 31 is changed, the boosting speed at the time of recording is also automatically changed. However, in the embodiment of Fig. 12, only the boosting speed at the time of erasing can be adjusted independently. It is possible to optimize the boosting speed of each separately.

Fig. 13 shows a system configuration example in the case where the EEPROM chip is used as the memory of the IC card. In Fig. 13, 201 is an EEPROM as a nonvolatile memory according to the present invention having the configuration as described in the above embodiment, 202 is a CPU (central processing unit) of a program control method for controlling the whole system, and 203 is a CPU. ROM (Read Only Memory) that stores the program to be executed or fixed data necessary for the execution of the program; Input / output port 206 for transmitting and receiving signals between the card and a device external to the card. The input / output port 206 is required for operation of the EEPROM 201 or the CPU 202 by waveform shaping or dividing the clock signal CLK supplied from the outside of the card. A clock generation circuit for generating a system clock phi c.

These circuits are each composed of individual chips or formed on one semiconductor chip, and the CPU 202, the ROM 203, the RAM 204, the EEPROM 201, and the input / output port 205 are the address bus 207. And data bus 208 are connected to each other to enable data transmission and reception. In addition, the CPU 202 is supplied with the signal / LD2 indicating the number of bytes of the rewrite described above to the EEPROM 201.

In Fig. 13, 211 to 216 are external terminals, and receive power supply terminals 211 and 212 supplied with power supply voltages Vcc and Vss, and a reset signal / RES for initializing the system. There are a reset terminal 213, a clock terminal 214 that receives a clock signal CLK supplied from the outside of the card, and data input / output terminals 215 and 216 connected to the input / output port 205 to perform serial input / output. .

Fig. 14 shows the appearance of an IC card incorporating the above EEPROM. In the drawing, reference numeral 300 denotes a card body formed of a plastic chip or the like, and 310 denotes an electrode portion as an external terminal provided on the surface of the card body 300. The external terminals 211 to 216 shown in FIG. Is electrically connected. Each chip 201 to 206 shown in Fig. 13 is disposed below the electrode portion 310 in Fig. 14, and is housed in a package made of plastic or the like, or mounted on a printed wiring board so that the whole is made of resin or the like. By being molded.

The IC card according to the present invention is not limited to the contact type as shown in Fig. 14, and may be a non-contact type IC card, in which case the electrode portion 310 as an external terminal may not appear in appearance. Further, in the IC card according to the present invention, as information for controlling rewriting so that a data guarantee time is lengthened, money information on a financial IC card, ID information when used as an ID card, and encryption when performing an encryption process Key / decryption key.

The system to which the EEPROM according to the present invention is applied is not limited to the above-described IC card system.

As mentioned above, although the invention made by this inventor was demonstrated concretely based on the Example, this invention is not limited to the said Example, Needless to say that various changes are possible in the range which does not deviate from the summary.

For example, in the above embodiment, the present invention has been described in the case where the data is applied to an EEPROM capable of collectively erasing data and an IC card using the same. However, the present invention includes a nonvolatile memory device having a two-layer gate of a floating gate and a control gate. The present invention can also be applied to other nonvolatile memories such as flash memories configured to collectively erase data and storage media using the same.

In the nonvolatile memory of the above embodiment, data "1" corresponds to erasing, and data "0" corresponds to writing, but data "1" corresponds to writing and data "0" corresponds to erasing. It is also possible.

Also, in the embodiment, the EEPROM has been described in which the threshold of the memory cell is increased by writing and the threshold is reduced by erasing. However, the nonvolatile device is used to make the threshold of the memory cell low by writing and to change the threshold high by erasing. It may be applied to a memory. Further, in the embodiment, the one-bit memory cell is composed of a memory element (MOSFET (Qm)) and a select switch element (MOSFET (Qs)), but without the select switch element, the memory element is directly connected to the data line DL. It may be a memory array having memory cells configured to be connected. In addition, although the embodiment has been described for storing one bit of data per one memory cell, it is also possible to store a plurality of bits of data per one memory cell.

In the above description, the case where the present invention is applied to an EEPROM and an IC card equipped with the same has been described, but the present invention can be used for other nonvolatile memories and electronic devices incorporating the same.

Claims (15)

And a power supply terminal, a ground terminal, a plurality of nonvolatile memory elements, a control circuit, and a boosting circuit for boosting a power supply voltage supplied to the power supply terminal. In a nonvolatile memory in which a write or an erase is performed by being applied to a back gate, and the magnitude of the load of the booster circuit differs in writing and erasing of the memory cell, And the boosting circuit is configured such that the boosting speed at the time of writing and the boosting speed at the time of erasing are substantially the same. And a power supply terminal, a ground terminal, a plurality of nonvolatile memory elements, a control circuit, and a boosting circuit for boosting a power supply voltage supplied to the power supply terminal. In a nonvolatile memory in which a load on the booster circuit changes in accordance with the number of data at the time of writing or erasing the memory cell while being written or erased by being applied to a back gate, And the boosting circuit is configured such that the boosting speed is constant regardless of the number of data during writing or erasing. The method of claim 2, A clock generation circuit for generating a plurality of boosting clock signals having different frequencies for operating the boosting circuit, and a counting circuit for counting the number of data at the time of writing or erasing, wherein the boosting circuit includes: And a boosting clock signal of a frequency in accordance with the counting result, so that the boosting speed is kept constant regardless of the number of data. The method of claim 2 or 3, A clock generating circuit for generating a boosted clock signal for operating the boosting circuit, and a setting circuit for setting a frequency of the boosted clock signal generated by the clock generating circuit; A nonvolatile memory, characterized in that it is configured to generate a clock signal for boosting a frequency in accordance with a value set in a circuit. The method according to claim 2, 3 or 4, A clock generation circuit for generating an internal clock signal for operating the control circuit, and a second setting circuit for setting a frequency of the internal clock signal generated in the clock generation circuit; A nonvolatile memory, characterized in that it is configured to generate an internal clock signal of a frequency in accordance with a value set in a second setting circuit. The method according to claim 1, 2, 3, 4, or 5, The memory device has a MONOS structure in which a gate electrode is formed through a three-layer gate insulating film made of an oxide film, a nitride film, and an oxide film on a channel forming region between the drain and source regions, and electrons or holes are accumulated in the nitride film. Nonvolatile memory, characterized in that consisting of a MOSFET. The method of claim 6, In the memory device, one-byte memory devices adjacent to each other connected to the same word line are formed on the same wafer region on the surface of the semiconductor substrate, and each well region is configured such that different voltages can be applied thereto. Nonvolatile Memory. The method of claim 7, wherein The memory device is characterized in that the high voltage generated in the boost circuit is applied to the well region when electrons are injected into the nitride film. The method of claim 8, In the memory device, when a hole is injected into the nitride film, a high voltage generated by the booster circuit is applied to the gate electrode of the memory device of the selected word line, and the memory device connected to the same word line and not selected is stored in the well region. Non-volatile memory, characterized in that a high voltage is applied to prevent the injection of electrons or holes. The nonvolatile memory of Claims 1-9, An IC card in which a semiconductor chip having a control function for giving a control signal for writing or reading data to a nonvolatile memory is stored in a package. And a power supply terminal, a ground terminal, a plurality of nonvolatile memory elements, a control circuit, and a boosting circuit for boosting a power supply voltage supplied to the power supply terminal. In a control method of a nonvolatile memory in which a load on the booster circuit changes in accordance with the number of data at the time of writing or erasing the memory cell while being applied to the back gate, Counting the number of data at the time of writing or erasing, and selecting the clock signal for boosting to the boosting circuit according to the number of data and controlling the boosting speed to be constant regardless of the number of data. Way. An IC card having a memory section and a controller section, each of which comprises a plurality of nonvolatile memory cells, stored in one package, And the plurality of nonvolatile memory cells are capable of changing a voltage increase rate of an erase voltage applied to the memory cells in accordance with predetermined information during an erase operation. The method of claim 12, And said predetermined information corresponds to the number of memory cells to be subjected to an erase operation. The method of claim 12, And said predetermined information can be read by said controller section, and said controller section controls the step-up rate of an erase voltage in accordance with said predetermined information. An IC card having a memory section comprising a plurality of memory cells, In the case of writing predetermined information, in the erasing operation of the memory cell to be recorded, the erase ratio to be applied to the memory cell to be recorded at the time of writing the other information and the step-up ratio of the erase voltage to be applied to the memory cell. IC card whose voltage boost rate is controlled differently.