KR20030043512A - Method for preventing a bad contact and an assembly process reduction in semiconductor package - Google Patents

Method for preventing a bad contact and an assembly process reduction in semiconductor package Download PDF

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Publication number
KR20030043512A
KR20030043512A KR1020010074752A KR20010074752A KR20030043512A KR 20030043512 A KR20030043512 A KR 20030043512A KR 1020010074752 A KR1020010074752 A KR 1020010074752A KR 20010074752 A KR20010074752 A KR 20010074752A KR 20030043512 A KR20030043512 A KR 20030043512A
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South Korea
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semiconductor chip
pad
semiconductor
assembly process
wafer
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KR1020010074752A
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Korean (ko)
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KR100438404B1 (en
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임강환
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동부전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67282—Marking devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE: A method is provided to be capable of reducing assembly process in semiconductor package and preventing bad contact between a pad and lead by simply attaching pins of a semiconductor chip to leads of a module using pressure. CONSTITUTION: After truncating a wafer into semiconductor chips(S2), a tape is attached on the wafer for preventing the deviation of the truncated semiconductor chip. The tape attached wafer is divided into semiconductor chips by cutting using a blade. After picking up the semiconductor chip, a pad(S3) of the semiconductor chip is attached on a pin(S5) formed on a lead(S4) of a module by simply using pressure. A marking process is carried out on the rear surface of the attached semiconductor chip. The semiconductor chip mounted on the module is encapsulated by using a cover for protecting the semiconductor chip.

Description

반도체 패키지의 조립 공정 단축 및 접촉불량 방지방법{METHOD FOR PREVENTING A BAD CONTACT AND AN ASSEMBLY PROCESS REDUCTION IN SEMICONDUCTOR PACKAGE}Reduction of assembly process of semiconductor package and prevention of contact failure {METHOD FOR PREVENTING A BAD CONTACT AND AN ASSEMBLY PROCESS REDUCTION IN SEMICONDUCTOR PACKAGE}

본 발명은 반도체 패키지의 조립 공정 단축 및 접촉불량 방지방법에 관한 것으로, 특히 웨이퍼에서 잘라진 칩을 픽 업(pick up)하여 모듈상의 리드(lead)에 누르는 힘을 이용하여 부착시키는 과정을 통해 단축된 공정과정을 만들며, 또한 핀(pin)을 이용하여 패드와 리드를 연결하고, 커버(cover)에 스프링을 사용하여 패드와 리드 부분의 접촉 불량을 억제할 수 있도록 하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for shortening the assembly process of a semiconductor package and a method for preventing contact failure. In particular, the present invention reduces the process of picking up chips cut from a wafer and attaching them using a pressing force to a lead on a module. The present invention also relates to a method of making a process and connecting a pad and a lead using pins, and using a spring in a cover to suppress a poor contact between the pad and the lead portion.

통상적으로, 반도체 제조의 조립공정(후공정, 패키징 공정)은 전공정(process)을 거친 웨이퍼(wafer)로부터 각각의 낱개로 다이싱(dicing)된 칩(chip)에 배선하여 전기적인 동작을 완성하며, 사용상의 편의를 위하여 외장(molding) 표시, 포장 등을 의미하며, 그 중에서도 다이싱(dicing), 다이 본딩(die bonding), 와이어 본딩(wire bonding), 몰딩(molding) 등을 일컬어 프론트 엔드(front end)라 칭한다.In general, an assembly process (post process, packaging process) of semiconductor manufacturing is completed by wiring each chip which is diced from a wafer which has been processed before, to complete electrical operation. For the convenience of use, it means molding marking, packaging, etc. Among them, dicing, die bonding, wire bonding, molding, etc. are referred to as front end. It is called a front end.

도 1을 참조하면, 종래 반도체 패키지의 조립 공정방법에 대한 흐름도를 설명한 것으로, 웨이퍼 마운터(wafer mounter)를 이용한 공정 1단계로, 웨이퍼를 낱개의 칩(chip)으로 절단하고, 절단된 칩의 이탈을 방지하기 위해 웨이퍼에 테이프(tape)를 부착시킨다(F1).Referring to FIG. 1, a flow chart of a method of assembling a semiconductor package according to the related art is described. In the first step of a process using a wafer mounter, the wafer is cut into individual chips and the chip is separated. In order to prevent the tape (tape) is attached to the wafer (F1).

웨이퍼 소우(wafer saw)를 이용한 공정 2단계로, 칩 단위로 분리하는 공정으로서, 물리적 지지를 위해서 테이프에 웨이퍼를 붙인 후, 블래드(blade)를 회전시켜 칩 단위로 자른다(F2).In a two step process using a wafer saw, a step of separating a chip is performed. The wafer is attached to a tape for physical support, and then the blade is rotated and cut into chips (F2).

이후, 다이 본더(die bonder)를 이용한 공정 3단계로, 잘라진 칩을 픽업(pick up)하여 리드 프레임(lead frame)의 패들(paddle)위에 접착제(epoxy)를 사용해서 부착시킨다. 이후, 접착제를 경화시키는 공정 과정이 뒤따르게 된다(F3).Thereafter, in the process step 3 using a die bonder, the chip is picked up and attached to the paddle of the lead frame by using an adhesive. Thereafter, the process of curing the adhesive is followed (F3).

이어서, 와이어 본더(wire bonder)를 이용한 공정 4단계로, 칩과 리드 프레임을 전기적으로 연결시키기 위해 금(Au) 선으로 칩의 패드와 리드 프레임의 리드 사이를 연결한다(F4).Subsequently, in step 4 of using a wire bonder, a gold line is used to connect the pad of the chip and the lead of the lead frame in order to electrically connect the chip and the lead frame (F4).

다음으로, 몰드(mold)를 이용한 공정 5단계로, 와이어 본딩(wire bonding)이 끝난 제품을 물리적, 전기적, 화학적 충격으로 보호하기 위해 EMC(epoxy mold compound : EMC) 열경화성 수지를 이용해 밀봉한다. 여기서, EMC의 경화를 위해 베이킹(baking) 공정이 필요하다(F5).Next, in a process step 5 using a mold, the wire-bonded product is sealed using an epoxy mold compound (EMC) thermosetting resin to protect the finished product by physical, electrical and chemical impact. Here, a baking process is required to cure the EMC (F5).

마킹(marking)을 이용한 공정 6단계로, 패키지 표면에 제조회사, 칩번호 등을 레이저 빔 또는 잉크를 이용해 표시한다(F6).In a six-step process using marking, the manufacturer, chip number and the like are displayed on the package surface using a laser beam or ink (F6).

다음으로, 트림(trim)을 이용한 공정 7단계로, 몰딩(molding)시 새어나온 EMC 부분과, EMC가 새어 나오는 것을 막고, 리드 프레임의 형상을 유지시켜 주는 뎀바(dambar)를 제거한다(F7). 그리고, 폼(form)을 이용한 공정 8단계로, 금속형금형을 이용한 공정 과정이 이루어진다(F8).Next, in the process step 7 using a trim, the EMC portion leaked out during molding, and prevents EMC from leaking out, and removes the dambar maintaining the shape of the lead frame (F7). . Then, in step 8 of the process using a form, a process using a metal mold is performed (F8).

마지막으로, 패키지(package)를 이용한 공정 9단계로, 패키지(package)의 형태에 따라 리드(lead)의 형상을 만든다(F9).Finally, in step 9 of using a package, a shape of a lead is formed according to the shape of the package (F9).

상술한 바와 같이, 공정 1단계에서 공정 9단계까지의 전 조립 공정 과정이 길어짐에 따라 생산 시 조립 시간이 길어져 원가 상승을 유발하게 되는 원인이 되며, 또한 금(Cu) 선으로 칩의 패드(pad)와 리드 프레임(lead frame)의 리드 사이를 연결함에 따라 패드와 리드 부분의 접촉 불량률을 증가하게 되는 문제점이 있었다.As described above, as the entire assembly process from step 1 to step 9 becomes longer, assembling time increases during production, causing cost increase, and the pad of the chip with gold (Cu) lines. ), There is a problem in that the contact failure rate between the pad and the lead portion is increased by connecting between the lead and the lead of the lead frame.

따라서, 본 발명은 상술한 문제점을 해결하기 위해 안출된 것으로서, 그 목적은 웨이퍼에서 잘라진 칩을 픽 업(pick up)하여 모듈상의 리드(lead)에 누르는 힘을 이용하여 부착시키는 과정을 통해 공정과정을 단축할 수 있으며, 금(Cu) 선 대신에 핀(pin)을 이용하여 패드와 리드를 연결하고, 커버(cover)에 스프링을 사용하여 위에서 아래 방향으로 칩을 눌러 패드와 리드 부분의 접촉 불량을 억제할 수 있도록 하는 반도체 패키지의 조립 공정 단축방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-described problems, the object of the process is to pick up the chips cut from the wafer (pick up) by using a pressing force on the lead (lead) on the module process through the process The pin and lead can be connected using pins instead of the Cu wires, and the contact between the pads and the lead parts is poor by pressing the chip from the top to the bottom using a spring on the cover. It is to provide a method for shortening the assembly process of a semiconductor package that can be suppressed.

상술한 목적을 달성하기 위하여 본 발명에서 반도체 패키지의 조립 공정 단축방법은 웨이퍼를 낱개의 반도체 칩(chip)으로 절단하고, 절단된 반도체 칩의 이탈을 방지하기 위해 웨이퍼에 테이프(tape)를 부착시키는 제1단계; 테이프가 부착된 웨이퍼를 물리적 지지를 위해 블래드(blade)를 회전시켜 칩 단위로 자르는 제2단계; 잘라진 반도체 칩(chip)을 픽업하여 모듈내 리드(lead) 상의 핀(pin)에 반도체 칩을 보호하기 위해 형성된 패드(pad)를 누르는 힘을 이용하여 부착시키는 제3단계; 부착된 반도체 칩의 후면에 마킹(marking)하는 제4단계; 모듈 상에 장착된 반도체 칩을 보호하기 위해 커버(cover)를 씌워 제작하는 제5단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, a method for shortening the assembly process of a semiconductor package may include cutting a wafer into individual semiconductor chips, and attaching a tape to the wafer to prevent separation of the cut semiconductor chips. First step; A second step of cutting the tape-attached wafer into chips by rotating a blade to physically support the wafer; A third step of picking up the sliced semiconductor chip and attaching it to a pin on a lead in the module by pressing a pad formed to protect the semiconductor chip; A fourth step of marking the back surface of the semiconductor chip attached thereto; And a fifth step of manufacturing a cover to protect the semiconductor chip mounted on the module.

도 1은 종래 반도체 패키지의 조립 공정방법에 대한 흐름도를 도시한 도면이고,1 is a flowchart illustrating a method of assembling a semiconductor package according to the related art.

도 2는 본 발명에 따른 반도체 칩을 구비한 모듈에 대하여 도시한 도면이며,2 is a view showing a module having a semiconductor chip according to the present invention,

도 3은 도 2에 도시된 반도체 칩(chip)이 안착되는 부분을 칩의 크기 및 두께를 계산하여 홈을 형성시킨 상세 도면이며,3 is a detailed view in which grooves are formed by calculating a size and a thickness of a chip in which a semiconductor chip illustrated in FIG. 2 is seated;

도 4는 도 3에 도시된 칩의 패드(pad)와 모듈의 리드(lead) 부분에 대한 상세 도면이며,FIG. 4 is a detailed view of the pad of the chip and the lead portion of the module shown in FIG.

도 5는 본 발명에 따른 모듈에 장착된 칩을 보호하기 위해 커버(cover)를 씌운 도면이다.Figure 5 is a cover (cover) to protect the chip mounted on the module according to the invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

S1 : 모듈 S2 : 반도체 칩S1: module S2: semiconductor chip

S3 : 패드(pad) S4 : 리드(lead)S3: Pad S4: Lead

S5 : 핀(pin) S6 : 구리(cu)S5: pin S6: copper (cu)

S7 : Ni S8 : 티탄(Ti)S7: Ni S8: Titanium (Ti)

S9 : 폴리 이미디(poly lmide) S10 : 실리콘(Si)S9: poly lmide S10: silicon (Si)

S11 : 폴리 산화물(poly oxide) S12 : 알루미늄 판S11: poly oxide S12: aluminum plate

S13 : 스프링 S14 : 고정핀 홀S13: Spring S14: Locking Pin Hole

S15 : 커버(cover)S15: cover

이하, 첨부된 도면을 참조하여 본 발명에 따른 실시 예를 상세하게 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 개인용 컴퓨터(PC)에 적용되는 모듈(S1)로서, 모듈(S1)내에 4개의 반도체 칩(chip)(S2)이 일정 간격으로 구비되어 있으며, 이러한 각각의 반도체 칩(S2)이 모듈(S1)상에 장착되는 세부 과정은 도 3 내지 도 4에 도시되어 있으며, 도 5는 장착된 반도체 칩(S2)을 외부 환경으로부터 보호하기 위해 커버(S15)를 씌운 도면이다.FIG. 2 is a module S1 applied to a personal computer PC according to the present invention. In the module S1, four semiconductor chips S2 are provided at regular intervals. A detailed process of mounting S2 on the module S1 is illustrated in FIGS. 3 to 4, and FIG. 5 is a diagram illustrating a cover S15 to protect the mounted semiconductor chip S2 from an external environment.

상술한 도면을 참조하면서, 본 발명에 따른 반도체 패키지의 조립 공정 단축 및 접촉불량 방지방법에 대하여 보다 상세하게 설명한다.With reference to the above-described drawings, a method of shortening the assembly process of the semiconductor package according to the present invention and preventing contact failure will be described in more detail.

먼저, 웨이퍼 마운터(wafer mounter) 제 1단계 공정으로, 웨이퍼를 낱개의 칩(chip)으로 절단하고, 절단된 칩의 이탈을 방지하기 위해 웨이퍼에 테이프(tape)를 부착시킨다.First, in a wafer mounter first step process, the wafer is cut into individual chips, and a tape is attached to the wafer to prevent the chip from being separated.

이후, 웨이퍼 소우(wafer saw) 제 2단계 공정으로, 칩 단위로 분리되는 공정으로서, 물리적 지지를 위해서 블래드(blade)를 회전시켜 테이프가 부착된 웨이퍼를 칩 단위로 자른다.Subsequently, in a wafer sawing step 2 step, the wafer is separated into chips, and the tape-attached wafer is cut into chips by rotating a blade for physical support.

다음으로, 칩 얼라인(Chip Align) 제 3단계 공정으로, 잘라진 칩(chip)을 픽업하여 도 2 내지 도 4와 같이, 모듈(S1)상의 리드(S4)에 누르는 힘을 이용하여 반도체 칩(S2)을 부착시킨다.Next, in the third step of chip alignment, the chip is picked up and the semiconductor chip (B) is pressed using a force pressed against the lead S4 on the module S1 as shown in FIGS. 2 to 4. Attach S2).

본 발명에 따른 제 3단계 공정에 대하여 보다 상세하게 설명하면, 도 2에 도시된 4개의 반도체 칩(S2) 중 특정 반도체 칩(S2)을 모듈(S1)상에 장착하는 과정으로, 도 3을 참조하면, 도 3은 도 2에 도시된 반도체 칩(S2)과 리드(lead)(S4)간의 세부도로서, 리드(lead)(S4) 부분에 핀(pin)(S5)을 형성하여 다이 얼라인(Die Align)시 본드 패드(pad)(S3)에 핀(S5)이 닿도록 하기 위해 반도체 칩(S2)의 크기와 두께를 계산하여 홈을 형성하고, 또한 리드(S4) 부분을 반도체 칩(S2)에 형성된 패드(S3)의 크기보다 작게 턱을 형성시키는 것이다.Referring to the third step process according to the present invention in more detail, a process of mounting a specific semiconductor chip (S2) of the four semiconductor chips (S2) shown in Figure 2 on the module (S1), Figure 3 For reference, FIG. 3 is a detailed view of the semiconductor chip S2 and the lead S4 illustrated in FIG. 2. The pin S5 is formed on the lead S4 to be dialed. The grooves are formed by calculating the size and thickness of the semiconductor chip S2 so that the pins S5 come into contact with the bond pad S3 during the die alignment, and the lead S4 is formed in the semiconductor chip. The jaw is formed smaller than the size of the pad S3 formed in S2.

여기서, 리드(S4) 부분의 핀(S5)은 패드(S3)를 보호하기 위하여 핀(S5)의 끝 부분에 저항(R) 성분을 주어 제작하고, 핀(S5)의 높이 또한 패드(S3)에 손상을 주지 않을 정도의 크기로 제작한다.Here, the fin S5 of the lead S4 is manufactured by giving a resistance R component to the end of the fin S5 to protect the pad S3, and the height of the fin S5 is also the pad S3. The size should not be damaged.

그리고, 패드(S3)의 형성은 반도체 칩(S2)을 보호하기 위하여 형성하는 것으로, 도 4를 참조하면 된다.In addition, the pad S3 is formed to protect the semiconductor chip S2, and reference may be made to FIG. 4.

즉, 도 4는 도 3에 도시된 패드(S3)의 형성 과정을 도시한 도면으로서, 기존 반도체 칩은 폴리 이미드(poly lmide : Pi) 까지만 형성하였지만, 본원 발명에서는 Pi층에 탈륨(Thallium : Tl), 니켈(Nickel : Ni) , 구리(Copper : Cu) 층을 더 형성시켜 반도체 칩(S2)내의 회로를 보호하는 것이다. 여기서, 패드(S3)는 알루미늄(Al)으로 되어 있으며, Ti, Ni, Cu는 Al 패드(S3)를 보호하기 위한 언더 베이스 메탈(under base metal)인 것이다.That is, FIG. 4 is a view illustrating a process of forming the pad S3 illustrated in FIG. 3. Although the conventional semiconductor chip is formed only up to polyimide (Pi), in the present invention, thallium (Thallium) is formed in the Pi layer. Tl), nickel (Ni), and copper (Copper: Cu) layers are further formed to protect the circuit in the semiconductor chip S2. Here, the pad S3 is made of aluminum (Al), and Ti, Ni, and Cu are under base metals for protecting the Al pad S3.

다음으로, 마킹(Marking) 제 4단계 공정으로, 패키지 표면, 즉 반도체 칩(S2)의 후면에 제조회사, 칩 번호 등을 레이저 광(laser beam) 또는 잉크를 이용해 표시한다.Next, in the fourth step of marking, the manufacturer, the chip number, and the like are displayed on the surface of the package, that is, the back surface of the semiconductor chip S2 using a laser beam or ink.

마지막으로, 커버(cover) 부착 제 5단계 공정으로, 도 5를 참조하면, 본 발명에 따른 모듈(S1)상에 장착된 반도체 칩(S2)을 보호하기 위해 커버(cover)(S15)를 씌운 도면으로서, 커버(S15)와 반도체 칩(S2) 사이에는 알루미늄 판(S12)을 사용하여 칩 사이즈(chip size)로 제작한다.Finally, in a fifth step of attaching the cover, referring to FIG. 5, a cover S15 is covered to protect the semiconductor chip S2 mounted on the module S1 according to the present invention. As a drawing, an aluminum plate S12 is used between the cover S15 and the semiconductor chip S2 to produce a chip size.

그리고, 제작된 커버(S15)와 알루미늄 판(S12) 사이에 스프링(S13)을 형성하여 제작한다. 그러면, 스프링(S13)의 힘에 의해 반도체 칩(S2)을 고정시킬 수 있으며, 패드(S3)와 핀(S5)간의 접촉을 시켜주어 반도체 칩(S2)의 이탈을 방지할 수 있는 것이다.Then, a spring S13 is formed between the manufactured cover S15 and the aluminum plate S12 to manufacture. Then, the semiconductor chip S2 can be fixed by the force of the spring S13, and the pad S3 can be brought into contact with the pin S5 to prevent the semiconductor chip S2 from being separated.

여기서, 커버(S15)와 알루미늄 판(S12) 사이에 형성된 스프링(S13)은 완충작용의 역할을 수행하며, 이 스프링(S13)의 강도는 반도체 칩(S2)의 패드(S3)에 손상을 주지 않을 정도의 강도로 제작한다. 여기서, 커버(S15) 부분의 상단 부분에도 마킹(Marking)한다.Here, the spring (S13) formed between the cover (S15) and the aluminum plate (S12) serves as a buffering action, the strength of the spring (S13) does not damage the pad (S3) of the semiconductor chip (S2). Produced to the strength that is not enough. Here, the upper portion of the cover S15 is also marked.

그러므로, 본 발명은 웨이퍼에서 잘라진 칩을 픽 업(pick up)하여 모듈상의 리드(lead)에 누르는 힘을 이용하여 부착시키는 과정을 통해 공정과정을 단축하여 양산시 시간 절약 및 원가 절감을 할 수 있으며, 금(Cu) 선 대신에 핀(pin)을 이용하여 패드와 리드를 연결하고, 커버(cover)에 스프링을 사용하여 위에서 아래 방향으로 칩을 눌러 패드와 리드 부분의 접촉 불량을 억제할 수 있으며, 또한 사용도중 불량 칩이 발생하여도 쉽게 교체할 수 있으며, 알루미늄 판 및 커버를 사용하여 열 방출을 줄일 수 있는 효과가 있다.Therefore, the present invention can shorten the process through the process of picking up the chip cut from the wafer and attaching it by using a pressing force on the lead on the module, thereby saving time and cost during mass production. Instead of the Cu wire, pins can be used to connect the pads and leads, and springs can be used on the cover to press the chip from the top to the bottom to suppress contact between the pads and the leads. In addition, it can be easily replaced even if a bad chip occurs during use, it is effective to reduce heat dissipation by using aluminum plate and cover.

Claims (8)

반도체 패키지의 조립 공정과정에 있어서,In the assembly process of the semiconductor package, 웨이퍼를 낱개의 반도체 칩(chip)으로 절단하고, 상기 절단된 반도체 칩의 이탈을 방지하기 위해 상기 웨이퍼에 테이프(tape)를 부착시키는 제1단계;Cutting the wafer into individual semiconductor chips, and attaching a tape to the wafer to prevent separation of the cut semiconductor chips; 상기 테이프가 부착된 웨이퍼를 물리적 지지를 위해 블래드(blade)를 회전시켜 칩 단위로 자르는 제2단계;A second step of cutting the tape-attached wafer into chips by rotating a blade to physically support the wafer; 상기 잘라진 반도체 칩(chip)을 픽업하여 모듈내 리드(lead) 상의 핀(pin)에 상기 반도체 칩을 보호하기 위해 형성된 패드(pad)를 누르는 힘을 이용하여 부착시키는 제3단계;A third step of picking up the cut semiconductor chip and attaching it to a pin on a lead in a module using a pressing force of a pad formed to protect the semiconductor chip; 상기 부착된 반도체 칩의 후면에 마킹(marking)하는 제4단계;A fourth step of marking a back surface of the attached semiconductor chip; 상기 모듈 상에 장착된 반도체 칩을 보호하기 위해 커버(cover)를 씌워 제작하는 제5단계를 포함하는 것을 특징으로 하는 반도체 패키지의 조립 공정 단축 및 접촉불량 방지방법.And a fifth step of manufacturing a cover to protect the semiconductor chip mounted on the module. 제 1 항에 있어서, 상기 제3단계는,The method of claim 1, wherein the third step, 상기 패드(pad)에 핀이 닿도록 하기 위해 상기 반도체 칩의 크기와 두께를 계산하여 홈을 형성하고, 상기 리드 부분을 반도체 칩에 형성된 패드의 크기보다 작게 턱을 형성시키는 것을 특징으로 하는 반도체 패키지의 조립 공정 단축 및 접촉불량 방지방법.The semiconductor package, characterized in that to form a groove by calculating the size and thickness of the semiconductor chip so that the pin is in contact with the pad, the jaw is formed smaller than the size of the pad formed on the semiconductor chip. To shorten the assembly process and prevent contact failure. 제 1 항 또는 제 2 항에 있어서, 상기 리드 상의 핀(pin)은,3. The pin of claim 1, wherein the pin on the lead comprises: 상기 패드를 보호하기 위하여 상기 핀의 끝 부분에 저항(R) 성분을 주어 제작하고, 상기 핀의 높이를 상기 패드에 손상을 주지 않을 정도의 크기로 제작하는 것을 특징으로 하는 반도체 패키지의 조립 공정 단축 및 접촉불량 방지방법.Shortening the assembly process of the semiconductor package, characterized in that to provide a resistance (R) component to the end of the pin to protect the pad, and to produce a height of the pin so as not to damage the pad And contact failure prevention method. 제 1 항에 있어서, 상기 패드의 형성 과정은,The method of claim 1, wherein the forming of the pad comprises: 상기 웨이퍼에 폴리 이미드(poly lmide : Pi )를 형성하고, 상기 형성된 Pi층에 탈륨(Thallium : Tl), 니켈(Nickel : Ni) , 구리(Copper : Cu) 층을 더 형성하는 것을 특징으로 하는 반도체 패키지의 조립 공정 단축 및 접촉불량 방지방법.Forming a polyimide (Pi) on the wafer, and further forming a layer of thallium (Thallium, Tl), nickel (Ni), and copper (Copper: Cu) on the formed Pi layer. A method for shortening the assembly process of semiconductor packages and preventing contact defects. 제 4 항에 있어서, 상기 패드는,The method of claim 4, wherein the pad, 상기 반도체 칩 내의 회로를 보호하기 위해 알루미늄(Al)으로 되어 있으며, 상기 Ti, Ni, Cu는 상기 패드를 보호하기 위한 언더 베이스 메탈(under base metal)인 것을 특징으로 하는 반도체 패키지의 조립 공정 단축 및 접촉불량 방지방법.In order to protect the circuit in the semiconductor chip is made of aluminum (Al), the Ti, Ni, Cu is shortened the assembly process of the semiconductor package, characterized in that the under base metal (under base metal) for protecting the pad and How to prevent poor contact. 제 1 항에 있어서, 상기 제5단계는,The method of claim 1, wherein the fifth step, 상기 커버와 반도체 칩 사이에는 알루미늄 판을 사용하여 칩 사이즈(chip size)로 제작하는 것을 특징으로 하는 반도체 패키지의 조립 공정 단축 및 접촉불량 방지방법.Shortening the assembly process of the semiconductor package and the contact failure prevention method, characterized in that produced between the cover and the semiconductor chip in a chip size (chip size) using an aluminum plate. 제 6 항에 있어서, 상기 커버와 반도체 칩 사이에는,The method of claim 6, wherein between the cover and the semiconductor chip, 스프링을 형성하여 제작하고, 상기 스프링의 힘에 의해 상기 반도체 칩을 고정 및 이탈을 방지하며, 상기 스프링의 강도는 상기 반도체 칩의 패드에 손상을 주지 않을 정도의 강도로 제작되는 것을 특징으로 하는 반도체 패키지의 조립 공정 단축 및 접촉불량 방지방법.Forming and manufacturing a spring, and prevents the fixing and detachment of the semiconductor chip by the force of the spring, the strength of the spring is characterized in that the strength is produced to a degree that does not damage the pad of the semiconductor chip Shortening the assembly process of the package and preventing contact failure. 제 7 항에 있어서,The method of claim 7, wherein 상기 커버 부분의 상단 부분에도 마킹(Marking)을 하는 것을 특징으로 하는 반도체 패키지의 조립 공정 단축 및 접촉불량 방지방법.Shortening the assembly process of the semiconductor package, characterized in that the marking (Marking) on the upper portion of the cover portion and preventing contact failure.
KR10-2001-0074752A 2001-11-28 2001-11-28 Method for preventing a bad contact and an assembly process reduction in semiconductor package KR100438404B1 (en)

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