KR20030039913A - Algorithm for embodying a shift register in software - Google Patents

Abstract

PURPOSE: A software implementation algorithm of a shift register is provided to reduce a waste of a memory and reduce the number of iterative statements required as a degree of primitive polynomial. CONSTITUTION: The number of variables is calculated, variables for storing the 'n' number of LFSR(Linear Feedback Shift Register) values and new value are calculated, and a temp to be stored is declared and a temporary variable is declared(30). The 'n' number of values given as an initial value is assigned to the variables for the storing the LFSR values and stored, and the left memory portion of the remaining variables are filled with '0'(31). The variables for storing the 'n' number of LFSR values are stored in a memory of a temporary variable sequentially using a memory shift calculation and an exclusive OR operation according to bits, combines the variables for storing the 'n' number of LFSR values, and stores the variables in a memory of a temporary variable sequentially(32). Temps for storing the 'n' number of LFSR values are calculated(33). A variable substitution is executed for updating new LFSR values(34). The above stages(32-34) are repeated until an output of a wanted bit is obtained(35).

Description

Algorithm for embodying a shift register in software

TECHNICAL FIELD The present invention relates to algorithms for implementing shift registers in software, and more particularly, to software implementation algorithms for LFSR and FCSR that are used as representative generation logic for stream ciphers.

Linear Feedback Shift Registers (LFSRs) and Feedback Carry Shift Registers (FCSRs) are logics that represent stream ciphers and are used in many fields because they provide a simple structure and mathematically high cycles. LFSR and FCSR are known to be very efficient because they can achieve 1-bit output on one clock with low gate complexity when implemented in hardware, but in software, they involve moving each bit repeatedly. Not only does it show very slow speeds, but at least 8 bits of data structures must be used to represent 1 bit of information, which is a waste of memory.

The basic logic of LFSR and FCSR is as follows.

Basic logic of LFSR

The nth order LFSR defined above the finite sieve GF (2) is generated from Equation 1 below, which is the nth order primitive polynomial above the GF (2).

From the given initial value n bits, we can get the output of consecutive 2 ⁿ -1 bits, and the k th bit can be obtained from the previous n bits. That is, the relationship as shown in Equation 2 below is satisfied.

From here, Denotes a bitwise exclusive OR operation, and an operation method of the LFSR is represented as shown in FIG. 1.

A conventional algorithm for implementing the LFSR generated by the primitive polynomial f (x) of Equation 1 in software will now be described with reference to FIG. 2.

The conventional algorithm for implementing LFSR in software consists of four steps.

Algorithm 1 Conventional Algorithm for Implementing LFSR in Software

Step 1 (Declare Variable): Declare an array A [] of size n to store n LFSR values and a Temp variable to store the new value.

Step 2 (initial value assignment): assigns n initial values of LFSR to array A []. This part, along with the variable declaration part, is executed only once, regardless of the number of output sequences.

Step 3 (Calculate New Value): A new term is generated from Equation 2 and stored in the temp variable.

Step 4 (variable substitution): move the values stored in the array A [] by one term to update the register of the new LFSR as shown in FIG. 1, and add the new value to the last A [n-1] th term. Save the Temp.

Step 5 : When the step 4 (variable substitution) process is completed, a new LFSR 1 bit is generated, and the steps 3 and 4 are repeated to obtain an output of a desired bit.

However, when using the conventional algorithm as described above, in step 1, variables corresponding to the order of the primitive polynomial should be declared. Therefore, the actual amount of information in one term of the LFSR is 1 bit, but in most programming languages, it is only necessary to store it in a data structure having a size of at least 8 bits. In addition, in step 4, in order to generate one bit of LFSR, variable substitution of the order of the primitive polynomial should be performed.

Basic Logic of FCSR

If binary expansion is given to a prime number q other than 2 as shown in Equation 3 below, the FCSR having q as the number of connections is composed of r registers and a memory m.

The value of the register Called memory In this case, the generation method of the FCSR at time k is expressed as shown in FIG. 3.

Step 10 : Integer sum is expressed by the following equation (4) Obtain

Step 11 : Move the contents of the register one space to the right.

Step 12 : Replace (mod 2) with the top register of the shift register.

Step 13 : Memory of Change to

Next, a conventional algorithm for implementing the FCSR generated by the connection number q of Equation 3 in software will be described with reference to FIG. 4.

The conventional algorithm for implementing FCSR in software consists of five steps.

Algorithm 2 Conventional Algorithm for Implementing FCSR in Software

Step 20 (Declare Variable): Declare an array A [] of size n to store n FCSR values, and a Temp variable and a memory variable M to calculate and store the new value.

Step 21 (Initial Value Allocation): Assigns n initial values of FCSR to array A [] and an initial memory value to variable M.

Step 22 (Calculate New Value): A new term is generated from a relation such as Equation 4 and stored in a Temp variable.

Step 23 (variable substitution): move the values stored in the array A [] by one term to update the register of the new FCSR as shown in FIG.

Step 24 (calculate new term and update M value): calculate A [n-1] = Temp (mod 2) and calculate M = (Temp-A [n-1]) / 2.

Step 25 : When step 24 (new term calculation and M value update) is completed, a new FCSR 1 bit is generated in A [n-1], and the process of steps 22 to 24 until an output of a desired bit is obtained. Repeat the process.

However, when using the conventional method as described above, as in the case of the LFSR, the waste of memory increases, and there is a disadvantage that an inefficient loop is used.

Accordingly, an object of the present invention is to provide a fast software implementation algorithm of LFSR and FCSR that can solve the above-mentioned disadvantages by reducing the number of unnecessary loops and the number of iterations required by the order of primitive polynomials.

The software implementation algorithm of the shift register according to the present invention for achieving the above object, after calculating the number (k) of the variable, the variable for storing the n LFSR value and the new value to declare the temp to store and store the temporary variable A first step of declaring a second value, a second step of filling the left memory part of the remaining variable with zero after assigning n values given as initial values to a variable for storing an LFSR value, and storing n LFSR values A third step of sequentially storing the variable to be stored in the memory of the temporary variable using a memory shift operation and an exclusive OR operation for each bit, and then sequentially storing the variable for storing n LFSR values in the memory of the temporary variable And a fourth step of calculating a temp to store the n LFSR values, and performing variable substitution to update the new LFSR values. And 5, characterized in that formed by until you get the desired output of the bit a sixth step of proceeding the third to repeat the process of the fifth step.

In addition, the software implementation algorithm of another shift register according to the present invention calculates the number of variables (k) and then calculates variables for storing n FCSR values, memory variables for storing memory values, and temporary variables for calculating new values. The first step of declaring a variable required for declaring and dividing and storing values stored in a variable for storing n FCSR values, and assigning and storing n values given as initial values into a variable for storing n FCSR values. After filling the left memory part of the remaining variable with 0, the second step of storing the memory value given as the initial value in the memory variable and shifting the memory variable to the left, and dividing the initial value stored in the initial variable into four variables After calculating the temporary variable of the LFSR using the third step of storing and the partitioned variables generated in the third step A fifth step of adding and storing the calculated temporary variable as an integer operation; and a fifth step of sequentially adding the memory updated in the previous term to the integer sum to generate a new term of the FCSR, for the variables stored in the temporary variables. A sixth step of updating a second value from the right of the memory storing each integer sum to a memory value, a seventh step of obtaining a new 32-bit FCSR value and then substituting a variable to obtain the next 32 bits; And an eighth step of repeating the processes of the fourth and seventh steps until an output of a desired bit is obtained.

1 is a generation structure diagram illustrating an operation method of an LFSR.

2 is a flow diagram of a conventional algorithm for implementing software of LFSR.

3 is a generation structure diagram showing an operation method of FCSR.

4 is a flow diagram of a conventional algorithm for implementing software of FCSR.

5 is a flowchart illustrating a software implementation algorithm of the LFSR in accordance with the present invention.

6 is a state diagram of a memory when the algorithm of the present invention is applied to a software implementation of a particular LFSR.

7 is a flowchart illustrating a software implementation algorithm of FCSR in accordance with the present invention.

FIG. 8 is an exemplary view for explaining step 42 of FIG. 7. FIG.

9 is a flowchart for explaining step 44 of FIG.

According to the present invention, 32 bits of 32-bit data type variables contain 32 pieces of information and generate 32 bits of LFSR and FCSR by one algorithm operation, and dramatically reduce the number of iterations. Then, the software implementation algorithm of the LFSR and FCSR proposed in the present invention will be described in detail with reference to the accompanying drawings.

5 is a flowchart illustrating a software implementation algorithm of the LFSR according to the present invention.

Assume that the number of degrees of the primitive polynomial that produces the LFSR is n and the number of taps is t. For convenience of description, the raw polynomial of Equation 1 is expressed by Equation 5 below by expressing only the sum of terms whose coefficients are not zero.

(0 = n ₁ <n ₂ <... <n _t = n)

Then, the relational expression of LFSR {a _i } generated by Equation 5 is expressed as Equation 6 below.

(k = 0, 1, 2, ....)

[Algorithm 3] Algorithm of the Invention for Implementing LFSR in Software

Step 30 : Declare a Variable

① Calculate

Calculate the number of variables to store n LFSR values. [a] means the maximum integer less than or equal to a. Since we will store 32 n LFSR values in one variable, we need as many as k variables, and this process does not appear in the actual algorithm.

② Declare 32-bit variables A ₁ , A ₂ , ...., A _k , and Temp.

Declare a variable A _i (1≤i≤k) for storing n LFSR values and a temp to store the new value. The size of the variable can be 16, 32, 64, etc. However, considering the current processor environment and the order of the LFSR being used, it is most appropriate to use a 32-bit variable.

③ Declare 32-bit variables T ₁ , T ₂ , ....., T _t-1 .

If the following step 32 is included in the algorithm, t-1 temporary variables are declared.

Step 31 : Set Initial Value

① Stores n values a ₀ , a ₁ , ....., a _n-1 given as initial values in A ₁ , A ₂ , ....., A _k .

To the far right in the memory 32 of the A _k, the value of a _n-1, is sequentially assigned to the 32 value in each memory of A _k to a value of a _n-32 substituted into the left-most memory.

In a similar way, the values of a _i are sequentially assigned to A _k-1 , A _k-2 , ....., A ₁ .

② assignment to a value of _0, and the left portion of memory of the remaining A ₁ is filled with zero.

Step 32 : calculate the temporary variable T _j (1≤j≤t-1)

① By using A ₁ , A ₂ , ....., A _k as the memory shift operation and the bitwise exclusive OR (XOR) operation, a _n1 (= a ₀ ) is located at the far left of the memory in T ₁ Let a _{n1 + 31} (= a ₃₁ ) be stored sequentially. This process can be solved by two memory shift operations and one exclusive OR operation.

② a method similar to the A _1, A _2, ....., by suitably combining the A _k in the memory of the left-most T _j (≤j≤t-1) is a _nj, the rightmost a _{nj + 31} sequentially To be stored.

Step 33 : calculate temp

① Calculate Temp using Equation 7 below.

② The new 32 LFSR values will be stored in Temp. If the equation for obtaining T _j of step 32 is directly substituted for each T _j (≦ _j ≦ t−1) in Equation 7, the process of step 32 may be excluded from the algorithm. In that case, the operation speed is not affected, but the amount of memory used can be reduced.

Step 34 : Replace Variables

① Variable substitution is performed as shown in Equation 8 below to update new LFSR values.

A ₁ = A ₂ , A ₂ = A ₃ , ....., A _k-1 = A _k , A _k = Temp

Step 35 : When the process of step 34 is completed, a new LFSR 32 bit is generated in A _k , and the initial value setting for generating the next 32 bit is completed. If you want to output m bits The process from step 32 to step 34 is repeated for each time. Where m represents the number of output bits.

Next, an embodiment of implementing the software of the LFSR using the above algorithm 3 will be described.

Primitive polynomials The source code that implements the LFSR generated by the C programming language is as follows. In this case, the order n of the primitive polynomial becomes 89 and the singular t becomes 5. Thus, the k value of step 30 is Becomes

#include <stdio.h>

void main ()

{

int i, Print_Number;

unsigned long A1, A2, A3, Temp; // step 30-②

unsigned long T1, T2, T3, T4; // step 30-③

A_1 = 0x01555555; // step 31-②

A_2 = 0x55555555; A_3 = 0x55555555; // step 31-①

Print_Number = 10000000; // specify the number of output bits

Print_Number = Print_Number / 32 + 1; // specify the number of loops

for (i = 0; i <Print_Number; i ++)

{

T1 = (A1 << 7) ^ (A2 >> 25); // step 32

T2 = (A1 << 10) ^ (A2 >> 22); // step 32

T3 = (A2 << 21) ^ (A3 >> 11); // step 32

T4 = (A2 << 25) ^ (A3 >> 7); // step 32

Temp = T1 ^ T2 ^ T3 ^ T4; // step 33

A1 = A2; A2 = A3; A3 = Temp; // step 34

printf ("% 08x", A3); // Print

}

}

When the program is executed once, the terms of the LFSR stored in the memory of the variables A1, A2, A3, T1, T2, T3, T4, and Temp are as shown in FIG. For convenience, a _i is represented by i in FIG. 6, and an “X” portion of A1 represents a portion where an actual data value is zero.

Next, the algorithm of the present invention for implementing FCSR in software is as follows.

The algorithm for implementing the FCSR in software has been realized by applying the algorithm for implementing the LFSR in software. However, since FCSR is more complicated to generate than LFSR, general algorithm cannot be configured, and it can be applied only to FCSR with some restrictions.

The number of concatenations that generate FCSRs can be similarly defined in degree and singularity, as in the LFSR's primitive polynomials. Assume that the order q of the coupling q is n and the singular t. For convenience of explanation, if the number of connections in Equation 3 is expressed only by the sum of terms whose coefficients are not zero, Equation 9 will be given.

(0 <n ₁ <n ₂ <..... <n _t = n)

Therefore, Equation 4 may be modified as in Equation 10 below.

The algorithm of the present invention for implementing FCSR in software is applicable only to the case where the number of connections q is 11 or less in Equation 9 and n ₁ is 32 or more. When FCSR is used in a real stream cipher, a decimal number of about 100 orders of magnitude is used. In this case, n ₁ is 32 or more, so there are many prime numbers. .

Hereinafter, a new software implementation algorithm of FCSR generated by the number of connections satisfying the above condition will be described with reference to the flowchart of FIG. 7. Descriptions overlapping with those described in the software implementation algorithm of the LFSR will be omitted.

[Algorithm 4] Algorithm of the Invention for Implementing FCSR in Software

Step 40 : Declare a Variable

① Calculate

② Declare 32 bit variables A ₁ , A ₂ , ....., A _k , T ₁ , T ₂ , T ₃ , T ₄ , M.

The process of declaring variables A _i (1≤i≤k) for storing n FCSR values, M for storing memory values, and temporary variables for partially calculating new values.

③ Declare 32-bit variables A ₁₁ , A ₁₂ , A _13, A _14, ....., A _k1 , A _k2 , A _k3 , A _k4 .

A _ij are variables necessary for dividing and storing the values stored in A _i in step 42 below.

Step 41 : Set Initial Value

① Set an initial value in the same manner as in step 31 of the software implementation algorithm of the LFSR.

② Store the given memory value m in M as the initial value, and shift M to the left by 28 times. That is, M = (M << 28).

Step 42 : Split Variable

① The initial variable A _i (1≤i≤k) is divided into four variables A _i1 , A _i2 , A _i3 and A _i4 by performing the following operation.

-A _i1 (A _i >> 3) & 0x11111111

-A _i2 (A _i >> 2) & 0x11111111

-A _i3 (A _i >> 1) & 0x11111111

-A _i2 (A _i ) & 0x11111111

Here, the operator & means logical bitwise, and (B >> j) denotes an operation of memory shifting the variable B to the right by j bits.

In step 42, 32 initial values stored in A _i are divided and stored in four variables, each of eight. At this time, the eight initial values are placed only in 4th, 8th, 12th, 16th, 20th, 24th, 28th and 32nd positions from the left of the 32 memory spaces. The bits in this location are referred to here as MSB (Most Significant Bit).

When assuming that the initial values of the variables A ₁ from a ₀ to a ₃₁ stored and hayeoteul the variable division with respect to A ₁ shown in Fig. 8 indicates the initial value is stored for each variable. In Figure 8 it was simply denote the sequence a _i a i.

Step 43 : Calculate T ₁ , T ₂ , T ₃ , T ₄

① Using A _ij generated in step 42, T _1j (1 ≦ j ≦ t-1) is calculated in a similar manner to step 32 of the software implementation algorithm of the LFSR. In this case, however, since the actual data is stored only in the MSBs of A _ij , step 32 of the software implementation algorithm of the LFSR is slightly modified so that the T _1j variables are placed only in eight significant bits. That is, in the case of LFSR, the leftmost bit of the memory is transformed to mean the leftmost of eight 'critical bits' in the case of FCSR.

② Add T _1j (1 ≦ j ≦ t-1) generated in ① to an integer operation and store in T ₁ .

③ The above steps ① and ② apply similarly to T ₂ , T ₃ and T ₄ .

In order to prevent unnecessary waste of the memory, the process of ① is included in the process of ② in the same manner as described in Step 33 of Algorithm 3, rather than included in the actual algorithm.

In the process of ②, it is assumed that the number of stages for generating the FCSR is 11 or less, and since the memory space occupied by each term stored in T _1j (1 ≦ j ≦ t-1) is 4 bits, 'significant bits' Carry due to addition between them does not affect the other bits.

In step 43, the following equation 11 is calculated and stored in T ₁ , T ₂ , T ₃ , and T ₄ of the calculation process of Equation 4 above.

Step 44 : Calculate and update M value

To create a new term a _k of FCSR, we update m _k-1 which is updated in the previous term. You need to add to, which proceeds sequentially for the 32 variables stored in the T ₁ , T ₂ , T ₃ , and T ₄ variables. This process is represented in FIG. In FIG. 9, the operation symbols S1 to S4 denote integer addition of mod 2 ³² , the symbol & denotes a logical bit-by-bit, and C [j] (0 ≦ j ≦ 7). It is expressed as

C [j] = (0xe0000000) >> (j × 4), (0 ≤ j ≤ 7)

That is, C [0] = 0xe0000000 and C [7] = 0x0000000e.

On the other hand, when j = 7, the {(& C [j]) >> 5} operation is transformed into {(& C [j]) << 27} to fit the meaning.

After the step 44, the T _i variables are expressed in Equation 4 every 4 bits. The value will be saved.

In the algorithm of FIG. 9, the value of M _i is equal to m _i . It is constructed by paying attention to the coefficient of the first term when the value of binary is expanded. That is, each The value of the second memory from the right of the 4-bit memory where the value is stored is taken as the M value.

Step 45 : Replace Variables and Create New Terms

To get the new 32-bit FCSR value and replace the variable to get the next 32 bits:

① A _i1 = A _{(i + 1) 1} , A _i2 = A _{(i + 1) 2} , A _i3 = A _{(i + 1) 3} , A _i4 = A _{(i + 1) 4} (1 ≤ i ≤ k -One)

② A _kj = T _j & 0x11111 111 (1 ≤ j ≤ 4)

③ A _k = (A _k1 ≪ 3) (A _k2 ≪ 2) (A _k3 ≪ 1) (A _k4 )

Step 46 : When the process of step 45 is completed, a new FCSR 32 bits are generated in A _k , and the initial value setting for generating the next 32 bits is completed. If you want to output m bits Repeat steps 43 to 45 for each time. (Originally, steps 3 to 6, that is, steps 42 to 45 are repeated, but in FIG. 7, the steps 43 to 45 are repeated. Please confirm this part.)

An embodiment of implementing FCSR in software using Algorithm 4 as described above will now be described.

The source code that implements the FCSR generated by the number of connections q = 2 ⁸⁹ +2 ⁸⁶ +2 ⁴³ +2 ³⁹ -1 in C programming language is as follows.

#include <stdio.h>

void main ()

{

int i, j, Print_Number;

unsigned long A1, A2, A3, T1, T2, T3, T4, M; // step 40-②

unsigned long A11, A12, A13, A14, A21, A22, A23, A24

A31, A32, A33, A34; // step 40-③

unsigned long int K, C [8];

C [0] = 0xe0000000; // C []: set the value of m

C [1] = 0x0e000000; // used to update

C [2] = 0x00e00000; // use

C [3] = 0x000e0000;

C [4] = 0x0000e000;

C [5] = 0x00000e00;

C [6] = 0x000000e0;

C [7] = 0x0000000e;

K = 0x11111111; // used for variable partitioning

A_1 = 0x55555555; // step 41

A_2 = 0x55555555;

A_3 = 0x55555555;

M = 0x00000000 << 28;

Print_Number = 10000000; // specify the number of output bits

Print_Number = Print_Number / 32 + 1; // specify the number of loops

A11 = (A1 >> 3) &K; A12 = (A1 >> 2) &K; // step 42

A13 = (A1 >> 1) &K; A14 = (A1) &K; // step 42

A21 = (A2 >> 3) &K; A22 = (A2 >> 2) &K; // step 42

A23 = (A2 >> 1) &K; A24 = (A2) &K; // step 42

A31 = (A3 >> 3) &K; A32 = (A3 >> 2) &K; // step 42

A33 = (A3 >> 1) &K; A34 = (A3) &K; // step 42

for (i = 0; i <Print_Number; i ++)

{

T1 = (A14 << 4) + (A24 >> 28) + (A13 << 8) + (A23 >> 24) // step 43

+ (A22 << 20) + (A32 >> 12) + (A22 << 24) + (A32 >> 8) // step 43

T2 = (A11 << 8) + (A21 >> 24) + (A14 << 8) + (A24 >> 24) // step 43

+ (A23 << 20) + (A33 >> 12) + (A23 << 24) + (A33 >> 8) // step 43

T3 = (A12 << 8) + (A22 >> 24) + (A11 << 12) + (A21 >> 20) // step 43

+ (A24 << 20) + (A34 >> 12) + (A24 << 24) + (A34 >> 8) // step 43

T4 = (A13 << 8) + (A23 >> 24) + (A12 << 12) + (A22 >> 20) // step 43

+ (A22 << 24) + (A31 >> 8) + (A22 << 28) + (A31 >> 4) // step 43

for (j = 0; j <7; j ++)

{

T1 = T1 + M; // step 44

M = (T1 & C [j]) >> 1; // step 44

T2 = T2 + M; // step 44

M = (T2 & C [j]) >> 1; // step 44

T3 = T3 + M; // step 44

M = (T3 & C [j]) >> 1; // step 44

T4 = T4 + M; // step 44

M = (T4 & C [j]) >> 5; // step 44

}

T1 = T1 + M; // step 44

M = (T1 & C [j]) >> 1; // step 44

T2 = T2 + M; // step 44

M = (T2 & C [j]) >> 1; // step 44

T3 = T3 + M; // step 44

M = (T3 & C [j]) >> 1; // step 44

T4 = T4 + M; // step 44

M = (T4 & C [j]) << 27; // step 44

A11 = A21; A12 = A22; A13 = A23; A14 = A24; // step 45-①

A21 = A31; A22 = A32; A23 = A33; A24 = A34; // step 45-①

A31 = T1 &K; A32 = T2 &K; // step 45-②

A33 = T3 &K; A34 = T4 &K; // step 45-②

A3 = (A31 << 3) ^ (A32 << 2) ^ (A33 << 1) ^ A34; // step 45-③

printf ("% 08x", A3); // Print

}

}

As described above, the present invention reduces unnecessary memory waste and the number of iterations that were required by the order of the primitive polynomial. Therefore, the algorithm can be implemented 30 to 300 times faster than the software implementation of the conventional FCSR and LFSR, and the memory required to implement the algorithm is also reduced.

Stream ciphers are actually transmitted in 16 or 32 bit units in most application environments. The existing LFSR software implementation, which is generated by 1 bit, is stored in memory until data as much as the transmission unit is created. And needed an algorithm. However, using the algorithm of the present invention as the internal logic of the stream cipher effectively solves this problem. In addition, by applying the same algorithm to the hardware, it is possible to implement a high speed in hardware.

Claims (6)

A first step of declaring a variable to store the number of LFSR values after calculating the number of variables (k), declaring a temp to store the new value, and declaring a temporary variable; A second step of filling the left memory part of the remaining variable with zero by assigning n values given as initial values to a variable for storing the LFSR value, and The variables for storing the n LFSR values are sequentially stored in the memory of the temporary variable by using a memory shift operation and an exclusive OR operation for each bit, and then the variables for storing the n LFSR values are combined to store the memory of the temporary variable. A third step of storing sequentially in a fourth step of calculating a temp for storing n LFSR values, A fifth step of performing variable substitution to update new LFSR values; And a sixth step of repeating the processes of the third to fifth steps until an output of a desired bit is obtained. The method of claim 1, The number k of the variable in the first step is calculated by the following equation (13). After calculating the number of variables (k), declare a variable to store n FCSR values, a memory variable to store memory values, and temporary variables to calculate and store a new value, and store the variable to store the n FCSR values. A first step of declaring a variable necessary for dividing and storing the values; The n values given as initial values are stored in the variables for storing the n FCSR values, the left memory portion of the remaining variables are filled with 0, and the memory values given as initial values are stored in the memory variables. A second step of memory shifting to the left; A third step of dividing and storing the initial value stored in the initial variable into four variables; A fourth step of calculating a temporary variable of the LFSR using the divided variables generated in the third step and storing the calculated temporary variable by adding it to an integer operation; A fifth step of sequentially adding the memory updated in the previous term to the integer sum to generate a new term of the FCSR, for the variables stored in the temporary variables; A sixth step of updating a second value from the right of the memory in which each integer sum is stored to the memory value; A seventh step of obtaining a new 32-bit FCSR value and substituting a variable to obtain the next 32 bits, And an eighth step of repeating the steps of the fourth and seventh steps until an output of a desired bit is obtained. The method of claim 3, wherein The number k of the variable in the first step is calculated by the following equation (14). The method of claim 3, wherein And wherein said partitioning of said variable in said third step is performed as follows. ① A _i1 (A _i >> 3) & 0x11111111 ② A _i2 (A _i >> 2) & 0x11111111 ③ A _i3 (A _i >> 1) & 0x11111111 ④ A _i2 (A _i ) & 0x11111111 The method of claim 3, wherein The variable substitution of the seventh step is performed as follows. ① A _i1 = A _{(i + 1) 1} , A _i2 = A _{(i + 1) 2} , A _i3 = A _{(i + 1) 3} , A _i4 = A _{(i + 1) 4} (1 ≤ i ≤ k -One) ② A _kj = T _j & 0x11111 111 (1 ≤ j ≤ 4) ③ A _k = (A _k1 ≪ 3) (A _k2 ≪ 2) (A _k3 ≪ 1) (A _k4 )