KR20030039738A - Fault tolerance apparatus and the method for processor duplication in wireless communication system - Google Patents

Abstract

PURPOSE: A device of permitting a defect for processor duplexing in a wireless communication system is provided to construct a defect permitting system based on interworking between tasks, and to prevent a processing function from being deteriorated owing to overhead of a duplexing function, thereby precisely constructing a dump and backup function. CONSTITUTION: A defect permitting control module(41) generates a defect permitting control signal for processor duplexing according to a control command of a task control module. A transmission data control module(42) separates dump and backup data into packet units according to a transmission environment of a duplexing path before transmitting the data to a standby board from an active board, based on the defect permitting control signal, and attaches sequence numbers for reassembling the data, then adds header information corresponding to each packet. A data transmission module(43) transmits the dump and backup data reconfigured according to the transmission data control module(42) by managing the duplexing path and controlling an Ethernet transmission buffer.

Description

Fault tolerance apparatus and the method for processor duplication in wireless communication system

The present invention relates to a fault-tolerant technology for processor duplication in a wireless communication system. In particular, the present invention relates to a duplication of a call processing process for controlling various types of call processing requests of a radio network controller (RNC) in a next generation mobile communication system (IMT-2000). In order to simplify the synchronization functions and procedures during data backup and to facilitate the implementation, a fault-tolerant apparatus and method and method thereof for redundancy in a wireless communication system are not required. A computer readable recording medium having recorded thereon a program for realization.

At present, the processor redundancy schemes such as Active-Standby, Master-Assistant, and Load-Sharing have been studied for the fault tolerance of the processor. Devices such as switching systems generally use active-standby processor redundancy to increase processor reliability. This architecture gives the two processors the same storage and prepares for a switchover, recovers the standby processor to enter the take-over phase after the actual active-switchover, and then transitions back to the preparation phase. It goes through a re-ready phase of recovering.

In general, depending on the preparation and re-preparation phase of preparing for active-standby-switch, the method of concurrent processing, concurrent write, and state checkpointing for current processor redundancy The system is implemented by applying technology such as state check-pointing method and automatic check pointing method.

In other words, the simultaneous operation method requires that the active processor and the standby processor execute the same code in separate hardware modules so that when one module requires a fault transfer, only the external communication path of another module needs to be changed. Real time fault tolerance is possible. However, there is a constraint that the active board and the standby board must be started at the same time. If the standby board operates late, a process of collectively replicating the storage of the active board is required. In RNC, the basic unit of execution is call processing message, and the context of each task can be inconsistent due to some temporary defect. Can be. In addition, the simultaneous operation can provide a completely continuous service when switching, but it is difficult to synchronize the two processors.

Simultaneous writes change the memory location of the active board when the active board changes its contents. This requires special hardware that uses shared storage or supports concurrent writes. When switching is required due to a defect, only the context of the active processor is copied, applied to its own context, and activated, and the work performed by the active processor is continuously performed. This approach results in dual down because the active processor's misbehavior is left to the standby processor, which makes it difficult to configure the hardware for concurrent writes and adds more cost.

The state checkpointing method is a result of the operation of the active processor, and transmits state information to the standby processor when the state changes. The subprocessor stores state information transmitted by the main processor, and when an error or defect occurs during the operation of the active process, the standby processor attempts to recover based on the latest checkpoint data. The recovery rate is high because each important task has status information, but for this purpose, a dedicated task for redundancy is supported by the operating system and inter-process communication (IPC), and the context information such as the change history of the storage location, context information such as registers, and the input queue ( Since the contents of the input queue must be written to a log and transmitted to the standby processor, the overhead of the redundancy module is large and difficult to implement.

The automatic checkpointing method is a method in which an operating system that supports redundancy automatically generates log information and passes it to a standby processor. This has been proposed to reduce the burden of implementing the status checkpointing method. However, the management cost is high because of the cost increase to build a new operating system supporting this, and the amount of data transferred to the standby processor is soaring.

Therefore, the above schemes have a problem in that synchronization problems, redundancy down, and overhead problems of a dedicated dedicated application program (AP) have a great influence on the system implementation.

The present invention has been proposed to solve the above problems, to build a fault-tolerant system based on the interworking between tasks, thereby preventing the degradation of processing of the call processing processor due to the overhead of redundancy function, dump and It is an object of the present invention to provide a fault-tolerant device for processor redundancy and a method thereof, and a computer-readable recording medium having recorded thereon a program for realizing the method.

1A is an exemplary configuration diagram of an interprocessor redundancy system to which the present invention is applied.

FIG. 1B illustrates an embodiment configuration of a fault tolerance module in the active board of FIG. 1A.

1C is a diagram illustrating an embodiment of a fault-tolerant module in the standby board of FIG. 1A.

FIG. 2 is a flowchart illustrating a process of setting an active / standby board when driving FIG. 1A.

3 is a diagram illustrating an embodiment of a fault-tolerant method for processor duplication according to the present invention;

4 is a flow diagram of an embodiment of a fault tolerance method for processor redundancy in accordance with the present invention.

5 is a diagram illustrating a message processing structure for deleting and reconstructing a message according to the present invention.

* Explanation of symbols for the main parts of the drawings

11, 21: fault tolerance module 41: fault tolerance control module

42: transmission data control module 43: data transmission module

44: data receiving module 45: receiving data transmission module

46: message management module

The present invention for achieving the above object, the fault tolerance device of the active board for processor duplication in a wireless communication system, the fault tolerance to generate a fault-tolerant control signal for processor duplication in accordance with a control command from the task control module Control means; According to the fault-tolerant control signal, before dump and backup data generated in the active board are transferred to the standby board, the packet is separated into packet units according to the transmission environment of the redundant path, and a sequence number is attached to each other so that they can be recombined. Transmission data control means for adding header information corresponding to the packet; And data transmission means for managing the redundancy path and controlling the Ethernet transmission buffer according to the fault tolerance control signal to transmit dump and backup data reconstructed by the transmission data control means.

In addition, the present invention, a fault-tolerant device of the standby board for processor redundancy in a wireless communication system, comprising: data receiving means for managing a redundancy path and controlling an Ethernet receive buffer to receive dump and backup data transmitted from an active board; In order to store the dump and backup data of the active board received through the data receiving means in a dedicated memory of the task of the standby board, the header information is deleted from the received packet and the original data is reconstructed according to the sequence number. Receiving data control means; And deleting the same message from the message table of the standby board when the backup of the data generated as a result of the message processing of the active board is completed in order to manage the external message received by the standby board. And a message management means for transmitting the message remaining in the message table to the task of the standby board in the activated state and restoring to a state before the occurrence of a defect when the transfer is performed.

In addition, the present invention provides a fault tolerance method for processor duplication applied to a wireless communication system, comprising: a first step of dumping information related to call processing on a task basis from an active board to a standby board; A second step in which each task stores the contents of the memory changed according to a message processing result in a redundant transmission buffer; A third step of transmitting data stored in the redundant transmission buffer to the standby board using the related information under control of each task, and storing the data in the redundant reception buffer; A fourth step of storing data stored in the redundant reception buffer in a corresponding task dedicated memory of the standby board; And a fifth step of deleting the same message from the message table of the standby board by using the header information of the transmitted data.

The present invention also provides a wireless communication system including a processor, comprising: a first function of dumping information related to call processing on a task basis from an active board to a standby board; A second function in which each task stores the contents of the memory changed according to a message processing result in a redundant transmission buffer; A third function of transmitting data stored in the redundant transmission buffer to the standby board under the control of each task and storing the data in the redundant reception buffer; A fourth function of storing data stored in the redundant reception buffer in a corresponding task dedicated memory of the standby board; And a computer readable recording medium having recorded thereon a program for realizing a fifth function of deleting the same message from the message table of the standby board using the header information of the transmitted data.

The present invention proposes a task-based fault tolerance scheme that overcomes synchronization issues, dual down issues, and the like in terms of real-time message handling and dumping, and synchronization schemes. This method handles synchronization between processors on a message-by-message basis without requiring register and processor state information, so that the synchronization function is simple and easy to implement. In addition, since the malfunctioning information is not transmitted to the standby board, the redundancy down problem can be solved.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A is an exemplary configuration diagram of an interprocessor redundancy system to which the present invention is applied.

As shown in FIG. 1A, task 12 of active board 10 processes a message sent from interprocessor communication module (IPC) 14 via ATM processing module 15, and as a result of the processing. When the generated backup / dump data is transferred to the fault-tolerant module (FTM) 11 of the active board 10, the fault-tolerant module 11 manages the task 12. ) Is transmitted to the standby board 20 by the control command of the control panel.

Accordingly, the fault-tolerant module 21 of the standby board 20 receives the backup / dump data transmitted through the active board 10 and stores the backup / dump data in the memory 23 of the task 22 and the ATM processing module 25. The external message (the same message as the message sent to the active board) input from the interprocessor communication module (IPC) 24 to the standby board 20 is temporarily stored in the IPC buffer via the active board 10. The message information stored in the header of the backup data transmitted to the standby board 20 is received, and if it is the same message, it is deleted.

The input message information is used to determine the order of messages received through the interprocessor communication modules 14 and 24, and the backup data is used to update the memory of the application programs and delete the same message.

The data dump is to match the state of the dedicated boards 13 and the dedicated memories 13 and 23 of the standby board 20 at the initial stage when the standby board 20 is mounted. ).

In the fault-tolerant structure of the present invention, the task control module 26 manages backup data until the last data is received, and if the error occurs in the active board 10 before the last data is received, the data is transferred to the task control module ( 26) has a basic structure of deleting from the redundant receive buffer. In order to efficiently implement this, management of backup data is performed for each task, and the task control modules 16 and 26 are constructed to manage start addresses and sizes of areas to be backed up.

In order to deliver a series of backup data registered in the task control module 16 to the standby board 20 by the backup message of the task 12 and the control command, the fault tolerance module 11 of the active board 10 Once the data is separated according to the size of the packet (1024 bytes), they are numbered so that they can be recombined. Then, the transfer to the standby board 20.

Upon receiving the backup data, the fault-tolerant module 21 of the standby board 20 transfers the packets transferred from the active board 10 to reconstruct the data, as in the active board 10, the redundant buffer of the task control module 26. Manage using That is, the task control module 26 manages the packet transferred from the active board 10 until data is reconstructed in the fault-tolerant module 21 of the standby board 20.

When the last packet of data arrives, synchronization is maintained by storing the backup data in the same memory 23 as the start address. If it transfers before the last packet is delivered, the synchronization is effectively maintained by deleting this incomplete data.

FIG. 1B is a diagram illustrating an embodiment of a fault-tolerant module in the active board of FIG. 1A.

As shown in FIG. 1B, the fault tolerance module 11 in the active board 10 generates, in accordance with a control command from the task control module 16, fault tolerance control that generates a fault tolerance control signal for processor redundancy. According to the module 41 and the fault-tolerant control signal of the fault-tolerant control module 41, before the dump and backup data generated by the active board 10 is transferred to the standby board 20, the transmission environment of the redundant pass is adapted. In accordance with the fault-tolerant control signal of the transmission data control module 42 and the fault-tolerant control module 41, which are separated into packet units, add sequence numbers so that they can be recombined, and add header information corresponding to each packet. And a data transfer module 43 for managing the redundant paths and controlling the Ethernet transmit buffer to transmit the dump and backup data reconstructed by the transmit data control module 42.

FIG. 1C is a diagram illustrating an embodiment of a fault-tolerant module in the standby board of FIG. 1A.

As shown in FIG. 1C, the fault-tolerant module 21 in the standby board 20 manages the redundancy path and controls the Ethernet receive buffer to receive dump and backup data sent from the active board 10. In order to store dump and backup data of the active board 10 received through the receiving module 44 and the data receiving module 44 in the dedicated memory 23 of the corresponding task 22 of the standby board 20, The receiving data control module 45 deletes header information from the received packet and reconstructs original data according to the sequence number, and manages an external message received by the standby board 20. When the backup of the data generated as a result of message processing is completed, the same message is deleted from the message table of the standby board 20, and the message remaining in the message table is transferred if it is switched over by the fault of the active board 10. It includes a message management module 46 to transfer them to the task (22) of the standby board 20 is activated state recovery to the state before the fault occurs.

FIG. 2 is a flowchart illustrating a process of setting an active / standby board when driving FIG. 1A.

As shown in FIG. 2, when the active / standby board is mounted (211,221), each active / standby board state is predetermined according to the mounted position.

That is, the board mounted on the A-side 210 is determined to be an active abnormal state, and the board mounted on the B-side 220 is determined to be a standby abnormal state ( 212,222). Each board checks the hardware state of the other board through the communication link (213, 223). The board receives the hardware status signal of the other board and checks it. In this process, the board is determined to be in an active normal or standby normal state (214, 224). If two boards are simultaneously activated using this information, the board mounted on the A-side 210 is determined as the active board 10, and the board mounted on the B-side 220 is determined as the standby board 20.

Thus, once the operation mode is determined, each board registers call processing related tasks (215 and 225). During registration, the task 22 of the standby board 20 sends a data dump request message to request the data dump to the same task 12 of the active board 10 individually (226). The task 12 of the active board 10 having received this transmits the dump data to the standby board 20 (216).

Subsequently, the task 12 which has completed the dump periodically performs a message processing process, and as a result, if the memory 13 has been changed, the backup data of the changed memory is transferred to the standby board 20 according to the control condition ( 217).

3 is a diagram illustrating an example of a fault-tolerant method for processor duplication according to the present invention. The duplication buffer is managed by a task control module and is responsible for real-time processing of a message.

As shown in Fig. 3, the contents of the task dedicated memory 31 changed as a result of the message processing of the task of the active board are stored in the redundant transmission buffer 32 in real time under the control of the task control module. Message information is added to the header portion of the data stored in the redundant transmission buffer 32 to be stored in the Ethernet transmission buffer 33, and the Ethernet header is added again to transmit data to the standby board.

Subsequently, the transmitted data is stored in the Ethernet receive buffer 34 to remove the Ethernet header information, and stored in the redundant receive buffer 35. The data is stored in the dedicated memories 31 and 36 of the task by referring to the start address of the data in the header information of the data.

Thus, the use of redundant transmit / receive buffers 32 and 35 ensures real-time processing of messages during the dump. In general, to ensure data consistency between two boards, suspend message processing by suspending the task during a dump.

However, this disables real-time processing of the message, resulting in other overhead, such as an increase in response time.

Therefore, the present invention improves this by using the redundant buffer of the task control module to process the message in real time without causing inconsistency of data during the dump.

During the dump, the task is not held and processes internal and external messages. The data generated by the processing of the messages is used for interfacing with other tasks and users, and the generated data continues to be stored in the redundant transmission buffer 32 until the dump of the task is completed. Then, it manages these data until the dump of the task is completed. When the task having completed the dump transmits a completion signal to the task control module, the task control module receiving the dump transmits the data stored in the redundant transmission buffer 32 to the standby board in a batch. This allows messages to be processed in real time without causing data inconsistencies during the dump.

4 is a flowchart illustrating a fault tolerance method for processor duplication according to the present invention.

As shown in FIG. 4, the task-based fault tolerance method performs synchronization using a task to build a fault-tolerant system based on a task. The proposed method performs synchronization on a per-message basis, so there is no need for task status information and register values, compared to the conventional method.

That is, the task-based fault tolerance method registers its storage area with the fault tolerance modules 11 and 21 when the tasks loaded on the active board 10 and the standby board 20 are initialized. This process is performed by the active board 10 and the standby board 20 in the same procedure, looking at this process as follows.

First, when task A of the active board and the standby board receives each message A at the same time (411,421), the corresponding task A of the active board generates the backup data by processing the message, and stores the backup data in the task dedicated memory, When the contents of the memory change due to the processing result (412,413), the backup data (the changed history including the start address and size and information about the message) are temporarily stored in the redundant transmission buffer 32 of the task control module 16. (414).

In the standby board 20, the task attempts to process a message, but since the task is in a standby state, execution of the task is suspended (422), and the message is temporarily stored in the message table (423).

The task control module 16 of the active board 10 manages backup data for each task. When the task 12 calls a control command, the task control module 16 transmits the backup data to the fault-tolerant module 11 and the fault-tolerant module 11. The synchronization is performed by transmitting the data back to the fault-tolerant module 21 of the standby board 20 (415). The task uses control commands to manage the backups, giving synchronization flexibility.

The duplication buffer due to error diffusion is solved by using the duplication buffer of the task control module 26 of the standby board 20. Delaying the storage of the backup data generated as a result of message processing until the final data is transmitted from the active board 10, and when the final data arrives on the standby board 20, the memory 23 of the task 22 is stored. Store the data (424).

The message stored in the message table of the standby board 20 is deleted from the message table if it is the same message using the message information of the last data header transmitted to the standby board 20 (425).

5 is a diagram illustrating a message processing structure for deleting and reconstructing a message according to the present invention.

As shown in FIG. 5, the IPC call message 55 inputted in the same manner as the active board 10 is connected to a message buffer 52 (MSGBuf) 52 of the standby board 20. Each MSGBuf 52 is assigned one per task ID 53. At this time, the IPC call message 55 uses the buffer allocated from the IPC as it is, and MSGBuf manages only the pointer of the IPC call message 55.

In the data backup, if the standby board 20 receives the backup message included in the header information of the last packet from the active board 10, all messages involved in the backup of the data should be deleted from the MSGbuf 52. To do this, find the task id 53 associated with the backed up data, and find the corresponding MSGbuf 52 from this task id 53.

Then, among the messages connected to the MSGbuf 52, a message related to the backup of the data is found, and all the messages below this message are deleted. If the backup board does not receive the backup message and becomes the active board 10, the message is restored by restoring the data.

In order to solve the data loss problem during the data backup, the completion time of the backup is viewed as the time when the data generated as a result of the message processing are all stored in the memory of the task 22 of the standby board 20, and the storage is completed. The same message of the standby board 20 can be deleted only afterwards. If you fail to back it up, recover the lost data by running this message again.

On the other hand, when restoring the board, the messages in the MSGbuf 52 are sent to the task 22 and the messages are deleted from the MSGBuf 52. This operation is performed until there is no message in the MSGbuf 52, and then acts as an active board. This series of steps prevents the loss of associated data that was processed on the active board but could not be backed up.

The method of the present invention as described above may be implemented as a program and stored in a computer-readable recording medium (CD-ROM, RAM, ROM, floppy disk, hard disk, magneto-optical disk, etc.).

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention as described above has the effect that simple and accurate synchronization is possible using a fault-tolerant structure under the control of a task, and can be easily implemented in a system.

In addition, the present invention enables real-time message processing during a dump, and in the event of a catastrophic failure due to a malfunction, the related information is not transmitted to the related task of the standby board, thereby preventing the duplication down by preventing the spread of error data. In addition to this, data loss can be prevented, and this can achieve more accurate synchronization.

Claims (8)

In a fault-tolerant device of an active board for processor redundancy in a wireless communication system, Fault tolerance control means for generating a fault tolerance control signal for processor redundancy in accordance with a control command from the task control module; According to the fault-tolerant control signal, before dump and backup data generated in the active board are transferred to the standby board, the packet is separated into packet units according to the transmission environment of the redundant path, and a sequence number is attached to each other so that they can be recombined. Transmission data control means for adding header information corresponding to the packet; And Data transmission means for managing a redundant path and controlling an Ethernet transmission buffer according to the fault-tolerant control signal to transmit dump and backup data reconstructed by the transmission data control means. Device for fault tolerance of the active board for processor redundancy in a wireless communication system comprising a. In the fault tolerance device of the standby board for processor redundancy in a wireless communication system, Data receiving means for managing a redundant path and controlling an Ethernet receive buffer to receive dump and backup data transmitted from an active board; In order to store the dump and backup data of the active board received through the data receiving means in a dedicated memory of the task of the standby board, the header information is deleted from the received packet and the original data is reconstructed according to the sequence number. Receiving data control means; And In order to manage an external message received by the standby board, upon completion of the backup of the data generated as a result of the message processing of the active board, the same message is deleted from the message table of the standby board, and switched by a defect of the active board. Message management means for transmitting the remaining message in the message table to the task of the standby board in the activated state and restoring it to the state before the occurrence of the defect. Device for fault tolerance of the standby board for processor redundancy in a wireless communication system comprising a. In the defect tolerance method for processor duplication applied to a wireless communication system, Dumping information related to call processing on a task basis from an active board to a standby board; A second step in which each task stores the contents of the memory changed according to a message processing result in a redundant transmission buffer; A third step of transmitting data stored in the redundant transmission buffer to the standby board using the related information under control of each task, and storing the data in the redundant reception buffer; A fourth step of storing data stored in the redundant reception buffer in a corresponding task dedicated memory of the standby board; And A fifth step of deleting the same message from the message table of the standby board by using the header information of the transmitted data; A fault tolerance method for processor redundancy in a wireless communication system comprising a. The method of claim 3, wherein The first step is, In the wireless communication system, the data is temporarily stored using a duplication buffer of the task control module so as to process the message in real time during the dump, and transmitted to the standby board by the control command of the task after the dump is completed. Fault Tolerance Method The method according to claim 3 or 4, The message table, During the data backup, if the standby board receives the backup message included in the header information of the last packet from the active board, deletes all the messages involved in the backup of the data from the message buffer MSGbuf, and performs the task associated with the backed up data. It finds the ID, finds the corresponding message buffer from this task ID, finds the message that was involved in the backup of the data among the messages connected to the message buffer, deletes all the messages below, and transfers without receiving the backup message. If the data is restored, the data is restored by re-executing the message, and if data loss occurs during the data backup, the completion time of the backup is a point where all the data generated as a result of the message processing are stored in the corresponding task memory of the standby board. Only after the completion of viewing and saving If transfer does not back up, and if removed, the fault-tolerant method for a redundant processor in a wireless communication system, characterized in that to recover the lost data by performing this message again. The method of claim 5, The message table, When restoring the lost board, it transmits the messages in the message buffer (MSGbuf) to the task and deletes the message from the message buffer until there is no message in the message buffer, and then operates as the active board, Through this process, if the processing occurs on the active board, but the backup does not occur in the case of a fault tolerance method for processor redundancy in a wireless communication system, characterized in that to prevent the loss of related data. The method of claim 6, The standby board, The packet transmitted from the active board is managed through the task control module until the data is reconstructed in the fault-tolerant module receiving the backup data, and when the last packet of data arrives, the corresponding backup data is stored in the same memory as the start address. A method for fault tolerance for processor redundancy in a wireless communication system, characterized by storing and maintaining synchronization, and maintaining synchronization by deleting incomplete data when it is transferred before receiving the last packet. In a wireless communication system having a processor, A first function of dumping information related to call processing on a task basis from an active board to a standby board; A second function in which each task stores the contents of the memory changed according to a message processing result in a redundant transmission buffer; A third function of transmitting data stored in the redundant transmission buffer to the standby board under the control of each task and storing the data in the redundant reception buffer; A fourth function of storing data stored in the redundant reception buffer in a corresponding task dedicated memory of the standby board; And A fifth function of deleting the same message from the message table of the standby board by using the header information of the transmitted data A computer-readable recording medium having recorded thereon a program for realizing this.