KR20030037693A - Chip size package improved solder joining characteristics and the manufacturing method thereof - Google Patents

Chip size package improved solder joining characteristics and the manufacturing method thereof Download PDF

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Publication number
KR20030037693A
KR20030037693A KR1020010068529A KR20010068529A KR20030037693A KR 20030037693 A KR20030037693 A KR 20030037693A KR 1020010068529 A KR1020010068529 A KR 1020010068529A KR 20010068529 A KR20010068529 A KR 20010068529A KR 20030037693 A KR20030037693 A KR 20030037693A
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South Korea
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bonding
insulating layer
solder ball
bonding pads
wire
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KR1020010068529A
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Korean (ko)
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권용환
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삼성전자주식회사
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Publication of KR20030037693A publication Critical patent/KR20030037693A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Abstract

PURPOSE: A chip size package for improving solder bonding characteristic and a manufacturing method thereof are provided to be capable of restraining the generation of crack at the solder bonding portion by electrically connecting a bonding pad with a solder ball using a bonding wire. CONSTITUTION: A plurality of bonding pads(4), a passivation layer(6), and an insulation layer(10) are formed on a semiconductor chip(2). A circuit pattern(14) is formed on the insulation layer(10) for contacting bonding pads(4). The second bonding pads(5) are formed on the insulation layer(10) for contacting the circuit pattern(14). The second insulation layer(12) is formed on the resultant structure for exposing the second bonding pads(5). A bonding wire(18) is then formed on the resultant structure. At this time, one end of the bonding wire(18) is attached on the second bonding pad and the other end of the bonding wire(18) is curved upward on the second insulation layer(12). A solder ball(16) is attached on the second insulation layer(12) by using an adhesive part(22), and electrically connected with the second bonding pad through the bonding wire(18).

Description

솔더 접합 특성을 향상시킨 칩 사이즈 패키지 및 그 제조 방법{Chip size package improved solder joining characteristics and the manufacturing method thereof}Chip size package improved solder joining characteristics and the manufacturing method

본 발명은 CSP에 관한 것으로서, 더욱 상게하게는 반도체 칩에의 솔더볼 부착 구조를 변경함으로써, 솔더 접합 특성을 향상시킨 CSP와 그 제조 방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CSP, and more particularly, to a CSP and a method of manufacturing the same, in which solder bonding properties are improved by changing a solder ball attachment structure to a semiconductor chip.

최근 전자기기 등이 소형 경량화 되어감에 따라 그에 사용되는 반도체 칩 패키지도 경박 단소화 되어가는 추세를 보이고 있다. CSP는 그러한 추세에 부합하는 반도체 칩 패키지 중 하나로써, 종래처럼 리드 프레임(lead frame) 등을 이용한 구조 대신에 솔더볼을 이용하여 반도체 칩을 회로 기판에 직접 부착시키는 구조를 가지고 있다.Recently, as electronic devices and the like become smaller and lighter, semiconductor chip packages used therein also tend to be light and small. CSP is one of the semiconductor chip packages meeting the trend, and has a structure in which a semiconductor chip is directly attached to a circuit board by using solder balls instead of a structure using a lead frame.

이하 도면을 참조하여 종래 기술에 따른 CSP를 계속 설명한다.Hereinafter, a CSP according to the related art will be described with reference to the accompanying drawings.

도 1a는 종래 기술에 따른 CSP의 일반적 구조를 보여주는 도이고, 도 1b는 종래 기술에 따른 CSP의 다른 구조를 보여주는 도이며, 도 1c는 종래 기술에 따른 CSP에서 솔더 접합 시의 문제점을 보여주는 도이다.Figure 1a is a view showing a general structure of a CSP according to the prior art, Figure 1b is a view showing another structure of the CSP according to the prior art, Figure 1c is a diagram showing a problem in solder bonding in the CSP according to the prior art. .

도 1a에 나타낸 것처럼, 종래의 CSP에서는 솔더볼(16)이 솔더볼 패드(34)에 직접 부착되었는데, 이 경우 솔더볼(16)과 솔더볼 패드(34), 도금층(8), 회로 패턴 (14), 절연층(10) 등과 같은 CSP를 구성하는 각 부분들 사이에 열팽창 특성의 차이가 존재함으로 인해 솔더볼(16) 부착 시, 도 1c에서 나타낸 것과 같은 크랙 (30)이 발생할 수 있었다. 도 1b에 나타낸 구조를 갖는 종래의 CSP는 솔더볼 패드(34)와 반도체 칩(2) 사이에 탄성중합체(32)를 형성하여 앞서 언급한 크랙(30)의 발생을 방지하고자 했는데, 이 경우에도 크랙(30) 발생의 억제에는 한계가 있었으며, 또한 탄성중합체(32) 형성으로 인한 공정 추가와 제조 비용의 상승 문제가 존재하였다.As shown in FIG. 1A, in the conventional CSP, the solder balls 16 are directly attached to the solder ball pads 34. In this case, the solder balls 16 and the solder ball pads 34, the plating layer 8, the circuit pattern 14, and the insulation are provided. Due to the difference in thermal expansion characteristics between the respective parts constituting the CSP such as the layer 10, a crack 30 as shown in FIG. 1C may occur when the solder ball 16 is attached. In the conventional CSP having the structure shown in FIG. 1B, an elastomer 32 is formed between the solder ball pad 34 and the semiconductor chip 2 to prevent the aforementioned crack 30 from occurring. (30) There was a limit to suppression of occurrence, and there was also a problem of an increase in manufacturing cost and process addition due to the formation of the elastomer 32.

따라서 본 발명은, CSP를 제조함에 있어서 각 구성 요소 간 솔더 접합 부위의 열팽창 특성 차이로 인한 크랙 발생을 억제하여 솔더 접합 특성을 향상시킬 수 있는 CSP와 그 제조 방법의 제공을 목적으로 한다.Accordingly, an object of the present invention is to provide a CSP and a method of manufacturing the same, which can improve solder joint characteristics by suppressing cracking caused by differences in thermal expansion characteristics of solder joints between components in manufacturing CSPs.

도 1a는 종래 기술에 따른 칩 사이즈 패키지(chip size package;이하 CSP라고 한다)의 일반적 구조를 보여주는 도,1A illustrates a general structure of a chip size package (hereinafter referred to as a CSP) according to the prior art;

도 1b는 종래 기술에 따른 CSP구조의 제 2 예를 보여주는 도,1B is a view showing a second example of a CSP structure according to the prior art;

도 1c는 종래 기술에 따른 CSP에서의 문제점을 보여주는 도,1c illustrates a problem in a CSP according to the prior art;

도 2a는 반도체 칩(semiconductor chip)의 활성면에 패시베이션층(passiva-tion layer)이 형성된 모습을 보여주는 도,FIG. 2A illustrates a passivation layer formed on an active surface of a semiconductor chip; FIG.

도 2b는 패시베이션층의 상부에 절연층이 형성된 모습을 보여주는 도,Figure 2b is a view showing an insulating layer formed on top of the passivation layer,

도 2c는 절연층의 상부에 회로 패턴(circuit pattern)이 형성된 모습을 보여주는 도,Figure 2c is a view showing a circuit pattern (circuit pattern) formed on top of the insulating layer,

도 2d는 회로 패턴의 상부와 절연층의 상부에 걸쳐 제 2 절연층이 형성된 모습을 보여주는 도,2D is a view showing a state in which a second insulating layer is formed over an upper portion of a circuit pattern and an insulating layer;

도 2e는 제 2 본딩 패드(the second bonding pad)에 본딩 와이어(bonding wire)의 일단이 부착된 모습을 보여주는 도,FIG. 2E is a view illustrating one end of a bonding wire attached to a second bonding pad; FIG.

도 2f는 본딩 와이어의 타단이 측방향을 향하도록 구부러짐과 더불어 그 타단이 제 2 절연층으로부터 그 상부 방향을 향하도록 형성된 모습을 보여주는 도,FIG. 2F is a view showing a state in which the other end of the bonding wire is bent in a lateral direction and the other end thereof is formed to face upward from the second insulating layer;

도 2g는 완성된 CSP의 구조를 보여주는 도,Figure 2g shows the structure of the completed CSP,

도 3은 본 발명에 따른 CSP구조의 제 2 예를 보여주는 도,3 is a view showing a second example of a CSP structure according to the present invention;

도 4는 본 발명에 따른 CSP구조의 제 3 예를 보여주는 도 및4 shows a third example of a CSP structure according to the invention;

도 5는 본 발명에 따른 CSP구조의 제 4 예를 보여주는 도이다.5 is a view showing a fourth example of the CSP structure according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

2 : 반도체 칩 4 : 본딩 패드2: semiconductor chip 4: bonding pad

5 : 제 2 본딩 패드 6 : 패시베이션층5: second bonding pad 6: passivation layer

8 : 도금층 10 : 절연층8 plating layer 10 insulating layer

12 : 제 2 절연층 14 : 회로 패턴12 second insulating layer 14 circuit pattern

16 : 솔더볼(solder ball) 18 : 본딩 와이어16 solder ball 18 bonding wire

20 : 와이어 핀(wire pin) 22 : 접착 수단20 wire pin 22 bonding means

24 : 도전성 접착 수단 26 : 회로 기판24 conductive bonding means 26 circuit board

28 : 패드(pad) 30 : 크랙(crack)28: pad 30: crack

32 : 탄성 중합체(elastomer) 34 : 솔더볼 패드(solder ball pad)32: elastomer 34: solder ball pad

이와 같은 목적을 이루기 위해, 본 발명은 활성면에 다수의 본딩 패드(4)들이 형성된 반도체 칩(2), 본딩 패드(4)들은 노출시키면서 반도체 칩(2)의 활성면 상부에 형성된 패시베이션층(6), 본딩 패드(4)들은 그대로 노출시키면서 패시베이션층(6)의 상부에 형성된 절연층(10), 절연층(10)의 상부에 형성되며 패시베이션층 (6)과 절연층(10)의 본딩 패드(4) 노출 부분들을 통하여 본딩 패드(4)들에 접속되도록 형성된 회로 패턴(14), 회로 패턴(14)에 연결되며 절연층(10)의 상부에 형성된 제 2 본딩 패드(5)들, 회로 패턴(14)의 상부와 절연층(10)의 상부에 걸쳐 형성되며 제 2 본딩 패드(5)들은 노출되도록 형성된 제 2 절연층(12), 제 2 본딩 패드(5)에 일단이 부착되며 타단은 측방향을 향하도록 구부러짐과 더불어 그 타단이 제 2 절연층(12)으로부터 그 상부 방향을 향하도록 형성된 본딩 와이어(18), 및 제 2 절연층(12)의 상부에 접착 수단(22)을 통하여 부착되며 본딩 와이어(18)의 타단이 내부로 삽입되어 제 2 본딩 패드(5)와 전기적으로 접속되는 솔더볼(16)을 포함하는 것을 특징으로 하는 CSP를 제공한다. 그리고, 활성면에 다수의 본딩 패드 (4)들이 형성된 반도체 칩(2), 본딩 패드(4)들은 노출시키면서 반도체 칩(2)의 활성면 상부에 형성된 패시베이션층(6), 본딩 패드(4)들은 그대로 노출시키면서 패시베이션층(6)의 상부에 형성된 절연층(10), 본딩 패드(4)에 일단이 부착되며 타단은 측방향을 향하도록 구부러짐과 더불어 그 타단이 절연층(10)으로부터 그 상부 방향을 향하도록 형성된 본딩 와이어(18), 및 절연층 (10)의 상부에 접착 수단(22)을 통하여 부착되며 본딩 와이어(18)의 타단이 내부로 삽입되어 본딩 패드(4)와 전기적으로 접속되는 솔더볼(16)을 포함하는 것을 특징으로 하는 CSP를 제공한다. 또한, 다수의 본딩 패드(4)들이 형성된 반도체 칩(2)의 활성면에 본딩 패드(4)들은 노출될 수 있도록 하여 패시베이션층(6)을 형성하는 단계(a), 본딩 패드(4)들은 그대로 노출될 수 있도록 하여 패시베이션층(6)의 상부에 절연층(10)을 형성하는 단계(b), 패시베이션층(6)과 절연층(10)의 본딩 패드(4) 노출 부분들을 통하여 본딩 패드(4)들에 접속되며 제 2 본딩 패드(5)들이 연결되는 회로 패턴(14)을 절연층 (10)의 상부에 형성하는 단계(c), 제 2 본딩 패드(5)들은 노출시키면서 회로 패턴(14)의 상부와 절연층(10)의 상부에 걸쳐 제 2 절연층(12)을 형성하는 단계(d), 제 2 본딩 패드(5)에 본딩 와이어(18)의 일단을 부착시키는 단계(e), 본딩 와이어(18)의 타단을 측방향을 향하도록 구부림과 더불어 그 타단이 제 2 절연층(12)으로부터 그 상부 방향을 향하도록 형성하는 단계(f), 및 솔더볼(16)을 제 2 절연층(12)의 상부에 접착 수단(22)을 통하여 부착하고 본딩 와이어(18)의 타단을 솔더볼(16)의 내부로 삽입시켜 제 2 본딩 패드(5)와 전기적으로 접속시키는 단계(g)를 포함하는 CSP 제조 방법을 제공한다. 더불어, 다수의 본딩 패드(4)들이 형성된 반도체 칩(2)의 활성면에 본딩 패드(4)들은 노출될 수 있도록 하여 패시베이션층(6)을 형성하는 단계(A), 본딩 패드(4)들은 그대로 노출될 수 있도록 하여 패시베이션층(6)의 상부에 절연층(10)을 형성하는 단계(B), 본딩 패드(4)에 본딩 와이어(18)의 일단을 부착시키는 단계(C), 본딩 와이어(18)의 타단을 측방향을 향하도록 구부림과 더불어 그 타단이 절연층(10)으로부터 그 상부 방향을 향하도록 형성하는 단계(D), 및 솔더볼(16)을 절연층(10)의 상부에 접착 수단(10)을 통하여 부착하고 본딩 와이어(18)의 타단을 솔더볼(16)의 내부로 삽입시켜 본딩 패드(4)와 전기적으로 접속시키는 단계(E)를 포함하는 CSP 제조 방법을 제공한다.In order to achieve the above object, the present invention provides a semiconductor chip 2 having a plurality of bonding pads 4 formed on the active surface, and a passivation layer formed on the active surface of the semiconductor chip 2 while exposing the bonding pads 4. 6) The bonding pads 4 are formed on the insulating layer 10 and the insulating layer 10 formed on the passivation layer 6 while being exposed, and the bonding of the passivation layer 6 and the insulating layer 10. A circuit pattern 14 formed to be connected to the bonding pads 4 through exposed portions of the pad 4, second bonding pads 5 connected to the circuit pattern 14 and formed on the insulating layer 10, One end is attached to the second insulating layer 12 and the second bonding pad 5, which are formed over the circuit pattern 14 and the upper portion of the insulating layer 10, and the second bonding pads 5 are exposed. The other end is bent to face side and the other end is directed upward from the second insulating layer 12. The formed bonding wire 18 and the upper portion of the second insulating layer 12 are attached through the adhesive means 22, and the other end of the bonding wire 18 is inserted therein to be electrically connected to the second bonding pad 5. It provides a CSP, characterized in that it comprises a solder ball (16). The semiconductor chip 2 having the plurality of bonding pads 4 formed on the active surface and the passivation layer 6 and the bonding pad 4 formed on the active surface of the semiconductor chip 2 while exposing the bonding pads 4 are exposed. One end is attached to the insulating layer 10 formed on the top of the passivation layer 6 and the bonding pad 4 while being exposed as it is, and the other end is bent to face in the lateral direction, and the other end thereof is upper side from the insulating layer 10. The bonding wire 18 formed to face in the direction, and attached to the upper portion of the insulating layer 10 through the adhesive means 22, the other end of the bonding wire 18 is inserted into the interior and electrically connected to the bonding pad 4 It provides a CSP, characterized in that it comprises a solder ball (16). In addition, forming the passivation layer 6 by exposing the bonding pads 4 to the active surface of the semiconductor chip 2 on which the plurality of bonding pads 4 are formed (a), and the bonding pads 4 Forming an insulating layer 10 on top of the passivation layer 6 so as to be exposed as it is, bonding pads through the passivation layer 6 and the bonding pads 4 exposed portions of the insulating layer 10. (C) forming a circuit pattern 14 connected to the (4) and connecting the second bonding pads 5 to the upper portion of the insulating layer 10, and exposing the second bonding pads 5 while the circuit pattern is exposed. (D) forming a second insulating layer 12 over the top of the insulating layer 10 and the top of the insulating layer 10, and attaching one end of the bonding wire 18 to the second bonding pad 5 ( e) bending the other end of the bonding wire 18 to face in the lateral direction and forming the other end from the second insulating layer 12 to face upwards, And attaching the solder ball 16 to the upper portion of the second insulating layer 12 through the adhesive means 22 and inserting the other end of the bonding wire 18 into the solder ball 16 so as to form the second bonding pad 5. It provides a method for producing a CSP comprising the step (g) of electrically connecting. In addition, the bonding pads 4 may be exposed on the active surface of the semiconductor chip 2 on which the plurality of bonding pads 4 are formed to form the passivation layer 6 (A), and the bonding pads 4 may be Forming an insulating layer 10 on the passivation layer 6 so as to be exposed as it is (B), attaching one end of the bonding wire 18 to the bonding pad 4 (C), bonding wire Bending the other end of the 18 to the lateral direction and forming the other end from the insulating layer 10 to the upper direction thereof, and forming a solder ball 16 on the upper part of the insulating layer 10. A method of manufacturing a CSP is provided, which comprises attaching through the adhesive means (10) and inserting the other end of the bonding wire (18) into the solder ball (16) to electrically connect with the bonding pad (4).

이하 도면을 참조하여 본 발명에 따른 CSP와 그 제조 방법에 대해 상세히 설명한다.Hereinafter, a CSP and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g에서는 본 발명에 따른 CSP의 제조 방법의 각 단계에 따른 모습을 나타내고 있는데, 도 2a에서는 다수의 본딩 패드(4)들이 형성된 반도체 칩(2)의 활성면에 본딩 패드(4)들은 노출될 수 있도록 하여 패시베이션층(6)을 형성한 모습을 나타내고 있고, 도 2b에서는 그렇게 형성된 패시베이션층(6)의 상부에 역시 본딩 패드(4)들은 노출될 수 있도록 하여 절연층(10)을 형성한 모습을 나타내고 있다. 도 2c에서는 절연층(10)의 상부에 제 2 본딩 패드(5)들이 연결되는 회로 패턴(14)을 형성한 모습을 나타내고 있는데, 앞서 형성된 패시베이션층(6)과 절연층(10)에서의 본딩 패드(4) 노출 부분들에도 회로 패턴이 형성되어 본딩 패드(4)와 전기적으로 접속된 모습을 나타내고 있다. 도 2d에서는 회로 패턴(14)의 상부와 절연층(10)의 상부에 걸쳐 형성하되 제 2 본딩 패드(5)들은 노출되도록 제 2 절연층(12)을 형성한 모습을 나타내고 있고, 도 2e에서는 노출된 제 2 본딩 패드(5)에 본딩 와이어(18)의 일단이 부착된 모습을 나타내고 있으며, 도 2f에서는 본딩 와이어(18)의 타단이 측방향을 향하도록 구부러짐과 더불어 그 타단이 제 2 절연층(12)으로부터 그 상부 방향을 향하도록 형성된 모습을 나타내고 있다. 도 2g에서는 솔더볼(16)을 접착 수단(22)을 이용하여 제 2 절연층(12)의 상부에 부착시키되 본딩 와이어(18)의 타단을 솔더볼(16)의 내부에 삽입시켜 제 2 본딩 패드(5)와 솔더볼 (16)을 전기적으로 접속시킴으로써 완성된 본 발명에 따른 CSP의 구조를 나타내고 있다.2A to 2G show the appearance of each step of the manufacturing method of the CSP according to the present invention. In FIG. 2A, the bonding pad 4 is formed on the active surface of the semiconductor chip 2 on which the plurality of bonding pads 4 are formed. 2 shows that the passivation layer 6 is formed so as to be exposed, and in FIG. 2B, the bonding pads 4 are also exposed on the upper portion of the passivation layer 6 so formed so that the insulating layer 10 is exposed. It shows how it was formed. In FIG. 2C, the circuit pattern 14 to which the second bonding pads 5 are connected is formed on the insulating layer 10. The passivation layer 6 and the bonding layer 10 are formed. A circuit pattern is also formed on the exposed portions of the pad 4 to show the state of being electrically connected to the bonding pad 4. In FIG. 2D, the second insulating layer 12 is formed to be formed over the upper portion of the circuit pattern 14 and the upper portion of the insulating layer 10, but the second bonding pads 5 are exposed. One end of the bonding wire 18 is attached to the exposed second bonding pad 5. In FIG. 2F, the other end of the bonding wire 18 is bent in a lateral direction, and the other end thereof is second insulated. It is shown that the layer 12 is formed to face upward. In FIG. 2G, the solder ball 16 is attached to the upper portion of the second insulating layer 12 by using the adhesive means 22, but the other end of the bonding wire 18 is inserted into the solder ball 16 to form a second bonding pad ( The structure of the CSP which concerns on this invention completed by electrically connecting 5) and the solder ball 16 is shown.

도 3 내지 도 5는 본 발명에 따른 각각 다른 구성예를 보여주는 도인데, 도 3에서는 앞서 제시한 구성에 있어서, 제 2 절연층(12)에서 노출된 제 2 본딩 패드(5)에 본딩 와이어(18)를 부착하는 대신 와이어 핀(wire pin, 20)의 일단을 부착하고, 솔더볼(16)은 노출된 제 2 본딩 패드(5)의 상부에 접착 수단(22)을 통하여 부착되며 그 내부로 와이어 핀(20)의 타단이 삽입되어 제 2 본딩 패드(5)와 전기적으로 접속되는 것을 특징으로 하는 CSP의 구조를 나타내고 있고, 도 4에서는 패시베이션층(6)의 상부에 절연층(10)을 형성하고, 회로 패턴(14)을 형성하는 대신 본딩 와이어(18)의 일단을 본딩 패드(4)에 직접 부착시키며, 타단을 측방향을 향하도록 구부림과 더불어 그 타단이 절연층(10)으로부터 그 상부 방향을 향하도록 형성한 후, 솔더볼(16)을 절연층(10)의 상부에 접착 수단(22)을 통하여 부착하되 본딩 와이어(18)의 타단을 솔더볼(16) 내부로 삽입시켜 본딩 패드(4)와 솔더볼(16)이 전기적으로 접속되는 것을 특징으로 하는 CSP의 구조를 나타내고 있으며, 도 5에서는 도 4에서 나타낸 구성에 있어서, 솔더볼(16)은 절연층(10)에 도전성 접착 수단(24)을 통하여 부착되고, 본딩 와이어(18)의 타단은 도전성 접착 수단(24)에 삽입되어 솔더볼(16)과 본딩 패드(4)가 전기적으로 접속되는 것을 특징으로 하는 CSP의 구조를 나타낸다.3 to 5 are views showing different configurations according to the present invention. In FIG. 3, the bonding wires are formed on the second bonding pads 5 exposed by the second insulating layer 12. Instead of attaching 18, one end of a wire pin 20 is attached, and the solder ball 16 is attached to the upper portion of the exposed second bonding pad 5 through an adhesive means 22 and wires therein. The other end of the pin 20 is inserted and electrically connected to the second bonding pad 5. The structure of the CSP is shown. In FIG. 4, the insulating layer 10 is formed on the passivation layer 6. Instead of forming the circuit pattern 14, one end of the bonding wire 18 is directly attached to the bonding pad 4, and the other end is bent in the lateral direction, and the other end thereof is upper side from the insulating layer 10. After forming to face the direction, the solder ball 16 is attached to the upper portion of the insulating layer (10) 2) shows the structure of the CSP characterized in that the bonding pad 4 and the solder ball 16 are electrically connected by inserting the other end of the bonding wire 18 into the solder ball 16. In the configuration shown in Figure 4, the solder ball 16 is attached to the insulating layer 10 through the conductive bonding means 24, the other end of the bonding wire 18 is inserted into the conductive bonding means 24 to the solder ball ( 16) shows a structure of a CSP characterized in that the bonding pads 4 are electrically connected.

이와 같이, 본 발명에 따른 CSP의 구조와 그 제조 방법에 따르면, 솔더볼이 반도체 칩 상의 패드에 직접 부착되는 대신 접착 수단을 통하여 절연층에 부착되고 본딩 와이어 또는 와이어 핀 등에 의해 전기적으로 접속되기 때문에 유동 특성을 지니게 되고 또한 솔더볼이 패키지 상에 가열을 통하여 부착되지 않기 때문에 솔더볼 부착시 각 구성 요소의 열팽창 계수 불일치로 인한 크랙 등의 불량 발생 억제를 기대할 수 있으며, 그로 인한 생산성 향상도 기대할 수 있다.As such, according to the structure of the CSP and the manufacturing method thereof according to the present invention, instead of directly attaching the solder balls to the pads on the semiconductor chip, the solder balls are attached to the insulating layer through adhesive means and electrically connected by bonding wires or wire pins or the like. Since the solder ball is not attached to the package through heating, it is possible to suppress defects such as cracks caused by mismatch of thermal expansion coefficient of each component when solder ball is attached, and thus productivity improvement can be expected.

Claims (8)

활성면에 다수의 본딩 패드(bonding pad)들이 형성된 반도체 칩 (semiconductor chip);A semiconductor chip having a plurality of bonding pads formed on an active surface thereof; 상기 본딩 패드들은 노출시키면서 상기 반도체 칩의 활성면 상부에 형성된 패시베이션층(passivation layer);A passivation layer formed on the active surface of the semiconductor chip while exposing the bonding pads; 상기 본딩 패드들은 그대로 노출시키면서 상기 패시베이션층의 상부에 형성된 절연층;An insulating layer formed on the passivation layer while exposing the bonding pads; 상기 절연층의 상부에 형성되며, 상기 패시베이션층과 상기 절연층의 본딩 패드 노출 부분들을 통하여 상기 본딩 패드들에 접속되도록 형성된 회로 패턴 (circuit pattern);A circuit pattern formed on the insulating layer and connected to the bonding pads through the passivation layer and the bonding pad exposed portions of the insulating layer; 상기 회로 패턴에 연결되며, 상기 절연층의 상부에 형성된 제 2 본딩 패드들;Second bonding pads connected to the circuit pattern and formed on the insulating layer; 상기 회로 패턴의 상부와 상기 절연층의 상부에 걸쳐 형성되며, 상기 제 2 본딩 패드들은 노출되도록 형성된 제 2 절연층;A second insulating layer formed over the circuit pattern and over the insulating layer, wherein the second bonding pads are exposed; 상기 제 2 본딩 패드에 일단이 부착되며, 타단은 측방향을 향하도록 구부러짐과 더불어 그 타단이 상기 제 2 절연층으로부터 그 상부 방향을 향하도록 형성된 본딩 와이어(bonding wire); 및A bonding wire having one end attached to the second bonding pad, the other end of which is bent to face in a lateral direction, and the other end of which is directed from the second insulating layer to an upper direction thereof; And 상기 제 2 절연층의 상부에 접착 수단을 통하여 부착되며, 상기 본딩 와이어의 타단이 내부로 삽입되어 상기 제 2 본딩 패드와 전기적으로 접속되는 솔더볼(solder ball);을 포함하는 것을 특징으로 하는 칩 사이즈 패키지(chip size package).And a solder ball attached to an upper portion of the second insulating layer through an adhesive means and having a second end of the bonding wire inserted therein and electrically connected to the second bonding pad. Package (chip size package). 제 1항에 있어서, 상기 제 2 절연층에서 노출된 상기 제 2 본딩 패드에 와이어 핀(wire pin)의 일단을 부착하고, 솔더볼은 노출된 상기 제 2 본딩 패드의 상부에 접착 수단을 통하여 부착되며, 그 내부로 상기 와이어 핀의 타단이 삽입되어 상기 제 2 본딩 패드와 전기적으로 접속되는 것을 특징으로 하는 칩 사이즈 패키지.The method of claim 1, wherein one end of a wire pin is attached to the second bonding pad exposed from the second insulating layer, and solder balls are attached to the upper portion of the exposed second bonding pad through adhesive means. And the other end of the wire pin is inserted therein and electrically connected to the second bonding pad. 활성면에 다수의 본딩 패드들이 형성된 반도체 칩;A semiconductor chip having a plurality of bonding pads formed on an active surface thereof; 상기 본딩 패드들은 노출시키면서 상기 반도체 칩의 활성면 상부에 형성된 패시베이션층;A passivation layer formed on the active surface of the semiconductor chip while exposing the bonding pads; 상기 본딩 패드들은 그대로 노출시키면서 상기 패시베이션층의 상부에 형성된 절연층;An insulating layer formed on the passivation layer while exposing the bonding pads; 상기 본딩 패드에 일단이 부착되며, 타단은 측방향을 향하도록 구부러짐과 더불어 그 타단이 상기 절연층으로부터 그 상부 방향을 향하도록 형성된 본딩 와이어; 및A bonding wire having one end attached to the bonding pad, the other end of which is bent to face in the lateral direction, and the other end of which is directed toward the upper direction from the insulating layer; And 상기 절연층의 상부에 접착 수단을 통하여 부착되며, 상기 본딩 와이어의 타단이 내부로 삽입되어 상기 본딩 패드와 전기적으로 접속되는 솔더볼;을 포함하는 것을 특징으로 하는 칩 사이즈 패키지.And a solder ball attached to an upper portion of the insulating layer through an adhesive means, and the other end of the bonding wire is inserted therein and electrically connected to the bonding pads. 제 3항에 있어서, 상기 솔더볼은 상기 절연층에 도전성 접착 수단을 통하여 부착되고, 상기 본딩 와이어의 타단이 상기 도전성 접착 수단에 삽입되어 상기 솔더볼과 상기 본딩 패드가 전기적으로 접속되는 것을 특징으로 하는 칩 사이즈 패키지.The chip of claim 3, wherein the solder ball is attached to the insulating layer through conductive bonding means, and the other end of the bonding wire is inserted into the conductive bonding means to electrically connect the solder ball and the bonding pad. Size package. 다수의 본딩 패드들이 형성된 반도체 칩의 활성면에 상기 본딩 패드들은 노출될 수 있도록 하여 패시베이션층을 형성하는 단계(a);(A) forming a passivation layer by exposing the bonding pads to an active surface of a semiconductor chip on which a plurality of bonding pads are formed; 상기 본딩 패드들은 그대로 노출될 수 있도록 하여 상기 패시베이션층의 상부에 절연층을 형성하는 단계(b);(B) forming an insulating layer on the passivation layer by allowing the bonding pads to be exposed as it is; 상기 패시베이션층과 상기 절연층의 본딩 패드 노출 부분들을 통하여 상기 본딩 패드들에 접속되며 제 2 본딩 패드들이 연결되는 회로 패턴을 상기 절연층의 상부에 형성하는 단계(c);(C) forming a circuit pattern connected to the bonding pads through the bonding pad exposed portions of the passivation layer and the insulating layer and to which second bonding pads are connected, on the insulating layer; 상기 제 2 본딩 패드들은 노출시키면서 상기 회로 패턴의 상부와 상기 절연층의 상부에 걸쳐 제 2 절연층을 형성하는 단계(d);(D) forming a second insulating layer over the circuit pattern and over the insulating layer while exposing the second bonding pads; 상기 제 2 본딩 패드에 본딩 와이어의 일단을 부착시키는 단계(e);Attaching one end of a bonding wire to the second bonding pad (e); 상기 본딩 와이어의 타단이 측방향을 향하도록 구부림과 더불어 그 타단이 상기 제 2 절연층으로부터 그 상부 방향을 향하도록 형성하는 단계(f); 및(F) bending the other end of the bonding wire toward the lateral direction and forming the other end toward the upper direction from the second insulating layer; And 솔더볼을 상기 제 2 절연층의 상부에 접착 수단을 통하여 부착하고, 상기 본딩 와이어의 타단을 솔더볼의 내부로 삽입시켜 상기 제 2 본딩 패드와 전기적으로 접속시키는 단계(g);를 포함하는 칩 사이즈 패키지 제조 방법.Attaching a solder ball to the upper portion of the second insulating layer through an adhesive means, and inserting the other end of the bonding wire into the solder ball to electrically connect the second bonding pad to the second bonding pad (g); Manufacturing method. 제 5항에 있어서, 상기 단계(e)는 상기 제 2 본딩 패드에 와이어 핀의 일단을 부착시키는 단계;이고, 상기 단계(f)는 상기 솔더볼을 상기 접착 수단을 이용하여 상기 회로 패턴에 부착시키는 단계;이며, 상기 단계(g)는 상기 와이어 핀의 타단을 상기 솔더볼의 내부로 삽입시켜 상기 제 2 본딩 패드와 솔더볼을 전기적으로 접속시키는 단계;인 것을 특징으로 하는 칩 사이즈 패키지 제조 방법.6. The method of claim 5, wherein step (e) comprises attaching one end of a wire pin to the second bonding pad, wherein step (f) attaches the solder ball to the circuit pattern using the bonding means. And (g) inserting the other end of the wire pin into the solder ball to electrically connect the second bonding pad and the solder ball. 다수의 본딩 패드들이 형성된 반도체 칩의 활성면에 상기 본딩 패드들은 노출될 수 있도록 하여 패시베이션층을 형성하는 단계(A);Forming a passivation layer by exposing the bonding pads to an active surface of a semiconductor chip on which a plurality of bonding pads are formed; 상기 본딩 패드들은 그대로 노출될 수 있도록 하여 상기 패시베이션층의 상부에 절연층을 형성하는 단계(B);(B) forming an insulating layer on the passivation layer by allowing the bonding pads to be exposed as it is; 상기 본딩 패드에 본딩 와이어의 일단을 부착시키는 단계(C);Attaching one end of a bonding wire to the bonding pad (C); 상기 본딩 와이어의 타단이 측방향을 향하도록 구부림과 더불어 그 타단이 상기 절연층으로부터 그 상부 방향을 향하도록 형성하는 단계(D); 및(D) bending the other end of the bonding wire toward the lateral direction and forming the other end toward the upper direction from the insulating layer; And 솔더볼을 상기 절연층의 상부에 접착 수단을 통하여 부착하고, 상기 본딩 와이어의 타단을 솔더볼의 내부로 삽입시켜 상기 본딩 패드와 전기적으로 접속시키는 단계(E);를 포함하는 칩 사이즈 패키지 제조 방법.Attaching a solder ball to the upper portion of the insulating layer through an adhesive means, and inserting the other end of the bonding wire into the solder ball to electrically connect the solder pad to the bonding pad (E). 제 7항에 있어서, 상기 단계(D)는 상기 본딩 와이어의 타단을 측방향을 향하도록 구부리는 단계;이고, 상기 단계(E)는 솔더볼을 상기 절연층의 상부에 도전성접착 수단을 통하여 부착시키면서, 상기 본딩 와이어의 타단을 상기 도전성 접착 수단의 내부에 삽입하여 상기 본딩 패드와 상기 솔더볼을 전기적으로 접속시키는 단계;인 것을 특징으로 하는 칩 사이즈 패키지 제조 방법.8. The method of claim 7, wherein the step (D) is a step of bending the other end of the bonding wire to the lateral direction; and the step (E) while attaching the solder ball to the upper portion of the insulating layer through the conductive adhesive means And inserting the other end of the bonding wire into the conductive adhesive means to electrically connect the bonding pad and the solder ball.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100596766B1 (en) * 1999-06-28 2006-07-04 주식회사 하이닉스반도체 Outside terminal structure of semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100596766B1 (en) * 1999-06-28 2006-07-04 주식회사 하이닉스반도체 Outside terminal structure of semiconductor package

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