KR20030033893A - Method for reading data storded in a semiconductor memory device - Google Patents

Abstract

PURPOSE: A method for reading data of a semiconductor memory device is provided to improve a refresh characteristic of a DRAM by generating the electric potential difference between a bit line and a bit line bar. CONSTITUTION: A memory cell array having plural memory cells is connected between plural word lines and plural bit lines. A sense amplifier is used for comparing input signals of the first and the second input terminals. The first transistor is connected between the bit line and the first input terminal of the sense amplifier. The second transistor is connected between a bit line bar and the second input terminal of the sense amplifier. The second bias voltage is applied to the first transistor when the first bias voltage is applied to the first and the second transistors. The first transistor is operated by the second bias voltage and the electric potential of a bit line connected with a selected memory cell is boosted to a predetermined level. A supply voltage is applied to a sense amplifier and the second bias voltage is applied to the second transistor. The data of the memory cell are read by operating the sense amplifier.

Description

Method for reading data storded in a semiconductor memory device

The present invention relates to a data reading method of a semiconductor memory device, and more particularly, to a data reading method of a semiconductor memory device that can improve read operations and refreshes.

In general, a DRAM (Dynamic Random Access Memory (DRAM)) is a cell array block, which is a collection of cells that store data, and a peripheral circuit for transferring data of cells quickly and accurately to the outside. It consists of. The cell array block is composed of a plurality of cells including one path transistor and a capacitor connected to word lines and bit lines connected in a mesh shape.

The operation of the row decoder selecting one of the word lines of the cell array block selects a word line corresponding to a row address input from a plurality of word lines.

The general operation of the DRAM device described above will be briefly described as follows.

First, when the ras (/ RAS) signal, the main signal for operating the DRAM device, changes to the active state (LOW), the address signal input to the row address buffer is received, and the received row address signals are decoded to decode the word line of the cell array block. The row decoding operation of selecting one is performed. In this case, when data of cells connected to the selected word line is loaded on the bit lines BL and / BL, a signal (ie, a sense amplifier enable signal) indicating an operation timing of the bit line sense amplifier is enabled and loaded. The sense amplifier driving circuit of the cell array block selected by the address is driven. The sense amplifier enable signal by the sense amplifier driving circuit is shifted to the power supply potential Vcc and the ground potential Vss, respectively, to drive the sense amplifier.

When the sense amplifier starts to operate, the bit lines BL and / BL which have maintained a small potential difference show full potential difference and are full-swing, and then the column selected by the column address. The decoder transfers the data transferred to the bit lines BL and / BL to the data bus lines DB and / DB by turning on a column transfer transistor that transfers the data of the bit line to the data bus line. Will print.

The DRAM driven as described above must perform a refresh operation to maintain the original data due to a loss current in which data stored in the cell capacitor is lost through various paths even while the power is turned on. The refresh operation of the DRAM is performed by rewriting after detecting data of a cell. In the refresh operation, the time required for one cell to be refreshed and then again to perform the refresh operation on the cell is' It is called a refresh cycle, which is called 'data retention time' because it is the time for one cell to perform a refresh operation and to maintain data until the next refresh operation. do.

Therefore, for stable operation, the data holding time needs to be longer than the refresh period. When the data holding time of the DRAM element is sufficiently long compared to the refresh period, that is, the refresh operation is too much compared with the data holding time of the cell. In case of frequent use, excessive power consumption is required. Therefore, it is preferable to make the refresh period somewhat longer to improve the refresh characteristics. In order to increase the refresh period, the amount of leakage current in the memory cell may be reduced to reduce the decrease of the cell voltage or the bit line precharge voltage V _BLP will be described in detail in terms of the bit line sense amplifier.

FIG. 1 is a circuit diagram of a bit line sense amplifier that is generally used, and is activated by a bit line precharge control signal (BLP) when entering a standby mode. Derivation of the precharge unit 10 and the rasba (/ RAS) signal which precharges the bit line BL and the bit line bar (/ BL ') equally to the bit line precharge voltage V _BLP The data sensing unit 20 senses data by amplifying a potential difference between the bit line BL and the bit line bar / BL by the two control signals / S and RTO.

In addition, the bit line sense amplifier is configured on the upper and lower portions of the bit line BL and the bit line bar / BL, and includes a first bis_BL signal, a first bisva signal bisu_ / BL, Connected to a memory cell (not shown) depending on the states of the bit line isolation transistors N1 to N4 driven according to the second bis signal bisd_BL and the second bisva signal bisd_ / BL. Is blocked.

2A and 2B illustrate an operation timing diagram of the bit line sense amplifier illustrated in FIG. 1, FIG. 2A is an operation timing diagram during a high data read operation '1', and FIG. 2B illustrates a low data ('0 operation). ') Operation timing chart during read operation.

Referring to FIGS. 2A and 2B, the word line WL potential is maintained at the ground potential Vss during the period t ₀ to t ₁ , that is, in the standby mode, and the bit line equalization signals blequ and bleqd are applied to the power supply potential. Vcc), and the first and second biscues bisu_BL and bisd_BL and the first and second bisva signals bisu_ / BL and bisd_BL are maintained at the power supply potential Vcc. As a result, the fifth and sixth NMOS transistors N5 and N6 are turned on so that both bit lines BL and / BL are equalized to the same potential and the first to fourth NMOS transistors N1 to N4 are turned on. Turn-ON, the memory cell and the sense amplifier is electrically connected.

In this state, as the bit line precharge control signal BLP transitions to the power supply potential Vcc, the seventh and eighth NMOS transistors N7 and N8 are turned on so that the bit line BL and the bit line bar ( / BL) is precharged to the bit line precharge voltage V _BLP at the same potential level. At this time, the sensing control signals '/ S' and 'RTO' signals are all precharged with the bit line precharge voltage V _BLP .

During the period t ₁ to t ₂ , the bit line precharge control signal BLP and the bit line equalization signals blequ and bleqd transition to the ground potential Vss, and the first bis signal bisu_BL and the first bis The bar signal bisu_ / BL transitions to the high voltage Vpp, and the second bis signal bisd_BL and the second bisva signal bisd_ / BL transition to the ground voltage Vss. As a result, the seventh and eighth NMOS transistors N7 and N8 of the precharge unit 10 are turned off, so that the bit line BL and the bit line bar / BL are 'Vcc /'. It is maintained in a floating state disconnected from the outside while maintaining a potential of 2 '.

During the period t ₂ to t ₃ , the row decoder analyzes the row address input from the outside, selects one word line WL, and raises the potential to the potential of the high voltage Vpp. Accordingly, the charge of the memory cell connected to the selected word line WL is carried on the corresponding bit line, and the bit line BL voltage V _B is high when the data stored in the cell is high data '1'. As shown in FIG. 2A, when the data stored in the cell is row data ('0'), the data is lowered by the predetermined potential as shown in FIG. 2B. At this time, the potential of the bit line bar / BL maintains the precharged 'Vcc / 2' without changing the potential. In addition, the bit line BL voltage V _B is represented by Equation 1 below.

Here, V _{S is a} cell voltage, C _{B is a} bit line capacitance, and C _{S is a} cell capacitance.

Then, the potential of the sensing control signal / S is gradually lowered from 'Vcc / 2' to activate the data sensing unit 20 to amplify the potential difference between the bit line BL and the bit line bar / BL. do. In this case, the potential of the bit line BL is gradually lowered, but the potential difference ΔV between the bit line BL and the bit line bar / BL is fixed while the potential of the opposite bit line bar / BL remains unchanged. Will increase.

If the potential difference ΔV between the bit line BL and the bit line bar / BL increases to some extent during the period t ₃ to t ₄ , the two sensing control signals / S , RTO) is rapidly changed to ground potential (Vss) and power supply potential (Vcc), respectively, so that the potential of the bit line (BL) loaded with low data ('0') is discharged to the ground potential (Vss), and the opposite bit line bar The potential of / BL is charged to the power supply potential Vcc to complete the sensing operation. In the case of the high data ('1'), the two sensing control signals (/ S, RTO) are rapidly changed into the power supply potential (Vcc) and the ground potential (Vss), respectively, so that the bit line containing the high data ('1') The potential of BL is discharged to the power supply potential Vcc, and the potential of the opposite bit line bar / BL is charged to the ground potential Vss to complete the sensing operation. In this case, the potential difference ΔV between the bit line BL and the bit line bar / BL is expressed by Equation 2 below.

Of course, since the potential of the word line WL continues to maintain the high voltage Vpp during this time, the selected cell is continuously connected to the bit line BL and the bit line bar / BL so that the cell data voltage is automatically grounded. (Vss) or power potential (Vss), which is referred to as a 'rewrite (rewrite) operation, which corresponds to the DRAM refresh operation. Thereafter, the data sensed by the column operation is loaded on the data bus so as to be read out from the outside.

After completion of the read operation, the potential of the word line WL is lowered to store the data of the memory cell, and the bit line precharge control signal BLP is transitioned back to the power supply potential Vcc in preparation for the next pupil. By turning on the seventh and eighth NMOS transistors N7 and N8 in the precharge unit 10, the potentials of both the bit line BL and the bit line bar / BL are changed to the bit line precharge voltage V _BLP . The bit line BL and the bit line bar / BL are shorted with each other by the bit line equalization signals blequ and bleqd to equalize.

The bit line sense amplifier, which performs data sensing and amplification through the above process, is more easily amplified as the potential difference ΔV between the bit line BL and the bit line bar / BL is large.

However, the charge stored in the capacitor in the DRAM cell gradually decreases over time due to the leakage current, so that the cell voltage V _S is lowered. The lowered cell voltage V _S is a bit as shown in Equation 2 above. By reducing the potential difference [Delta] V between the line BL and the bit line bar / BL, it becomes difficult to sense and amplify the data of the bit line sense amplifier, thereby increasing the error occurrence during the read operation. Therefore, the refresh operation is performed periodically to compensate for the reduced charge in the cell capacitor, and the refresh cycle is also an important characteristic of the DRAM for this reason.

Typically, the refresh characteristics of the DRAM are more vulnerable at high data ('1') than at low data ('0') and at higher temperatures than low temperature, because the amount of leakage current in the cell increases as the temperature increases. As such, a long refresh period is desirable to improve the refresh characteristics. To this end, the cell leakage is reduced by reducing the leakage current in the cell, or the refresh period is extended by lowering the bit line precharge voltage (V _BLP ). .

However, when the bit line precharge voltage V _BLP is lowered and applied as described above, when the high data '1' is read, the potential difference ΔV between the bit line BL and the bit line bar / BL is applied. However, when the DRAM operates at a high speed, the operation of precharging the bit line BL and the bit line bar / BL to the bit line precharge voltage V _BLP level becomes frequent. As the precharge voltage V _BLP becomes a voltage close to 'Vpp / 2', as shown in Equation 2, the potential difference ΔV between the bit line BL and the bit line bar / BL becomes It becomes lower than when it is precharged by the bit line precharge voltage V _BLP .

Therefore, in the high speed operation, the effect of lowering the bit line precharge voltage V _BLP is lost, and there is a problem in that the refresh characteristic is not improved at all.

Accordingly, the present invention has been made to solve the above problem, and the gate signal of a pair of bit line isolation transistors which connect or disconnect between a memory cell and a bit line sense amplifier are different from each other. Refreshing characteristics of the DRAM by causing the potential difference between the bit line BL and the bit line bar (/ BL) by causing the voltage rising effect due to the gate capacitance to be different in the bit line BL and the bit line bar (/ BL) The aim is to improve this.

1 is a circuit diagram illustrating a general bit line sense amplifier.

2A and 2B are timing diagrams illustrating operation of the bit line sense amplifier illustrated in FIG. 1.

3A and 3B are timing diagrams illustrating an operation of the bit line sense amplifier shown in FIG. 1 according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: precharge unit 20: data sensing unit

The present invention provides a memory cell array in which a plurality of memory cells are connected between a plurality of word lines and bit lines, a sense amplifier for comparing signals input through first and second input terminals, the bit line and the sense amplifier. A semiconductor memory device comprising: a first transistor connected between a first input terminal of a second transistor; and a second transistor connected between a bit line bar and a second input terminal of the sense amplifier. A second bias voltage is applied to the first transistor while a first bias voltage is applied to operate the first transistor to increase a potential of a bit line connected to a selected memory cell by a predetermined level, and then supply a power supply voltage to the sense amplifier. The second bias voltage is supplied to the second transistor and the second transistor is operated by the operation of the sense amplifier. It is characterized in that the data stored in the memory cell is read.

The present invention also provides a memory cell array having a plurality of memory cells connected between a plurality of word lines and bit lines, a sense amplifier for comparing signals input through first and second input terminals, the bit lines and the 1. A semiconductor memory device comprising a first transistor connected between a first input terminal of a sense amplifier, and a second transistor connected between a bit line bar and a second input terminal of the sense amplifier. Applying a first bias voltage to a gate of the gate and applying a read bias voltage to a selected word line to cause the potential of the first input terminal to rise to a first level higher than the potential of the second input terminal; A second step of applying a second bias voltage to the gate of the first transistor to raise the potential of the first input terminal to a second level; And applying a power supply voltage to the sense amplifier and applying a second bias voltage to the gate of the second transistor so that data stored in the memory cell selected according to the potential difference between the first input terminal and the second input terminal is read. The third step is made.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3A and 3B illustrate an operation timing diagram of the bit line sense amplifier shown in FIG. 1 according to an embodiment of the present invention. FIG. 3A is an operation timing diagram when a high data ('1') read operation is performed. 3B is an operation timing diagram at the time of reading the low data ('0').

Referring to FIGS. 3A and 3B, the word line WL potential is maintained at the ground potential Vss during the period t ₀ to t ₁ , that is, in the standby mode, and the bit line equalization signals blequ and bleqd are applied to the power supply potential. Vcc), and the first bis_Bl and the first bisva signal bisu_ / BL, the second bisb signal bisd_BL and the second bisva signal bisd_ / BL are supplied to the power supply potential Vcc. maintain. As a result, the fifth and sixth NMOS transistors N5 and N6 are turned on so that the bit line BL and the bit line bar / BL are equalized to the same potential, and the first to fourth NMOS transistors N1 to N1. N4) is turned on so that the memory cell and the bit line sense amplifier are electrically connected.

In this state, as the bit line precharge control signal BLP transitions to the power supply potential Vcc, the seventh and eighth NMOS transistors N7 and N8 are turned on so that the bit line BL and the bit line bar ( / BL) is precharged to the bit line precharge voltage V _BLP at the same potential level. At this time, the sensing control signals '/ S' and 'RTO' signals are all precharged with the bit line precharge voltage V _BLP .

During the period t ₁ to t ₂ , the first bis signal bisu_BL and the first bisba signal bisu_ / BL are maintained at a power supply potential Vcc, and the bit line precharge control signal BLP and the bit are maintained. The line equalization signals blequ and bleqd are transitioned to the ground potential Vss, and the second bissign signal bisd_BL and the second bisva signal bisd_ / BL transition to the ground potential Vss. As a result, the seventh and eighth NMOS transistors N7 and N8 of the precharge unit 10 are turned off, so that the bit line BL and the bit line bar / BL are 'Vcc /'. It is maintained in a floating state disconnected from the outside while maintaining a potential of 2 '.

During the period t ₂ to t ₃ , the row decoder analyzes the row address input from the outside, selects one word line WL, and raises the potential to the potential of the high voltage Vpp. Accordingly, the charge of the memory cell connected to the selected word line WL is carried on the corresponding bit line, and the bit line BL voltage V _B is high when the data stored in the cell is high data ('1'). As shown in FIG. 3A, the voltage is increased by a predetermined potential, and when the data stored in the cell is row data '0', the value is lowered by a predetermined potential as shown in FIG. 3B. At this time, the potential of the opposite bit line bar / BL maintains the precharged potential 'Vcc / 2' without changing the potential.

During the period t ₃ to t ₄ , as the first bis signal bisu_BL transitions to the high voltage Vpp, the voltage of the bit line BL is increased by the gate capacitance of the first NMOS transistor N1.

When the potential difference ΔV between the bit line BL and the bit line bar / BL increases to some extent during the period t ₄ to t ₆ , the two sensing control signals / S , RTO is rapidly changed to ground potential (Vss) and power supply potential (Vcc), respectively, so that the potential of the bit line (BL) loaded with low data ('0') is discharged to the ground potential (Vss), and the opposite bit line bar The potential of / BL is charged to the power supply potential Vcc to complete the sensing operation. In the case of the high data ('1'), the two sensing control signals (/ S, RTO) are rapidly changed into the power supply potential (Vcc) and the ground potential (Vss), respectively, so that the bit line containing the high data ('1') The potential of BL is discharged to the power supply potential Vcc, and the potential of the opposite bit line bar / BL is charged to the ground potential Vss to complete the sensing operation.

Then, as the first bisva signal bisu_ / BL transitions to the high voltage Vpp, the voltage of the bit line bar / BL is increased by the gate capacitance of the second NMOS transistor N2. The potential difference ΔV between BL) and the bit line bar / BL is expressed by Equation 3 below (t ₅ ).

Here, C _B : bit line capacitance, C _S : cell capacitance, and C _OX : gate oxide capacitance of the first NMOS transistor N1 are shown.

During this time, the potential of the word line WL continues to maintain the high voltage Vpp, so the selected cell continues to be connected to the bit line BL and the bit line bar / BL so that the cell data voltage is automatically set to the ground potential Vss. ) Or power supply potential (Vcc). Thereafter, the data sensed by the column operation is loaded on the data bus so as to be read out from the outside.

After completion of the read operation, the potential of the word line WL is lowered to store the data of the memory cell, and the bit line precharge control signal BLP is transitioned back to the power supply potential Vcc in preparation for the next pupil. By turning on the seventh and eighth NMOS transistors N7 and N8 in the precharge unit 10, the potentials of both the bit line BL and the bit line bar / BL are changed to the bit line precharge voltage V _BLP . The bit line BL and the bit line bar / BL are shorted with each other by the bit line equalization signals blequ and bleqd to equalize.

That is, according to the present invention, when the memory cell is connected to the bit line, the voltage of the bit line bar / BL is first changed as the first bis signal bisu_BL transitions to the high voltage Vpp before the bit line sense amplifier operates. On the other hand, the voltage of the bit line BL is increased by the gate capacitance of the first NMOS transistor N1. Further, after the bit line sense amplifier operates, as the first bisbar signal bisu_ / BL transitions to the high voltage Vpp, the gate capacitance of the second NMOS transistor N2 causes the The voltage rises.

The present invention described above has been described only in the case where the memory cell is connected to the bit line BL, but the present invention can also be applied to the case where the memory cell is connected to the bit line bar / BL.

In brief, when the memory cell is connected to the bit line bar / BL, the first bisva signal bisu_ / BL is first transitioned to the high voltage Vpp before the bit line sense amplifier operates. Accordingly, while the voltage of the bit line BL is maintained as it is, the voltage of the bit line bar / BL is increased by the gate capacitance of the second NMOS transistor N2. In addition, as the first bis signal bisu_BL transitions to the high voltage Vpp after the bit line sense amplifier operates, the voltage of the bit line BL is increased by the gate capacitance of the first NMOS transistor N1. .

In conclusion, the potentials of the bit line BL and the bit line bar / BL are changed as the first bis signal bisu_BL and the first bisva signal bisu_ / BL of the prior art simultaneously transition to the high voltage Vpp. While the potential difference between the two ends is kept constant by the same rise, the present invention uses a different bit at a time when the first bis signal bisu_BL and the first bisva signal bisu_ / BL transition to the high voltage Vpp. By increasing the potential difference between the line (BL) and the bit line bar (/ BL), the potential difference between both ends can be increased to increase the sensing speed of the bit line sense amplifier.

Therefore, when the low data '0' is stored in the memory cell, the bit line BL voltage is lowered due to charge sharing of the memory cell, and the high data '1' is stored. In this case, the bit line BL voltage is increased by charge distribution of the memory cell. That is, if one of the voltages of the bit line BL and the bit line bar (/ BL) is increased by the gate capacitance of the bit line isolation transistor, in the case of the high data ('1'), the potential difference becomes large and the refresh characteristic is increased. On the other hand, in the case of the low data ('0'), the potential difference becomes small and the refresh characteristics become worse. However, when the low data '0' is stored due to the refresh characteristics of the DRAM, the refresh characteristic of the DRAM is improved because the refresh characteristic of several seconds is improved.

As described above, according to the present invention, the voltage increase effect due to the gate capacitance of the bit line isolation transistor is different from that of the gate signal of the pair of bit line isolation transistors that connect or disconnect between the memory cell and the bit line sense amplifier. By making the bit line BL and the bit line bar (/ BL) different from each other, a potential difference between the bit line BL and the bit line bar (/ BL) may be caused to improve read operation and refresh characteristics of the DRAM. .

Furthermore, the improvement of the refresh characteristics of the semiconductor device can not only increase the production of the product but also shorten the development period of the product.

Claims (5)

A memory cell array in which a plurality of memory cells are connected between a plurality of word lines and bit lines, a sense amplifier for comparing signals input through first and second input terminals, a first amplifier of the bit lines and the sense amplifiers; A semiconductor memory device comprising a first transistor connected between input terminals, and a second transistor connected between a bit line bar and a second input terminal of the sense amplifier. The first transistor is operated by applying a second bias voltage to the first transistor while a first bias voltage is applied to the first and second transistors, thereby increasing a potential of a bit line connected to a selected memory cell. And supplying a power supply voltage to the sense amplifier and operating the second bias voltage to the second transistor so that data stored in the memory cell is read by an operation of the sense amplifier. How to read data. A memory cell array in which a plurality of memory cells are connected between a plurality of word lines and bit lines, a sense amplifier for comparing signals input through first and second input terminals, a first amplifier of the bit lines and the sense amplifiers; A semiconductor memory device comprising a first transistor connected between input terminals, and a second transistor connected between a bit line bar and a second input terminal of the sense amplifier. A first bias voltage is applied to the gates of the first and second transistors and a read bias voltage is applied to the selected word line to raise the potential of the first input terminal to a first level higher than the potential of the second input terminal. A first step of making; A second step of applying a second bias voltage to the gate of the first transistor to raise the potential of the first input terminal to a second level; And After supplying a power supply voltage to the sense amplifier, a second bias voltage is applied to a gate of the second transistor to read data stored in the memory cell selected according to a potential difference between the first input terminal and the second input terminal. And a third step. The data reading method of the semiconductor memory device. The method of claim 2, Before the first step, turning on the third transistor to equalize the potentials of the bit line and the bit line bar, and then precharging the potentials of the first and second input terminals to a predetermined level. A data reading method of a semiconductor memory device. The method of claim 2, And the data stored in the memory cell is high data ('1'). The method of claim 2, When the data stored in the memory cell is row data ('0'), in the first step, the potential of the first input terminal is lowered to a first level lower than the potential of the second input terminal. How to read data from a memory device.