KR20030024680A - Print engine/controller and printhead interface chip incorporating the engine/controller - Google Patents

Abstract

The print engine / controller is suitable for use with drop-on-demand printheads. The print engine / controller works with compressed page data having both a two-level image plane compressed using the JPEG contone image layer and the Group 4 facsimile protocol. Receive a compressed image plane, achieve magnification and print in a pipelined manner. It is a tag that places a high speed serial interface 27 (such as a standard IEEE 1394 interface), a standard JPEG decoder 28, a standard group 4 fax decoder, a half toner / synthesis unit 29, and an infrared tag on a printed page. It consists of an encoder 30 and a line loader / formatter unit 31 for providing an interface 32 to the print head 33. Decoder 28 and 88 and encoder 30 are buffered with half toner / synthesis device 29.

Description

Print engine / controller and printhead interface chip incorporating the engine / controller}

The range of printer types has evolved in that images are constructed by selectively applying ink in the form of dots on a page. The inventor, Kia Silverbrook, entitled U.S. Patent No.6045710 entitled 'Self-aligning Configuration and Manufacturing Process of Monolithic Print Heads', describes a drop on demand printer and its manufacturing process. Prior art evaluations are described.

The microelectromechanical drop on demand print head, hereafter referred to as the Memjet print head, is filed simultaneously with the present application and described in a pending co-pending international application. It is hereby incorporated by reference as a cross reference.

PCT application number Our reference number PCT / AU00 / 00591 MJ62 PCT / AU00 / 00578 IJ52 PCT / AU00 / 00579 IJM52 PCT / AU00 / 00592 MJ63 PCT / AU00 / 00590 MJ58

Memjet print heads have been developed in print head segments, for example, where liquid ink can produce 1600 dpi two-level dots over the entire width of one page. Dots are easily created separately, which makes the most of distributed-dot dithering. The color side is printed as a complete record, allowing for ideal dot-on-dot printing. The print head uses microelectromechanical ink droplet technology to enable high speed printing.

Various methods, systems and apparatuses of the present invention are disclosed in the following pending applications filed concurrently with the present application by the applicant or assignee of the present invention.

PCT / AU00 / 00518, PCT / AU00 / 00519, PCT / AU00 / 00520,

PCT / AU00 / 00521, PCT / AU00 / 00522, PCT / AU00 / 00523,

PCT / AU00 / 00524, PCT / AU00 / 00525, PCT / AU00 / 00526,

PCT / AU00 / 00527, PCT / AU00 / 00528, PCT / AU00 / 00529,

PCT / AU00 / 00530, PCT / AU00 / 00531, PCT / AU00 / 00532,

PCT / AU00 / 00533, PCT / AU00 / 00534, PCT / AU00 / 00535,

PCT / AU00 / 00536, PCT / AU00 / 00537, PCT / AU00 / 00538,

PCT / AU00 / 00539, PCT / AU00 / 00540, PCT / AU00 / 00541,

PCT / AU00 / 00542, PCT / AU00 / 00543, PCT / AU00 / 00544,

PCT / AU00 / 00545, PCT / AU00 / 00547, PCT / AU00 / 00546,

PCT / AU00 / 00554, PCT / AU00 / 00556, PCT / AU00 / 00557,

PCT / AU00 / 00558, PCT / AU00 / 00559, PCT / AU00 / 00560,

PCT / AU00 / 00561, PCT / AU00 / 00562, PCT / AU00 / 00563,

PCT / AU00 / 00564, PCT / AU00 / 00565, PCT / AU00 / 00566,

PCT / AU00 / 00567, PCT / AU00 / 00568,

PCT / AU00 / 00569, PCT / AU00 / 00570, PCT / AU00 / 00571,

PCT / AU00 / 00572, PCT / AU00 / 00573, PCT / AU00 / 00574,

PCT / AU00 / 00575, PCT / AU00 / 00576, PCT / AU00 / 00577,

PCT / AU00 / 00578, PCT / AU00 / 00579, PCT / AU00 / 00581,

PCT / AU00 / 00580, PCT / AU00 / 00582, PCT / AU00 / 00587,

PCT / AU00 / 00588, PCT / AU00 / 00589, PCT / AU00 / 00583,

PCT / AU00 / 00593, PCT / AU00 / 00590, PCT / AU00 / 00591,

PCT / AU00 / 00592, PCT / AU00 / 00584, PCT / AU00 / 00585,

PCT / AU00 / 00586, PCT / AU00 / 00594, PCT / AU00 / 00595,

PCT / AU00 / 00596, PCT / AU00 / 00597, PCT / AU00 / 00598,

PCT / AU00 / 00517, PCT / AU00 / 00511, PCT / AU00 / 00501,

PCT / AU00 / 00502, PCT / AU00 / 00503, PCT / AU00 / 00504,

PCT / AU00 / 00505, PCT / AU00 / 00506, PCT / AU00 / 00507,

PCT / AU00 / 00508, PCT / AU00 / 00509, PCT / AU00 / 00510,

PCT / AU00 / 00512, PCT / AU00 / 00513, PCT / AU00 / 00514,

PCT / AU00 / 00515

Descriptions of these pending applications are incorporated herein by cross-reference.

The performance of such a print head is determined by the engine / controller. High speed printing is a problem in the development of both the printhead and its engine / controller. The page width print head enabled by the above technique requires an engine / controller capable of supplying a drop control signal at high speed. Typical page layouts include a mixture of images, graphics and text. Because of the nature of the microelectromechanical page width print head, each page can be printed at a constant speed to avoid the generation of visible artifacts. This means that the print speed does not need to be changed to match the input speed of the data. Rasterization of documents and printing of documents can be separated. To ensure that the print head has a constant data supply, the page should not be printed until it is completely rasterized. Ideally, you should rasterize before printing, which makes time to raster more complex pages. The engine / controller determines the extent to which these functions are realized.

The speed of the print head is determined by the development of both the print head and its engine / controller. The architecture of the print engine / controller needs to be designed to push large amounts of data into the print head at high speed.

[Summary of invention]

The print engine / controller according to one aspect of the present invention,

A contone image decoder;

A two-level compression decoder;

It includes a half-toner / compositor and a print head interface.

The print engine / controller provides, by a computer or print distribution system, the final steps of generating a page from independently formatted compressed page data, the steps of expanding the page image, dithering the continuous tone layer ( dithering, compositing a black layer on the continuous tone layer, adding an infrared tag to the infrared layer, and sending the synthesized image to the print head.

The print engine / controller preferably uses a high speed serial interface to receive compressed page data. The continuous tone image plane is decoded by a JPEG decoder and scaled by a half toner / synthesis device under margin unit control. The Group 4 facsimile decoder decodes the two-level image plane and scales with the half toner / synthesizer under margin unit control. The infrared tag encoder allows arbitrary infrared image planes to be placed to place the infrared ink printed tag on the printed page. The half toner / sum growth value includes a dither matrix access unit for dithering the continuous tone image plane by supplying dither data from the compressed page data.

In addition, the present invention provides an interface for receiving compressed page data, a continuous tone image decoder for decoding a contone image plane within the received compressed page data, and a two-level in the received compressed page data. Ink droplets including a two-level decoder for decoding the image plane and dither data, a half-toner / compositor for combining the two-level image plane on the continuous tone image plane, and a printhead driver for outputting the synthesized image with the print head. It further includes a print engine / controller for connecting with the print head.

The present invention relates to a print engine / controller (PEC) suitable for use within the scope of printer products. The present invention further relates to a print engine / controller realized by a print head interface chip.

1 is a diagram illustrating a data flow and a function executed by a print engine controller.

2 is a diagram illustrating a print engine controller associated with a schematic printer system structure.

3 is a diagram illustrating the architecture of a print engine controller.

4 is a diagram illustrating an external interface to the half toner / synthesis unit unit (HCU) of FIG. 3.

5 is a diagram illustrating an internal circuit related to the HCU of FIG. 4.

FIG. 6 is a block diagram showing a process in the dot merging unit of FIG.

FIG. 7 is a diagram illustrating a process in the dot realignment unit of FIG. 5.

FIG. 8 is a diagram illustrating a process in the line loader / format unit (LLFU) of FIG. 5.

9 is a diagram illustrating an internal circuit for generating color data in the LLFU of FIG. 8.

10 and 11 are diagrams illustrating components of the LLFU shown in FIG. 9.

Detailed Description of the Preferred Embodiments

In general, a 12 inch wide print head is controlled with one or more PECs to allow full-bleed printing of A4 and letter pages, as described below.

Six-channel color inks are the maximum expectations in the current printing environment, which are as follows.

ㆍ For full color printing, CMY.

For black text and other black printing;

ㆍ Tagable application, IR (Infrared).

F (fixing agent), which enables high speed printing.

The printer must be able to speed up printing, and a fixing agent capable of drying the ink at high speed is needed before the next page is finished printing. Otherwise, they bleed each other on the page. Fixing agents are not needed in low speed printing environments.

PEC is embedded in a single chip that connects to the printhead. Basically it includes four levels of functionality:

• Receive a compressed page through a serial interface, such as IEEE 1394.

Print engine for generating pages from compressed form. Print engine functions include enlarging the page image, dithering the continuous tone layer, compositing the black layer on the continuous tone layer, optionally adding an infrared tag, and sending the synthesized image to the print head. .

Print controller for controlling the print head and step motor.

Two standard low speed serial ports communicating with two QA chips. Note that there are two ports instead of a single port to ensure strong security during the authorization process.

1 shows a flow of data for sending a document to a printed page in a computer system. The document is received at 11 and loaded into memory buffer 12 where page layout is achieved and any necessary objects can be added. Pages from memory buffer 12 are rasterized at 13 and compressed at 14 before being sent to print engine controller 10. The page is received in the memory buffer 15 as a compressed page image in the print engine controller 10 and supplied to the page expander 16 where the page image is recovered. Any necessary dithering can be applied to any continuous tone layer at 17. Any black two-level layer can be synthesized on the continuous tone layer at 18 with an infrared tag of 19. The synthesized page data is printed at 20 to generate page 21.

The print engine / controller receives the compressed page image and begins to enlarge and print the page in a pipelined manner. Since it is not feasible to store a significant two-level CMYK + IR page image in memory, page magnification and printing is a pipeline where possible.

The first stage of the pipeline consists of a JPEG compressed continuous tone CMYK layer (shown below), a Group 4 fax compressed 2-level dither matrix selection map (shown below) and a Group 4 fax compressed 2-level black layer (bottom) Zoom in). In parallel with this, the tag encoder encodes two-level IR tag data from the compressed page image. The second step is to dither the continuous tone CMYK layer using the dither matrix selected by the dither matrix selection map, synthesize a two-level black layer on the synthesized two-level K layer, and add an IR layer to the page. Also, no matter which C, M, Y, K or IR channel is required, a fixation layer is created at each dot position. The final step is to print the two-level CMYK + K data through the print head via the print head interface (shown below).

2 shows how the print engine / controller 10 is installed within the schematic printer system structure. Various components of the printer system include the following.

Print engine / controller (PEC). The PEC chip 10 or chip is responsible for receiving a compressed page image for storage in the memory buffer 24, executing page enlargement, synthesizing a black layer, and transmitting dot data to the print head 23. have. It also provides a means for communicating with the QA chips 25, 26 to compensate printhead characteristics to ensure optimal printing. PEC is the subject of this specification.

Memory buffer. The memory buffer 24 is for storing compressed page images and for scratch use while printing a given page. The construction and operation of memory buffers are known to those skilled in the mood arts, and the range of standard chips and techniques for their use are used in the use of the PEC of the present invention.

Master QA chip. The master chip 25 is matched with the replaceable ink cartridge QA chip 26. The construction and operation of the QA unit is known in the art and a range of known QA processes is used in the use of the PEC of the present invention. For example, QA chips are described in co-pending US patent application.

US Application Number Our reference number title TBA AUTH01 Valid protocols and systems 09 / 112,763 AUTH02 Chip Protection Circuit Against IDD Unsafe Attacks 09 / 112,737 AUTH04 On-chip memory (flash and RAM) protection method 09 / 112,761 AUTH05 Chip Tamper Resistance Manufacturing Method 09 / 113,223 AUTH06 Physical object authentication system TBA AUTH07 Valid protocols and systems TBA AUTH08 Valid protocols and systems 09 / 505,003 AUTH09 Consumable Authentication Protocols and Systems 09 / 517,608 AUTH10 Consumable Authentication Protocols and Systems 09 / 505,147 AUTH11 Consumable Authentication Protocols and Systems 09 / 505,952 AUTH12 Unauthorized modification of values stored in flash memory TBA AUTH13 Security data handling system 09 / 516,874 AUTH14 Certified Chips Prevent Power Attacks TBA AUTH15 How to protect your confidential data

Since the QA communication chip not only drives the physical print head but also serves as an image enlargement, it is best included in the schematic functionality of the PEC chip. By installing the QA communication chip, it can be ensured that sufficient ink for printing a page is sufficient. Preferably, the QA chip embedded in the print head assembly is realized using an authentication chip. Since it is a master QA chip, it contains only an authentication key and no user data. However, it must match with the ink cartridge QA chip. The QA chip of the ink cartridge contains the information necessary to maintain the best print quality as possible, and is realized using an authentication chip. Preferably, a 64 MBit (8 MByte) memory buffer is used to store the compressed page image. The other page is read (double buffered) while one page is written to the buffer. In addition, the PEC uses memory to buffer the dot information computed while printing the page. While printing page N, the buffer is used for:

Read compressed page N

Read and write two-level dot information for page N

• Write compressed page N + 1

Preferably, the PEC chip includes a simple microcontroller CPU core 35 to perform the following functions.

Executes the QA chip authentication protocol via the serial interface 36 between the printed pages.

Drive the stepper motor via the parallel interface 91 during printing (the stepper motor requires a 5 ms process)

Synchronize different parts of the PEC chip during printing

• Provide a means of connecting to external data requests (programming registers, etc.)

Provide means for connecting with print head segment slow data requests (such as reading a characteristic vector and recording a pulse profile)

Provides a means for writing portrait and landscape tag structures to external DRAM

Since all image processing is performed by dedicated hardware, the CPU does not process the pixels. As a result, the CPU becomes very simple. Various known types of CPU cores are suitable: any processor core can be any processor capable of processing the necessary computation and control functions quickly enough. An example of a suitable core is the Philips 8051 microcontroller operating at about 1 MHz. CPU core 35 may be associated with a program ROM and a small program scratch RAM. The CPU communicates with other units in the PEC chip via memory-map I / O. The specific address area is placed in a specific register in a specific unit in each area. This includes a serial interface 36 and a parallel interface 91. Small program flash ROM is included in the PEC chip. The size is determined by the selected CPU, but is 8 KB or less. Similarly, small scratch RAM regions may be included in the PEC chip. The program code does not process the image, so it does not need a large scratch area. The size of the RAM is determined by the selected CPU (i.e. stack structure, subroutine call convention, register size, etc.) but is about 2KB or less.

The PEC chip using the above-described process based on the page width printhead can reproduce black at the maximum dot resolution (typically 1600 dpi), but it can reproduce continuous tone color using halftoning at a certain low resolution. have. Thus, the page technique is divided into a black two-level layer and a continuous tone layer. The black two-level layer is defined as the composite on the continuous tone layer. The black two-level layer consists of a bitmap containing one bit of opacity per pixel. This black layer matte has a resolution that is an integer element of the dot resolution of a printer. The maximum supported resolution is 1600 dpi, the maximum dot resolution of the printer. The continuous tone layer consists of a bitmap containing 32 bits of CMYK color per pixel, with K being optional. This continuous tone image has a resolution that is an integer element of the dot resolution of the printer. The maximum supported resolution is 320 ppi over 12 inches for a single PEC, ie 1/5 of the printer dot resolution. For higher continuous tone resolution, multiple PECs are required, each generating a strip of output pages. In addition, continuous tone resolution is generally an integer component of black two-level resolution to simplify the calculation in RIP. However, this is not a requirement. The black two-level layer and the contone layer are both in compressed form for efficient storage in the printer's internal memory.

3 shows a print engine structure. The print engine's page magnification and print pipeline includes a high speed serial interface 27 (such as a standard IEEE 1394 interface), a standard JPEG decoder 28, a standard Group 4 fax decoder, a custom halftoner / compositor unit 29, It consists of an order tag encoder 30, a line loader / formatter unit 31 and an order interface 32 to the print head 33. Decoder 28, 88 and encoder 30 are buffered in half toner / synthesis device 29. The tag encoder 30 sets an infrared tag or tag on the page according to a protocol according to the purpose of the page, and the actual content of the tag is not a subject of the present invention.

The print engine works with a double buffer. While one page is loaded into DRAM 34 via DRAM interface 89 and data bus 90 on high speed serial interface 27, the previously loaded page is read from DRAM 34, which leads to a print engine pipeline. To pass. Once the page printing is finished, the immediately loaded page becomes the printed page, and the new page is loaded through the high speed serial interface 27. In the first step, the pipeline expands any JPEG compressed continuous tone (CMYK) layer and any Group 4 fax compressed two-level data streams. The two streams are mats that choose between a black layer (PEC is actually color agnostic, but this two-level layer can be directed to any output ink) and dither matrix for continuous tone dithering (shown below). In parallel with the first step, in the second step, any tag that is later rendered with IR or black ink is encoded. Finally, in the third step, the continuous tone layer is dithered, and the position tag and the two-level spot one layer are synthesized on the synthesized two-level dither layer. The data stream is ideally adjusted to create a smooth transition across the redundant segments in the print head and ideally to compensate for dead nozzles in the print head. In this step, up to six channels of two-level data are generated. Note that all six channels do not exist on the print head. For example, the print head may be just CMY, where K is pushed into the CMY channel and IR is ignored. Optionally, if IR ink is not available (or for testing purposes), the location tag may be printed in K. The synthesized two-level CMYK-IR dot data is buffered and formatted for printing on the print head 33 through a set of line buffers (shown below). Most of these line buffers are ideally stored on the off chip DRAM 34. The final step prints six channels of two-level dot data via the print head interface 32.

Compression is used in printing systems that use PEC. This not only reduces the memory required for page storage, but also reduces the bandwidth required between the host and the PEC. At 267 ppi, the letter page of continuous tone CMYK data has a size of 25 MB. By using a lossy continuous tone compression algorithm such as JPEG (shown below), the continuous tone image is compressed to a ratio of 10: 1 without significant loss of quality, resulting in a 2.5MB compressed page size. At 800 dpi, a letter page of two-level data has a size of 7 MB. Adherent data such as text is compressed very well. By using a lossless two-level compression algorithm such as Group 4 facsimile (shown below), the 10 point text is compressed at a ratio of about 10: 1, giving a compressed page size of 0.8 MB. Once dithered, a page of CMYK contone image data consists of 114 MB of two-level data. The two-layer compressed page image format described below utilizes the relative strengths of lossy JPEG contone image compression and lossless two-level text compression. The format is compact enough to be effectively stored and simple enough to allow direct real-time magnification during printing. Since the text and images do not overlap normally, the normal worst case page image size is 2.5 MB (i.e. images only) and the normal best case page image size is 0.8 MB (i.e. text only). In the absolute worst case, the page image is 3.3 MB (that is, the text added to the image). Assuming a quarter of the average page containing the image, the average page image size is 1.2 MB.

The Group 3 facsimile compression algorithm (ANSI / EIA 538-1988, Facsimile Coding Schemes and Coding Control Functions for Group 4 Facsimile Equipment, August 1988) provides lossless 2-level data for transmission over slow and noisy telephone lines. Can be used to compress. The two-level data displays black text and graphics scanned on a white background, and the algorithm is adjusted for this kind of image (eg for two-level images of midtones, not explicitly adjusted). The 1D group 3 algorithm runs-encodes each scan line and then Huffman-encodes the resulting run length. Run lengths in the range 0-63 are coded with terminating codes. Run lengths ranging from 64 to 2623 are encoded with a make-up code followed by a termination code, each representing a multiple of 64. Run lengths greater than 2623 are coded with a number of makeup codes followed by an exit code. The Huffman table is fixed, but adjusted independently for black and white runs (except for common 1728 and higher makeup codes). If possible, the 2D Group 3 algorithm encodes the scan line as a set of short edge deltas (0, ± 1, ± 2, ± 3) with reference to the previous scan line. Delta symbols (eg, zero delta symbols are 1 bit long) are entropy-encoded. Edges in 2D-encoded lines that cannot be delta encoded are run length encoded and identified by the prefix. 1D and 2D-encoded lines are displayed differently. 1D-encoded lines are generated at regular intervals to ensure that the decoder can recover from the noise of the line with minimal image degradation. 2D group 3 achieves a compression ratio of 6: 1 (Urban, SJ, "Review of standards for electronic imaging for facsimile systems", Journal of Electronic Imaging, Vol. 1 (1), January 1992, 5-21 Page).

The Group 4 facsimile algorithm (ANSI / EIA 538-1988, Facsimile Coding Schemes and Coding Control Functions for Group 4 Facsimile Equipment, August 1988) loses two-level data for transmission on error-free communication lines. Compress without (i.e., there are exactly no errors in the line, or error correction was done at a low protocol level). Since the Group 4 algorithm is assumed to have no errors in transmission, it is based on the 2D Group 3 algorithm, which is a fundamental variant that 1D encoded lines are no longer generated at regular intervals as a help for error recovery. Group 4 achieves a compression ratio in the range of 20: 1 to 60: 1 for the CCITT set of test images. The design purpose and performance of the Group 4 compression algorithm makes it suitable for the compression algorithm for the two-level layer. However, the Huffman table is adjusted to low scan resolution (100-4000 dpi), making it difficult to encode run lengths exceeding 2623. At 800 dpi, the maximum run length is now 6400. Group 4 decoder cores can be used in PEC, but they cannot handle run lengths beyond the 400dpi facsimile application normally encountered, so modifications are needed. The black layer (typically 1600 dpi) is compressed losslessly using a G4 Fax with a typical compression ratio of more than 10: 1. Dither matrices (typically 320 dpi) match with continuous tone color layers and use G4 Fax to select layers that are losslessly compressed (typically 320 dopi) with a typical compression ratio of more than 10: 1.

The Group 4 Fax decoder is responsible for decompressing the two-level data. The two-level data is limited to a single spot color (typically black for text and line graphics), and the dither matrix selects the bitmap for use in subsequent dithering of the continuous tone data (uncompressed with a JPEG decoder). The inputs to the G4 Fax decoder are two sides of the two-level data read out from the external DRAM. The output of the G4 Fax decoder is two sides of decompressed two-level data. The decompressed two-level data is sent to the Half Toner / Synthesis Unit (HCU) in the print pipeline for the next step. Two two-level buffers provide a means of transferring two-level data between the G4 Fax decoder and the HCU. Each decompressed two-level layer is output to two line buffers. Each buffer can hold up to 12 inches of dot lines at the maximum resolution expected. By having two line buffers, the other line is recorded by the G4 Fax decoder while one line is read by the HCU. This is important because a single two-level line is generally 1600 dpi or less and therefore must be enlarged in both dot and line dimensions. If the buffering is below the maximum line, the G4 Fax decoder decodes the same line many times, once every 600 dpi dot line.

Spot color 1 is designed so that a single color plane of the output image becomes high resolution dot data. The continuous tone layer provides the proper resolution for the image, and spot color 1 is targeted for applications such as text and line graphics (usually black). When text and line graphics are used, typical compression ratios exceed 10: 1. Spot color 1 varies the resolution up to 1600 dpi for maximum print quality. Thus, each of the two line buffers is a total of 2400 bytes (12 inches x 1600 dpi = 19,200 bits).

The resolution of the dither matrix selection map ideally matches the continuous tone resolution. Naturally, each of the two linebuffers is thus 480 bytes (3840 bits) and can store 12 inches at 320 dpi. If the map matches the continuous tone resolution, the typical compression ratio exceeds 50: 1.

800 dpi spot color 1 layer (normally black)

ㆍ 320dpi dither matrix selection layer

To support this, the decompression bandwidth required is 9.05 MB / sec for 1 page / sec performance (regardless of page width 12 inches or 8.5 inches), and 12 during the printer's maximum speed performance (30,000 lines / sec). 20MB / sec and 14.2MB / sec, respectively, for page widths of inches and 8.5 inches. Given that the decompressed data is output to the line buffer, the G4 Fax decoder can easily decompress the lines in each output one at a time.

The G4 Fax decoder is supplied directly from main memory via the DRAM interface. The amount of compression determines the bandwidth required for external DRAM. G4 Fax is lossless, so complex images impact the amount of data, or bandwidth. In general, the 800 dpi black / text / graphic layer exceeds a compression of 10: 1, so the bandwidth required to print one page / second is 0.78 MB / second. Similarly, a 320dpi dither selection matrix typically compresses above 50: 1, resulting in a bandwidth of 0.025MB / sec. A high speed printing configuration of 320 dpi for the dither selection matrix and 800 dpi for spot color 1 requires bandwidths of 1.72 MB / sec and 0.056 MB sec, respectively. Thus, the total bandwidth of 2MB / sec is more than enough for DRAM bandwidth.

G4 Fax decoding functionality is realized with the G4 Fax decoder core. Various G4 Fax decoder cores are suitable and can be any core with sufficient processing power to execute the necessary computation and control functions at high speed. It can handle run lengths beyond the 400dpi facsimile application it normally encounters, and needs to be modified.

The JPEG compression algorithm (ISO / IEC 19018-1: 1994, Information technology-Digitalcompression and coding of cintinuous-tone still image: Requirements and guidelines, 1994) losslessly compresses a continuous tone image at a predetermined quality level. It employs fine image degradation with a compression ratio of 5: 1 or less and minor image degradation with a compression ratio of 10: 1 or less (Wallace, GK, "The JPEG Still Picture Compression Srandard", Communication of the ACM, Vol. 34 , No. 4, April 1991, pp. 30-44). In general, JPEG first converts an image into a color space that separates luminance and chrominance into independent color channels. This results in the chroma channel being subsampled without significant loss, since the human visual system is more sensitive to luminance than chroma. After this first step, each color channel is compressed independently. The image is divided into 8x8 pixel blocks. Each block is then transformed into the frequency domain via discrete cosine transform (DCT). This conversion has the effect of concentrating image energy at relatively low frequency coefficients, and the high frequency coefficients are more incompletely quantized. This quantization is the main principle of compression in JPEG. Compression is also achieved by aligning the coefficients with a frequency to maximize the likelihood of adjacent zero coefficients, and then run length-encoding a run of zeros. Finally, run length and nonzero frequency coefficients are coded entropy. Decompression is the reverse process of compression.

The CMYK (or CMY) contone layer is compressed into a flat color JPEG byte stream. If luminance / saturation separation is deemed necessary, CMYK is converted to YCrCb and Cr and Cb are appropriately subsampled for table sharing or chroma subsampling. The JPEG byte stream is complete and self-sufficient. Contains all data needed for decompression, including quantization and Huffman tables.

The JPEG decoder is responsible for performing on-the-fly decompression of the continuous tone data layer. The input to the JPEG decoder extends to four sides of continuous tone data. This is generally three sides displaying a CMY continuous tone image or four sides displaying a CMY continuous tone image. In general, even if all color planes have the same resolution, each color plane can be of different resolution. The contone layer is read from an external DRAM. The output of the JPEG decoder is decompressed continuous tone data separated by planes. The decompressed contone image is sent to the half toner / compositor (HCU) 29 in the print pipeline for the next step. The four-sided continuous tone buffer provides a means for transferring the continuous tone data between the JPEG decoder and the HCU 29.

Each color plane of decompressed continuous tone data is output in a set of two line buffers (shown below). Each line buffer is 3840 bytes, so it can hold 12 inches of single color plane pixels at 320 ppi. Line buffering causes the other line buffer to be written by the JPEG decoder while one line buffer is read by the HCU. This is important because a single continuous tone line is generally 1600 dpi or less and therefore must be enlarged in both dot and line dimensions. If the buffering is less than or equal to the entire line, the JPEG decoder decodes the same line many times and once for each output 600 dpi dot line. Various resolutions are supported, but there is a tradeoff between resolution and available bandwidth. As the resolution and number of colors increase, so does the required bandwidth. In addition, the number of segments targeted by the PEC chip also affects bandwidth and possible resolutions. Note that since the contone image is processed in a flat format, each color plane may be stored at a different resolution (eg, CMY may be a higher resolution than the K plane). The maximum supported continuous tone resolution is 1600 ppi (matching the printer's maximum dot resolution). However, it is sufficient to output the line buffer memory to maintain enough continuous tone pixels for a 320 ppi line of 12 inches in length.

Note that if up to 12 inches of output is required at higher continuous tone resolution, the final output on the printer will still be only two-level, but will require multiple PEC chips. By supporting four colors at 320 ppi, the decompression bandwidth required is one page / second performance (regardless of whether the page width is 12 inches or 8.5 inches) is 40 MB / second, and the printer's maximum speed performance (30,000 lines / second). While page widths of 12 inches and 8.5 inches are 80 MB / sec and 64 MB / sec, respectively.

The JPEF decoder is supplied directly from main memory via the DRAM interface. The amount of compression determines the bandwidth required for external DRAM. As the level of compression increases, the bandwidth decreases but the quality of the final output image may also decrease. DRAM bandwidth for a single color plane can be easily calculated by applying the compression rate to the output bandwidth. For example, a single color plane with a compression ratio of 10: 1 at 320 ppi requires 1 MB / second access to the DRAM to produce 1 page / second. JPEG functionality is realized by the JPEG core. Various JPEG cores may be suitable and may be any core having sufficient processing power to execute the necessary calculation and control functions at a sufficiently high speed. For example, the BTG X-Match core has a decompression speed of 140 MBytes / sec, and decompression of four color planes with continuous tone resolution of 400 ppi for maximum printer speed (30,000 lines / sec at 1600 dpi) and printer speed of 1 page / sec. For up to 800 ppi.

Note that the core is only needed to support decompression and reduces the need imposed by the more common JPEG compression / decompression core. The size of the core is not expected to be more than 100,000 gates. Given that the decompressed data is output to the linebuffer, the JPEG decoder can easily decompress the entire line one at a time for each color plane, thus reducing context switching during one line, Simplify control Four contexts must be maintained (one context for each color plane) and include the current address in the external DRAM as well as the appropriate JPEG decoding parameters.

The half toner / synthesizer unit (HCU) 29 of FIG. 4 makes the continuous tone (typically CMYK) layer halftoning for the same two-level version, and spots on the appropriate halftone continuous tone layer. 1 Has the ability to synthesize two-level layers. If the printer does not have K ink, the HCU 29 can map K to CMY dots as if dedicated. It also selects between two dither matrices based on sequential pixels and is based on corresponding values in the dither matrix selection map. Inputs to the HCU 29 include an enlarged continuous tone layer (in the JPEG decoder unit) passing through the buffer 37, an enlarged two-level spot1 layer passing through the buffer 38, generally buffer 39. Dither matrix selection bitmap enlarged to the same resolution as the continuous tone layer passing through and tag data of the maximum dot resolution passing through the buffer 40. The HCU 29 uses up to two dither matrices read out from the external DRAM 34. The output from the HCU 29 to the line loader / format unit (LLFU) at 41 is a set of printer resolution two-level image lines on six color planes. Generally, the continuous tone layer is CMYK or CMY and the two-level Spot1 layer is K.

5 shows the HCU in more detail. Once started, the HCU proceeds until it detects the end condition of the page or is explicitly stopped through its control register. The first task of the HCU is to scale, at each scale unit, such as scale unit 43, all data received on a buffer side, such as 42, to printer resolution, both horizontally and vertically.

The scale unit provides means for scaling continuous tone or two-level data at printer resolution in both horizontal and vertical. Scaling is accomplished by copying the data values in integer multiples in both dimensions. The process of scaling data is known to those skilled in the art.

Two control bits, an advance dot and an advance line are provided to the scale unit 43 by the margin unit 57. Advanced dot bits cause the state machine to generate multiple examples of the same dot data (useful for page margins, and generate dot data for duplicate segments in the printhead). The advance line bit cuts data in accordance with the printer margin, since the state machine is controlled when a particular dot line ends. In addition, the end point logic of a predetermined line required in the scale unit is omitted. The input to the scale unit is the entire line buffer. A line is used the number of scale elements to achieve vertical upscaling through line copying, and within each line, each value is used the number of scale elements to achieve horizontal upscaling through pixel copying. If the input line is used the number of scale elements (advanced line bits set the number of scale elements), the input buffer selection bits of the address are toggled (double buffering). Since the scale unit only generates an address, the logic of the scale unit is the same for 8 bits and 1 bit.

Each continuous tone layer can be of different resolution and therefore scaled independently. The two-level Spotl layer in buffer 45 and the dither matrix selection layer in buffer 46 also need to be scaled. The two-level tag data in the buffer 47 is determined to be corrected resolution, but does not need to be scaled. The scale up dither matrix select bit is used by the dither matrix access unit 48 to select a single 8-bit value from the two dither matrices.

The 8-bit value is output to four comparators 44, 49 to 51 that simply compare with a predetermined 8-bit continuous tone value. The generation of the actual dither matrix is determined by the structure of the print head, and the general process of generating the dither matrix is known to those skilled in the art. If the continuous tone value is greater than or equal to the value of the 8-bit dither matrix, 1 is the output. Otherwise, 0 is output. Then, these bits are all ANDed with the inPage bits from the margin unit 57 (whether or not a specific dot is in the printable area of the page) at 52 to 56. The final stage of the HCU is the synthesis stage. For every six output layers there is a single dot merging unit, such as 58, with six inputs each. The single output bit from each dot merging unit is a combination of some or all of the input bits. This allows spot colors to be placed on any output color plane (including test infrared), blacks mixed with cyan, magentas mixed with yellow (without black ink in the print head), and tag dot data. To be placed on the visible surface. Fixing color faces can also be easily produced. The dot reconstruction unit (DRU) 59 regards a given color plane as a generated dot stream, and organizes it into 32-bit quantities so that the output is within the segment order and the dot order within the segment. Due to the fact that dots for duplicate segments are not generated in segment order, minimal realignment is required.

Two control bits, an advanced dot and an advanced line are provided to the scale unit by the margin unit 57. Advanced dot bits cause the state machine to generate multiple instances of the same dot data (useful for page margins, generating dot data for duplicate segments in the printhead). The advance line bit cuts data in accordance with the printer margin, since the state machine is controlled when a particular dot line ends. In addition, the end point logic of a predetermined line required in the scale unit is omitted.

The comparator unit includes a simple eight bit "grater-than-or-equal" comparator. It is used to determine if the 8-bit continuous tone value is greater than or equal to the 8-bit dither matrix value. By itself, the comparator unit accepts two 8-bit inputs, producing a single 1-bit output.

6 shows the details of the dot merging unit. It provides a means of mapping two-level dither data, Spot1 color and tag data to output ink to the actual print head. Each dot merging unit accepts six 1-bit inputs to produce a single bit output that indicates the output for the color plane. The output bit at 60 is a combination of any or all of the input bits. This allows spot colors to be placed on any output color plane (including test infrared), blacks mixed with cyan, magentas mixed with yellow (without black ink on the print head), and tag dot data. To be placed on the visible surface. The output for the fixation agent can be easily generated by simply combining all the input bits. The dot merging unit includes a six bit color mask register 61 which is used as a mask for six input bits. Each input bit is ANDed with the corresponding color mask register bit, and then the six synthesized bits are ORed together to form the final output bit.

In Fig. 7, a dot reorganization unit (DRU) is shown in which a given color plane is regarded as a generated dot stream, and is organized in 32-bit quantities so that the output is in the segment order and the dot order in the segment. Due to the fact that dots for duplicate segments are not generated in segment order, minimal realignment is required. The DRU includes a 32 bit shift register, a regular 32 bit register and a regular 16 bit register. The 5-bit counter remembers the number of bits processed so far. The dot advance signal from the dither matrix access unit (DMAU) is used to instruct the DRU for the bit to be output.

Register A 62 in Fig. 7 is written every cycle. It contains the most recent 32 dots generated by the dot merging unit (DMU). By means of a WriteEnable signal generated by the DRU state machine 64 via a simple 5-bit counter, a complete 32-bit value is copied into register B 63 every 32 cycles. Sixteen odd bits (bits 1, 3, 5, 7, etc.) from register B 63 are copied to register C 65 using the same WriteEnable pulse. The 32-bit multiplexer 66 is then selected from the following three outputs based on two bits from the state machine.

Full 32 bits from register B

A 32-bit value consisting of 16 even bits of register A (bits 0, 2, 4, 6, etc.) and 16 even bits of register B. Sixteen even bits from register A form bits 0-15, and sixteen even bits from register B form bits 16-31.

• A 32-bit value consisting of 16 odd bits of register B (bits 1, 3, 5, 7, etc.) and 16 odd bits of register C. The bits in register C form bits 0-15, and the odd bits from register B form bits 16-31.

A state machine for the DRU is shown in Table 1. It starts in the 0 state. It changes every 32 cycles. For 32 cycles, a single noOverlap bit collects the AND of all dot advance bits for 32 cycles (NoOverlap = dot advance for cycle 0, and NoOverlap = NoOverlap AND dot advance for cycles 1 to 31). )

State machine for DRU condition Nooverlap Print Output validity exegesis Next status 0 X B 0 Startup status One One One B One Regular nonredundant One One 0 B One A contains the first duplicate 2 2 X Even A, Even B One A contains the second redundancy B contains the first redundancy 3 3 X C, odd B One C contains the first redundancy B contains the second redundancy One

The margin unit (MU) 57 in FIG. 5 converts the advanced dot and advanced line signals from the dither matrix access unit (DMAU) 48 into a general control signal based on the page margin of the current page. It also creates a page endpoint condition. The MU calculates the dots and lines that cross the page. Both are set to zero at the beginning of the page. Each time the MU receives a dot advance signal from the DMAU, the dot counter advances by one. When the MU receives a line advance signal from the DMAU, the line counter is incremented and the dot counter is reset to zero. The cycle, current line and dot values are compared to the margin of the page, and based on these margins, a signal within the appropriate output dot advance, line advance and margin ranges is given. DMAU contains only the actual memory required for the HCU.

8 shows a line loader / format unit (LLUF). It receives the dot information from the HCU, loads the dots for a given print line into the appropriate buffer storage (some on chip and some on external DRAM 34) and formats them in the order required for the print head. A high level block diagram of the LLFU for its external interface is shown in FIG. Input 67 to the LLFU is a set of six 32-bit words and one DataValid bit, all generated by the HCU. The output 68 is a set of 90 bits representing up to 15 print head segments in six colors. Not all output bits may be valid and are actually determined by how many colors are used for the print head.

In the nozzles of two offset rows, the actual position of the jet nozzle on the print head described above means that the odd and even dots of the same color are on two different lines. The even dot is at L and the odd dot is at line L-2. In addition, there are a number of lines between one color dot and another color dot. Since six color planes are calculated at one time by the HCU at the same dot position, it is necessary to delay the dot data for each color plane until the same dot is located under an appropriate color nozzle.

The size of each buffer line is determined by the width of the print head. A single PEC produces dots up to 15 print head segments, so a single odd or even buffer line is 15 sets of 640 dots for a total of 9600 bits (1200 bytes). For example, the buffers required for odd numbers of six colors are approximately 45 KBytes in total.

If manufacturing techniques are available, the full set of necessary buffers is installed on the PEC chip. Otherwise, the front buffer of color 2 is stored in the external DRAM. This can make the PEC effective even if the distance between the color planes later changes. Since everything is printed according to a particular dot line (no additional line buffer is needed), it is trivial to keep even dots of color 1 on the PEC. In addition, the two halflines needed to buffer color one odd dots save substantial DRAM bandwidth.

To have clean edges, all zeros need to be preloaded in various line buffers (on-chip and DRAM) before the page is printed. The page endpoint is automatically generated by the HCU and then has a clean edge.

FIG. 10 shows a block diagram for color N OESplit (see Oesplit 70 in FIG. 9), and in FIG. 9 a block diagram for each of the two buffers E and F 71, 72 is shown in FIGS. 10 and 11. Will be on. The buffer EF is a double buffer structure for transferring data to the print head interface (PHI) 32 of FIG. Thus, buffers E and F have the same structure. During processing of the dot line, it is written into one of the two buffers and read from the other. Upon receipt of the line-sync signal from the PHI, the two buffers are logically swapped. Both buffers E and F consist of six sub buffers, and as shown in Fig. 11, one sub buffer per color and one color sub buffer are numbered 73. Each sub buffer is 2400 bytes in size. For example, 1280 dots per segment is sufficient to hold 15 segments. The memory is accessed 32 bits at a time, and there are 600 addresses for each subbuffer (requires 10 bits of address). All even dots are placed in preference to odd dots in the sub buffer of each color. If there is any free space (to print fewer than 15 segments), it is placed at the end of the subbuffer of each color. The amount of memory actually used in each subbuffer is directly related to the number of segments actually addressed by the PEC. For a 15-segment print head, there are 1200 bytes of odd dots without empty space followed by 1200 bytes of even dots. Advantageously the number of subbuffers used is directly related to the number of colors used in the print head. The maximum number of colors supported is six.

The addressing of the decoding circuit of each buffer E and F is a given cycle, and a single 32-bit access can be made to all six subbuffers that are read in all six subbuffers or written to one of six subbuffers. Only one bit of the 32 bits read from each color buffer is selected for a total of six output bits. The process is shown in FIG. A 15-bit address uses a 10-bit address to select 32 bits to read a particular bit, and a 5-bit address selects 1 bit from 32 bits. Since all color subbuffers share this logic, a single 15-bit address outputs a total of six bits, one bit per color. Each subbuffer 73-78 has a line WriteEnable such that a single 32-bit value is written to a particular color buffer within a given cycle. Each recordable signal is generated by ANDing a single recordable input to the decoded form of ColorSelect. Since only one buffer actually writes data in, 32 bits of data In are shared on line 79.

Address generation for reading from buffers E and F is simple. Generates 1 bit per cycle, used to get 6 bits representing 1 bit per color for a particular segment. By adding 640 to the current bit address, it proceeds to the equivalent dot of the next segment. Add odd 640 (not 1280) because odd and even dots are separated in the buffer. This number segment (NumSegment) is executed to recover the data representing even dots and transfer these bits to PHI. If NumSegment = 15, the number of bits is 90 (15 x 6 bits). Thereafter, the process is repeated for odd dots. This entire even / odd bit generation process is repeated 640 times with increasing start address each time. All dot values are thus transferred to the PHI in the required order by the print head in the 640 × 2 × NumSegment cycle. If NumSegment = 15, the number of cycles is 19,200 cycles. Note that 6 bits (1 bit from each color buffer) are generated for a given read cycle, regardless of the number of colors actually used in the print head.

In addition, a TWriteEnable control signal for writing 90 bits to the Transfer register 90 of FIG. 9 is generated. Since LLFU begins before PHI, it delivers a first value prior to the advance pulse from PHI. In addition, the following values are also generated in preparation for the first advance pulse. The solution is to transfer the first value to the Transfer register after the NumSegment cycle, then delay the NumSegment cycle later, and wait for the advance pulse to start the next NumSegment cycle group. When the first advance pulse arrives, the LLFU is synchronized to PHI.

The reading process for a single dot line is shown in the following pseudocode:

DoneFirst = FALSE

WantToXfer = FALSE

For DotInSegment 0 = 0 to 1279

If (DotInSegment0: bit0 == 0)

CurrAdr = DotInSegment0 (high bits) (puts in range 0 to 639)

Endif

XfersRemaining = NumSegments

Do

WantToXfer = (XfersRemaining == 0)

TWriteEnable = (WantToXfer AND NOT DoneFirst) OR PHI: ADVANCE

DoneFirst = DoneFirst OR TWriteEnable

Stall = WantToXfer AND (NOT TWriteEnable)

SWriteEnable = NOT (Stall)

If (SWriteEnable)

Shift Register = Fetch 6 bits from EFSense [ReadBuffer]: CurrAdr

CurrAdr = CurrAdr + 640

XfersRemaining = XfersRemaining-1

Endif

Until (TWriteEnable)

Endfor

Wait until BufferEF Write process has finished

EFSense = NOT (EFSense)

While the read process transfers from buffer E or F to PHI, the write process prepares the next dot line in another buffer.

The data recorded in the buffer E or F are the color 1 data generated by the HCU and the color 2-6 data (supplied from the DRAM) from the buffer D. Color 1 data is written to buffer EF each time the Output Valid flag of the HCU is set, and color 2-6 data is written from register C for another period.

Buffer OE ₁ 81 in FIG. 9 is a 32-bit register used to hold a single HCU generation set of 32 consecutive dots for color one. While the dots are continuous on the page, odd and even dots are printed at different times.

The buffer AB 82 is a double buffer structure for delaying odd data for color 1 to 2 dot lines. Thus, buffers A and B have the same structure. During processing of the dot line, one of the two buffers is read and written. After the entire dotline has been processed, the two buffers are logically swapped. The single bit flag ABSense determines which of the two buffers is read and written.

The HCU provides 32 bits of color 1 data whenever the output validity control flag, which is every 32 cycles after the first flag is sent on the line, is set. The 32 bits define a continuous set of 32 dots-16 even dots (bits 0, 2, 4, etc.) and odd dots (bits 1, 3, 5, etc.) for a single dot line. The output validity control flag is used as WriteEnable control for the OE ₁ register 81. HCU data is processed for every two Output Valid signals. The 16 even bits of the HCU color 1 data are combined with the 16 even bits of the register OE ₁ to produce 32 bits of even color 1 data. Similarly, 16 odd bits of HCU color 1 data are combined with 16 odd bits of register OE ₁ to produce 32 bits of odd color 1 data. Upon receipt of two groups of first output validity signals, buffer AB is read to transfer odd data to color 1 in buffer EF, 73 in FIG. Upon receipt of the two groups of second output validity signals, 32 bits of odd data are written at the same location in the previously read buffer AB, and 32 bits of even data are written to color 1 in the buffer EF.

The HCU provides 32 bits of data per color plane whenever the output validity control flag is set. This happens every 32 cycles except during any startup time. The 32 bits define a continuous set of 32 dots-16 even dots (bits 0, 2, 4, etc.) and odd dots (bits 1, 3, 5, etc.) for a single dot line.

While buffer OE ₁ (83 in Figure 10) is used to store a single 32-bit value for color 1, buffers OE ₂ through OE ₆ are each used to store a single 32-bit value for colors 2-6. . Just as the data for color 1 is separated into 32 bits representing color 1 odd dots and 32 bits representing color 1 even dots, every 64 cycles (once every 2 output validity flags), the remaining color planes are even and odd dots. To be separated.

However, instead of writing directly to the buffer EF, the dot data is delayed by a number of lines and written to the DRAM through the buffer CD (84 in FIG. 9). While the dot for a given line is written to the DRAM, the dot for the previous line is read from the DRAM and written to the buffer EF 71,72. This process is inserted between the processes of writing the color 1 to the buffer EF.

Each time an output validity flag is received from the HCU on line 85 in FIG. 10, 32 bits of color N data are written to buffer OE _N 83. For each second output validity flag, a combined 64-bit value is written to color buffer N 86. This occurs in parallel for all color planes 2-6. Color buffer N 86 contains 40 sets of 64-bits (320 bytes) so that dots for two complete segments can be stored. This causes the complete segment generation count (20 x 64 = 1280 cycles) to be written to the DRAM for both previous segment data (both odd and even dots). Generation of a write address is simple. The ColorNWriteEnable signal on line 87 is given per second output validity flag. The address starts at 0 and increments every second output validity flag until 39. Instead of proceeding to 40, the address is reset to zero, providing a double buffering configuration. This works as long as no read occurs during the output validity flag, and previous segment data can be written to the DRAM in time to generate single segment data. The process is shown in the following pseudo code:

adr = 0

firstEncountered = 0

While (NOT AdvanceLine)

If (HCU_OutputValid) AND (firstEncountered))

ColorNWriteEnable = TRUE

ColorNAdr = adr

If (adr == 39)

adr = 0

Else

adr = adr + 1

Endif

Else

ColorNWriteEnable = FALSE

Endif

If (HCU_OutputValid)

firstEncountered = NOT (firstEncountered)

Endif

EndWhile

As it relates to the timing for DRAM access (both read and write), buffer EF access, and color 1 occurrence, the address generation for reads is a tricker. It is described in more detail below.

Address generation for buffers C, D, E, F and color N are all related to the timing of DRAM access and do not interfere with color 1 processing for buffers E and F. The basic principle is that data for a single segment of color N (odd or even dots) is transferred from the DRAM to the buffer EF via the buffer CD. When data is read from the DRAM, these dots are compensated based on the value of ColorBufferN. This was done for each color in odd and even dots. After the complete segment value of the dot has accumulated (20 sets of 64 cycles), the process starts again. If data for all segments in a given print line is delivered to the DRAM, then the current address is advanced for the color DRAM buffer so that the appropriate number of lines until the specific data for the color line is read from the DRAM. Thereafter, DRAM operates in the form of a FIFO. Thus, while copying color N (same odd / even sense) to buffer C, color N (odd or even) is read from DRAM to buffer D. Copying data into buffer C takes 20 or 21 cycles depending on whether the output validity flag will occur during 20 transfers. When both tasks are terminated (usually DRAM access becomes a slower task), the second part of the process begins. The data in buffer C is written to the DRAM (the same position is read directly), and the data in buffer D is copied to buffer EF (again, color 1 data is transferred, so that color N data is not generated while the output validity flag is set). Is not passed to the buffer EF). When both tasks end, the same processing occurs for each of the other senses of color N and the remaining colors. The entire duplex process occurs 10 times. Thereafter, the address for each of the current lines in the DRAM is updated to begin the process of the next line.

In terms of bandwidth, DRAM access to the dot data buffer consumes most of all DRAM access from the PEC. For each print line, the entire dot line is read for color 2-6 and the entire dot line is written for color 2-6. For up to 15 segments, this is equivalent to 2x5x15x1280 bits = 192,000 (24,000 bytes) / print line. For a high speed printing system (30,000 lines / second) this is equivalent to 687 MB / second. The bandwidth required for printing one page / second is 312 MB / second. Because the bandwidth is so high, the addresses of the various halflines for each color in DRAM are optimized for the type of memory used. For example, in an RDRAM memory system, the first first half-line buffer is adjusted to a 1 KByte boundary for each color to maximize page hits on DRAM access. As the various segments are processed, if the start of the next segment is to be adjusted to 960 bytes within a 1 KByte page, then 640 bit access needs to be guaranteed to reach 2 pages. Thus, the variable DRAMMaxVal is used to check this case, and if generated, the address for the page aligned next half line buffer is rounded off. Thus, the waste is only 64 bytes per 13 segments, which has the advantage of full 640 bit access within a single page.

The address generation process can be considered as 10 sets of NumSegment values consisting of 20x32-bit reads followed by 20x32-bit writes and can be shown as the following pseudocode:

EFStartAdr = 0

Do NumSegments times:

For CurrColor = 0 to MaxHalfColors

DRAMStartAddress = ColorCurrAdr [CurrColor]

While reading 640 bits from DRAMStartAddress into D (> = 20 cycles)

ColorNAdr = 0

While (ColorNAdr! = 20)

If (NOT HCU_OutputValid)

Transfer ColorNBuffer [ColorNAdr | CurrColor_bit0] to

C [ColorNAdr]

ColorNAdr = ColorNAdr + 1

Endif

EndWhile

EndWhile-wait until read has finished

While writing 640 bits from C into DRAMStartAddress (> = 20 cycles)

ColorNAdr = 0

EFAdr = EFStartAdr

While (ColorNAdr! = 20)

If (NOT HCU_OutputValid)

Transfer D [ColorNAdr] to EF [CurrColor | EFAdr]

If ((ColorNAdr == 19) AND (CurrColor == NumHalfColors))

EFStartAdr = EFAdr + 1

Else

EFAdr = EFAdr + 1

Endif

ColorNAdr = ColorNAdr + 1

Endif

EndWhile

EndWhile-wait until write has finished

If (DRAMStartAddress == DRAMMaxVal)

ColorCurrAdr [currColor] = round up DRAMStartAddress to next 1KByte page

Else

ColorCurrAdr [currColor] = DRAMStartAddress + 640 bits

Endif

If (Segment == maxSegments)

If (ColorCurrRow [CurrColor] == ColorMaxRow [CurrColor])

ColorCurrRow [currColor] = ColorStartRow [currColor]

ColorCurrAdr [currColor] = ColorStartAdr [currColor]

Else

ColorStartRow [currColor] = ColorCurrRow [currColor] + 1

Endif

Endif

Endfor

Enddo

Wait until next Advance signal from PHI

Note that the MaxHalfColors register does not contain color 1, but is at least one less than the number of colors in terms of odd and even colors processed individually. For example, in terms of a standard six-color printing system, if there are 10 (colors 2-6 at odd and even), MaxHalfColors is set to 9.

The LLFU requires 2 NumSegments cycles to prepare 180 bits of first data for PHI. Thus, the print head starts, and a first LineSync pulse occurs at this time after the LLFU starts. This makes the initial Tansfer value valid and prepares the next 90-bit value to be loaded into the Tranfer register.

The print head interface PHI is a means for the processor to load the dots to be printed on the print head and to control the actual dot print processing. It is input from LLFU and outputs data to the print head itself. PHI can handle a variety of print head lengths and formats. The internal configuration of the PHI allows up to 6 colors, 8 segments per transfer and up to 2 segment groups. This is sufficient for a 15-segment (8.5-inch) printer capable of printing A4 / Letter with complete bleed.

Throughout the specification, it is intended to describe preferred embodiments of the present invention without limiting any other embodiment or specific set of features. Those skilled in the art can realize variations of certain embodiments that fall within the scope of the invention.

Claims (14)

An interface for receiving compressed page data; A continuous tone image decoder for decoding a compressed continuous tone image plane in the received compressed page data; A two-level decoder for decoding a compressed two-level image plane in the received compressed page data; A half toner / compositing device for dithering the continuous tone image plane and synthesizing two-level image plane data with an output plane; A print engine / controller for driving a drop print head having a print head driver for outputting a composite to the print head. The method of claim 1, And the interface is a high speed serial interface. The method of claim 1, And the continuous tone image decoder is a JPEG decoder. The method of claim 1, And the continuous tone image decoder outputs the individual color planes of the decoded image to individual buffers in front of the half toner / synthesizer. The method of claim 1, A print engine / controller, wherein the page data in each continuous tone image plane is scaled by a half toner / synthesizer. The method of claim 1, And said two-level decoder is a group four facsimile decoder. The method of claim 1, And the two-level decoder decodes the compressed two-level image plane in the received compressed image plane toward each buffer in front of the half toner / compositor. The method of claim 1, A page engine in a two-level image plane is scaled with a half toner / synthesis device. The method of claim 1, A print engine / controller, further comprising an infrared tag encoder for generating an infrared image plane for placing a tag printed with infrared ink on a printed page. A continuous tone image decoder for decoding the compressed continuous tone image plane in the received compressed page data; A two-level decoder for decoding the compressed two-level image plane; A print engine / controller for driving an ink drop print head, comprising a half-toner / compositing device including a dot merging unit controlled by a color mask to achieve integration of an image plane provided with ink in the print head. A continuous tone image decoder for decoding the compressed continuous tone image plane in the received compressed page data; A two-level decoder for decoding the compressed two-level image plane; A print engine / controller for driving an ink drop print head, comprising a half toner / synthesis device including a margin unit, for supplying margin data to each image plane during the synthesis process. An interface for receiving compressed page data; A continuous tone image decoder for decoding the continuous tone image plane in the received compressed page data; A two-level decoder for decoding the two-level image plane in the received compressed page data; A half-toner / compositing device for dithering a continuous tone image plane and synthesizing a two-level image plane with an output plane; A print engine / controller chip connected with an ink drop print head, comprising a print head driver for outputting the composite to the print head. An interface for receiving compressed page data; A continuous tone image decoder for decoding the continuous tone image plane in the received compressed page data; A two-level decoder for decoding the two-level image plane in the received compressed page data; A half toner / compositing device for dithering the continuous tone image plane and synthesizing the two-level image plane with the output plane; A print head driver for outputting the composite to the print head; An ink drop printer driven by a print engine / controller having a print head. Receiving compressed page data; Decoding a contone image plane in the received compressed page data to produce an output plane; Decoding a two-level image plane in the received compressed page data to produce an output plane; Dithering the contone image plane, and synthesizing the two-level image plane with the output plane; An ink droplet printer operating method comprising the step of transmitting the synthesized data to the print head.