KR20030013050A - Wordline Enable Drive Circuit of Semiconductor Memory Device - Google Patents

Abstract

PURPOSE: A word line enable driving circuit of semiconductor memory device is provided to be capable of reducing a word line enable time by removing a boosting margin. CONSTITUTION: A boost voltage generating circuit(300) receives an external power supply voltage and generates a high voltage(Vpp) and a boosted voltage. A row decoder(200) is supplied with the boosted voltage from the boost voltage generating circuit as a power supply voltage, and outputs a normal word line enable signal(NWE) of the boosted voltage level in response to row address signals. A row address pre-decoder(40) receives other row address signals and generates four decoded address signals(DRAij). A control signal generating circuit(30) generates a control signal(PX) and an inverted control signal(PXB) in response to output signals of the pre-decoder. A sub-word line driver(100) is connected to a word line, and enables the word line in response to the normal word line enable signal of the boosted voltage level, the control signal, and the inverted control signal.

Description

Word line enable drive circuit of semiconductor memory device

The present invention enables word line enablement without a self boosting operation of a sub word line driver (SWD) of a semiconductor memory device, thereby eliminating boosting margins. A word line driving circuit of a semiconductor memory device capable of shortening a word line enable time.

Recently, as the trend toward higher integration and higher speed of semiconductor memory devices is accelerated, researches for storing more information in a smaller area and increasing the speed thereof have been conducted in various fields.

In particular, the design aspect, that is, the arrangement and wiring of the memory circuit, and the implementation of a new concept of circuit to achieve this high integration and high speed trend.

1 is a block diagram showing a schematic configuration of a conventional semiconductor memory device.

As shown in the drawing, a conventional semiconductor memory device may include a plurality of normal wordline enable signals NWE0 to NWEi, corresponding to a plurality of row address signals RA2 to RAi. A row decoder 50 generating a NWE, and a column generating a plurality of column select line signals corresponding to the plurality of column address signals CA0 to CAi. By the combination of a decoder (Column Decoder) 60, a memory cell array 10 in which a plurality of memory cells are arranged in a row direction and a column direction, and another plurality of row address signals RA0, RA0B, RA1, and RA1B. The output of the row address predecoding unit 40 and the row address predecoding unit 40 which generate four decoding row address (DRAij) signals, that is, DRA01, DRA0B1, DRA01B, and DRA0B1B are input. My A PX signal generator 30 for generating signals PX0 to PXi (hereinafter referred to as PX) and an inversion control signal (PX0B to PXiB, hereafter referred to as PXB), respectively, and an NWE signal that is an output of the row decoder 50; It consists of a SWD (20) for receiving the PX and PXB signals that are the output of the PX signal generator 30, boosts and outputs a word line enable signal.

At this time, the four DRAij signals output by the row address pre-decoding unit 40, that is, DRA01, DRA0B1, DRA01B, and DRA0B1B, are in a standby state, that is, maintain a high level when the semiconductor memory device is deactivated. When the semiconductor memory device is activated, only one of the four DRAij signals transitions to the low level.

In addition, the PX signal and the PXB signal output from the PX signal generator 30 maintain the low level and the high level in the standby state of the semiconductor memory device, respectively, and the semiconductor memory device is activated so that one of the four DRAij signals is low. Transitioning to the PX and PXB signals corresponding to the transitioned DRAij signal transitions from the low level to the high level and from the high level to the low level, respectively.

On the other hand, SWD (20) is a device for transmitting a sufficient high voltage (VPP) level to the word line through the self-boosting after receiving the NWE signal and the PX and PXB signal as mentioned above, the configuration is shown in FIG. same.

As shown, the SWD 20 is composed of four NMOS transistors, namely a first NMOS transistor 21, a second NMOS transistor 22, a third NMOS transistor 23, and a fourth NMOS transistor 24. .

When the semiconductor memory device is in the standby state, the NWE, PX, and PXB signals are in a low level, a low level, and a high level, respectively, so that the fourth NMOS transistor 24 is turned on to ground the voltage level of the word line. Maintain at the voltage (Vss) level.

However, when the semiconductor memory device is activated and the NWE signal is enabled at the high level, the PX and PXB signals transition from the low level to the high level and the high level to the low level, respectively, so that the second NMOS transistor 22 boosts the NWE. Driven to node B, the first NMOS transistor 21 self-boosts the voltage of boosted node B via a parasitic capacitor generated by itself and transfers it to the word line.

The reason why the voltage is boosted through the SWD 20 is that each memory cell is composed of a capacitor and a transistor to store data in the capacitor and to control the input and output to the transistor. This is because the data cannot be completely inputted and outputted, and therefore the enable signal must be supplied to the word line at a voltage level higher than the high voltage level VPP (a boost value by the Vpp + NMOS transistor).

Therefore, by supplying the word line enable voltage boosted through the SWD 20 to the word line, when the data input and output to the memory cell consisting of the capacitor and the transistor, the data can not be completely input and output to the capacitor can be compensated for will be.

3 is a timing diagram illustrating states of signals involved in the operation of the SWD 20.

When the NWE signal is enabled at high level, the voltage at boost node B rises to a certain level, and when PX is enabled at high level, voltage at boost node B is boosted to a voltage sufficient to enable word lines, thereby providing a word line. This will be enabled.

At this time, a certain time delay must exist between the enable time of the NWE signal and the enable time of the PX signal, which is called a boost margin. In order to perform word line enable correctly, sufficient boost margin must be secured.

This is because if the boost margin is not sufficiently secured, the boost node B is transferred to the word line without being boosted to a voltage sufficient for the word line enable, so that the word line enable time is long or the data of the memory cell is sansed. This is because data failing may occur due to insufficient charge sharing with the amplifier (Sense Amp).

Therefore, according to the word line structure of the semiconductor memory device described above, the boost margin is an essential element.

However, such boosting margins ensure sufficient word line enablement, but are also a kind of time delay, resulting in a problem of reducing the word line enable rate.

Accordingly, there is a need for a word line enable circuit of a semiconductor memory device which eliminates such a boost margin to increase the word line enable rate while ensuring sufficient boost for the word line enable.

The present invention was devised in this background, and generates a boosted voltage separately and supplies it to the power supply voltage of the low decoder, and the low decoder outputs the NWE signal of the boosted voltage level to the SWD, and in the SWD, a word without a separate boosting process. It is an object of the present invention to provide a word line enable circuit of a semiconductor memory device to perform line enable, thereby eliminating the boost margin to shorten the word line enable time.

1 is a block diagram showing a schematic configuration of a conventional semiconductor memory device.

2 is a circuit diagram showing a conventional sub word line driver configuration.

3 is a timing diagram illustrating states of signals involved in an operation of a conventional sub word line driver.

4 is a block diagram illustrating a word line enable circuit of a semiconductor memory device according to an exemplary embodiment of the present invention.

5 is a circuit diagram illustrating a configuration of a sub word line driver according to an exemplary embodiment of the present invention.

6 is a flowchart illustrating an operation of a word line enable circuit of a semiconductor memory device according to an exemplary embodiment of the present invention.

7 is a timing diagram illustrating a state of a signal according to an operation of a word line enable circuit.

<Description of the symbols for the main parts of the drawings>

30: PXi generator

40: row address predecoding unit

100: sub word line driver

200: low decoder

300: boosted voltage generation unit

In order to achieve the above object, the present invention, in the word line enable driving circuit for enabling the word line of the semiconductor memory device, generating a boosted voltage to generate a voltage of a high voltage and a boosted voltage level by receiving a voltage from an external power supply voltage And a row decoder configured to receive a boosted voltage generated by the boosted voltage generator as a power supply voltage and output an NWE signal at a boosted voltage level in response to a plurality of row address signals RA2 to RAi transmitted from the outside. A row address pre-decoding unit for receiving four row row signal combinations RA0, RA0B, RA1, and RA1B other than one row address signal and generating four decoded row address signals DRAij; A control signal and an inverted control signal are received by receiving the output decoded row address signal. Receiving the output signal generation portion and the PX, and the NWE signal PX and PXB signal of the step-up voltage level output from the row decoder is composed of SWD for enabling the word line.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In addition, it should be noted that the same reference numerals are given to the same components, although belonging to different drawings for convenience of understanding.

4 is a block diagram illustrating a word line enable circuit of a semiconductor memory device according to an exemplary embodiment of the present invention.

As shown, the word line enable circuit includes a boosted voltage generator 300, a row decoder 200, a row address predecoder 40, a PX signal generator 30, and a SWD 100. It is composed.

The boosted voltage generator 300 receives a voltage from an external power supply voltage and generates a voltage having a high voltage Vpp and a boosted voltage level.

At this time, the boosted voltage compensates for the voltage loss due to the threshold voltage of the transistor in the memory cell, so that the word line enable can be sufficiently performed, that is, the voltage boosted by the conventional SWD 20 (Vpp + NMOS transistor). It is preferable to set more than the boost value by).

The row decoder 200 receives a boosted voltage from the boosted voltage generator 300 and generates a NWE signal corresponding to a plurality of row address signals. The generated NWE signal is a boosted voltage level and is output. The NWE signal is output to the SWD (100).

The row address pre-decoding unit 40 generates four DRAij signals, that is, DRA01, DRA0B1, DRA01B, and DRA0B1B by a combination of a plurality of row address signals other than the above-described row address signals.

The PX signal generator 30 receives the output of the row address predecoder 40 as an input, outputs the PX and PXB signals, and applies the same to the SWD 100.

The SWD 100 receives the NWE signal of the boosted voltage level and the PX and PXB signals, which are outputs of the PX signal generator, from the row decoder 200 to enable word lines, and the configuration thereof is illustrated in FIG. 5. As described above, the SWD 100 is composed of three transistors (a fifth NMOS transistor 101, a sixth NMOS transistor 102, and a seventh NMOS transistor 103).

In this case, the fifth NMOS transistor 101 is connected to an output terminal and a gate terminal of the row decoder 200 and controlled by the NWE signal, and a PX signal is applied to the source terminal. In addition, the sixth NMOS transistor 102 has a gate terminal connected to the output terminal of the PX signal generator and controlled by the PX signal, and an NWE signal having a boosted voltage level is applied to the source terminal. Meanwhile, the seventh NMOS transistor 103 is connected to the PXB output terminal and the gate terminal of the PX signal generator 30 and controlled by the PXB signal, and the PX signal is applied to the source terminal.

6 is a flowchart illustrating an operation of a word line enable circuit of a semiconductor memory device according to an exemplary embodiment of the present invention.

First, the boosted voltage generator 300 generates a boosted voltage by receiving power from an external power supply voltage (step: S1).

The row decoder 200 receives a plurality of row address signals from the outside and generates an NWE signal for enabling a word line in response to the row decoder 200 (step S2) and transmits the same to the SWD 100.

At this time, since the row decoder 200 receives and uses the boosted voltage generated from the boosted voltage generator 300 as its power source, the output NWE is at the same voltage level as the boosted voltage level.

Meanwhile, the row address predecoder 40 receives four DRAij signals DRA01, DRA0B1, DRA01B, and DRA0B1B after receiving a combination of a plurality of row address signals other than the row address signal input to the row decoder 200. (Step S3).

Subsequently, the PX signal generation unit 30 receives the DRAij signal generated by the row address pre-decoding unit 40, outputs the PX and PXB signals (step S4), and applies it to the SWD 100.

The SWD 100 receives the NWE signal having the boosted voltage level and the PX and PXB signals output from the PX signal generator 30 from the row decoder 200 to enable the word line without a separate boost operation.

That is, when the semiconductor memory device is in the standby state, since the NWE, PX, and PXB signals are in the low level, the low level, and the high level, respectively, the seventh NMOS transistor 103 is turned on to turn on the voltage level of the word line. Keep at the ground voltage (Vss) level, but if the semiconductor memory device is enabled and the NWE signal at the boosted voltage level is enabled at high level, then the PX and PXB signals will transition from low level to high level and from high level to low level, respectively. (Step S5) The fifth NMOS transistor 101 and the sixth NMOS transistor 102 are turned on (step: S6), so that the boost voltage is transferred to the word line and the word line is enabled. (Step: S7)

7 is a timing diagram showing the state of each signal in this process. When the NWE signal is enabled in the boosted voltage state and input to the SWD, and at the same time, the state of the node A becomes the boosted voltage level when the PX signal is input, the word line is enabled. This will be done.

As such, since the NWE signal input to the SWD 100 is a boost voltage level capable of sufficiently enabling the word line from the input, the boost is unnecessary.

Therefore, since the SWD 100 does not need a boosting process through the boosting node B as in the related art, a time delay due to securing a boosting margin can be shortened, thereby increasing the word line enable rate.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will appreciate that the present invention may be modified without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Therefore, changes in the future embodiments of the present invention will not be able to escape the technology of the present invention.

As described above, according to the present invention, since the boosted voltage is generated and supplied to the power supply voltage of the low decoder, and the low decoder outputs the NWE signal at the boosted voltage level and supplies the SWD to the SWD, the word does not need a separate boosting process in the SWD. Line enable is possible.

Accordingly, the word line enable time can be shortened by removing the boost margin, thereby increasing the processing speed of the semiconductor memory device.

Claims (3)

A word line enable driving circuit for enabling a word line of a semiconductor memory device, A boosted voltage generator configured to receive a voltage from an external power supply voltage and generate a voltage having a high voltage and a boosted voltage level; A row decoder receiving a boost voltage generated by the boost voltage generator as a power supply voltage and outputting a normal word line enable signal at the boost voltage level in response to a plurality of row address signals transmitted from an external device; A row address predecoding unit configured to receive a plurality of row address signal combinations other than the row address signal and generate four decoded row address signals; A control signal generator for receiving a decoded row address signal output from the row address pre-decoder and outputting a control signal and an inverted control signal; A sub word line driver connected to a word line of the semiconductor memory device and receiving the normal word line enable signal of the boosted voltage level output from the row decoder, the control signal, and the inverted control signal to enable the word line; And a word line enable driving circuit of the semiconductor memory device. The semiconductor memory device of claim 1, wherein the boosted voltage is a voltage obtained by adding the high voltage to a voltage capable of compensating for a voltage loss due to a threshold voltage of a transistor in a memory cell of the semiconductor memory device. Word line enable drive circuit. The method of claim 1, wherein the sub word line driver, A first NMOS transistor connected to an output terminal of the row decoder and a gate terminal and controlled by the normal word line enable signal, and to a source terminal of the first NMOS transistor; A second NMOS transistor connected to an output terminal of the control signal generator and controlled by the control signal, and having a normal word line enable signal of the boosted voltage level applied to a source terminal; A gate terminal is connected to an output terminal of the control signal generator and controlled by the inversion control signal, and a source terminal includes a third NMOS transistor to which the control signal is applied. Circuit.