KR20030009250A - Control method and apparatus for operations of flash memory system - Google Patents

Abstract

PURPOSE: A method and device for controlling operation of flash memory are provided to be capable of improving an operating speed of a flash memory device and elongating the life of the flash memory device. CONSTITUTION: A logic address is received from a host computer, and the received logic address is converted into a physical address. Data from the host computer is written at a location of a flash memory device appointed by the physical address. When the appointed location is linked, a linked location is previously written by valid data, and a frequency of use of the linked location is higher than a reference voltage, the valid data of the appointed location is shifted into the linked location(134,150,152,154). When a frequency of use of the linked location is lower than a reference voltage, the valid data of the linked location is shifted into another linked location(134,136,142,148).

Description

Method and apparatus for controlling flash memory operation {Control method and apparatus for operations of flash memory system}

The present invention relates to a memory semiconductor technology, and more particularly to a flash memory operation control method and a control device that can improve the operation speed of the flash memory.

Advantages of flash memory include data retention even after a power outage, faster data reads and vibrations than hard disks, and lower cost than SRAM. On the other hand, a feature of flash memory is that when data is written (written or programmed) to a memory cell block, even if it is some pages or sectors of the block, all the blocks must be erased and then written. The size of the unit is different from that of the program (or recording). Therefore, it takes a long time to write data to the flash memory, and there is a problem that the life of the flash memory becomes shorter as the number of write operations increases as the erase operation must be preceded before writing. The conventional erasing operation of flash memory has been performed in various ways. The flash memory is divided into blocks or sectors (they can be erased individually but only one at a time), and then the desired block is selected and the data of the block is selected. After moving to a temporary storage device such as RAM, it is common to write data in a predetermined portion of the block in the selected block and restore the data stored in the temporary storage device to the original block for the remaining blocks. In the more advanced prior art, the flash memory is divided into sectors and all the cells in each sector are erased at once, while each sector selection and addressing are separately performed for the erase operation. In this way, a combination of sectors to be erased simultaneously can be arbitrarily selected, thereby reducing the time required for the erase operation.

However, according to this conventional erasing method, since unnecessary additional operations still exist, problems of overall performance degradation and operation time delay of the memory system remain. For example, in the conventional flash memory system as shown in FIG. 1, the write operation is performed as follows.

(1) The flash memory controller 20 receives a logical address (LA) designating a place to write data from the host 10.

(2) The memory controller 20 converts a logical address into a physical address (PA).

(3) In the memory block including the converted physical address, the rest of the data except for the portion to be written is backed up to the buffer. For example, in the memory array 30 of FIG. 1, each of the plurality of memory units or banks 30A, 30B,..., 30N is a plurality of memory blocks 30A1, 30A2..., 30AM; 301B, 30B2,..., 30BM; 30N1, 30N2, 30NM, and each memory block is composed of a plurality of pages or sectors 32; If the physical address to which data is to be written includes the page 36A included in the first memory block 30A1 of the first memory 30A, the second memory block 30B2 of the second memory 30B may be used. Suppose you include the page 36B contained in the data buffer in the memory controller 20. The data in the memory controller 20 is stored in pages 34A and 34B where data is not written before writing data to the pages 36A and 36B. Back up your data by moving to.

(4) The block containing the page designated by the logical address (blocks 30A1 and 30B2 in the above example) is erased.

(5) The memory controller 20 receives data to be written from the host 10.

(6) The memory controller 20 programs the data received from the host 10 to a location designated as a logical address (pages 36A and 36B in the above example).

(7) The data backed up in the previous step (3) is taken from the data buffer of the memory controller 20 and restored to its original position (e.g., pages 34A and 34B).

In such a conventional system, an operation of erasing the entire block and programming data at a designated location is essential, but an operation of backing up and restoring data is a kind of unnecessary additional operation according to the characteristics of the flash memory. Thus, for example, when the size of a unit for a program and a size of a unit (ie, a memory block) for erasing are different from each other, a lot of time is required for a backup or write operation required for such an additional operation. In addition, since a data read (or read) operation is involved in backing up the data, the time for the additional operation is further increased.

The present invention is to overcome the disadvantages of such a conventional flash memory system, to improve the operating speed of the flash memory and to extend the life of the flash memory.

1 is a block circuit diagram showing a write operation of a flash memory system according to the prior art.

2 is a flowchart showing a data recording operation according to the present invention;

Fig. 3 is a detailed flowchart showing the operation when the linked block is not a free block in the data write operation according to the present invention.

4 is a flow chart illustrating a BiT / link table update operation in accordance with the present invention.

5 is a data structure diagram showing a structure of BiT information and link information.

6 is a data structure diagram showing a structure of an ST table.

7 is a block circuit diagram showing the overall structure of a flash memory control system to which the present invention can be applied.

8 is a block circuit diagram illustrating a storage structure of a flash memory and an operation process of the flash memory.

9 is a block diagram showing an information structure of a memory block to which the present invention can be applied.

10 is a flowchart showing a data read operation of a flash memory;

Fig. 11 is a flowchart showing an erase operation of a block in which invalid data is recorded according to the present invention.

12 is a flowchart illustrating a process of moving data between different blocks in accordance with the present invention.

<Description of Major Symbols in Drawing>

10, 300: host system 20, 310: flash memory controller

30, 320: flash memory array 312: control chip

314: flash control block 316: ECC

322, 324: memory bank 210: BiT information structure

220: link information structure 230: ST information structure

350: block information structure

The flash memory control method according to the present invention comprises the steps of receiving a logical address from a host system, converting the received logical address into a physical address, and storing data received from the host system by the physical address. Writing to a location (eg, a basic block). In the recording step, the storage location (basic block) of the designated flash memory is linked, the linked storage location (primary link block) is already recorded as valid data, and the utilization of the linked storage location is higher than the reference value. If larger, the valid data of the designated storage location is moved to the linked storage location, and if the utilization of the linked storage location is less than a reference value, the valid data of the linked storage location is another linked storage. Moving to a location. Here, the reference value is determined as a value that minimizes the time taken to move data in different memory blocks. The movement of data from the basic block to the primary link block is performed when the host system using the flash memory as the data storage device is in an idle state. In addition, an erase operation may be performed on the memory block in which invalid data is recorded in the storage location of the flash memory when the host system is in the idle state.

The flash memory operation control apparatus according to the present invention transfers data between the host system and the flash memory and controls the operation of the flash memory. Here, the flash memory is composed of a plurality of memory blocks, each of the plurality of memory blocks is composed of a plurality of pages / sectors, the plurality of memory blocks are designated by a physical address corresponding to a logical address transferred from the host system A basic block, a primary link block to which this basic block is linked, and a secondary link block to which this primary link block is linked. The flash memory operation control apparatus writes data received from a host system to the flash memory, and when validity of the primary link block is greater than a reference value, moves valid data of the basic block to the primary link block. And means for moving valid data of the primary link block to the secondary link block when the degree of use of the secondary link block is smaller than the reference value. After moving the data, we change the BiT / Link table and ST table for that block. The BiT / Link table changes the base block address, the chip address for the base block, the link block address, the chip address for the link block, and the link status. The ST table includes data representing valid data record information and invalid data record information.

Description of the Invention Terms used are as follows.

Flash memory data storage structure: memory array → memory bank → memory unit → block → page / sector (pages and sectors may be the same depending on memory capacity, and pages may be larger than sectors (eg 1G or more)).

BiT / Link table: A table indicating information about the position of each block in the flash memory and whether the corresponding block is linked or whether a current program operation can be performed. For example, the table includes a physical address, a link address, and link state data.

ST (Status Table) table: A table indicating the status of each block of flash memory, indicating whether the corresponding block is available (eg, a free block) or already used. Blocks that have already been used can be divided into valid data (Used Block) and invalid data (Dirty Block) .The invalid data write block does not need the data in the block anymore. Indicates that it is necessary.

Flash memory operation control unit: A link is a block unit, a program or a write unit is a page unit, an erase unit is a block unit, and a unit for obtaining data from a host unit is a sector (or page) unit.

Embodiment

Embodiments of the present invention will be described below with reference to the drawings.

2 and 3 show the overall flow of the flash memory operation control method according to the present invention. 2 and 3 are flowcharts of a write operation to the flash memory, first receiving an address from the host system to which data is to be written (step 100). The host system here includes a portable electronic device such as a PC and a digital camera, an MP3 player, and the data is transferred in sectors or pages, for example. The address received from the host system is a logical address. The logical address in the block information table (BiT) / link buffer is checked (step 101). The BiT / Link buffer refers to a buffer that holds the address of the flash memory block, the movement of the erase block, and the link data in the memory (eg, SRAM) in the controller that controls the operation of the flash memory. If there is information on the logical address corresponding to the BiT / link buffer, the process proceeds directly to the logical address search step 105 based on this data. If information on the logical address cannot be found in the BiT / link buffer, the BiT in the flash memory is found. The relevant data is read from the / link table (step 103) and then a physical address is found based on this data (step 105).

After converting the logical address into a physical address in step 105, data to be written is received from the host (step 107), and the state of the memory block corresponding to the physical address is checked (step 109). If the block is not linked (path A), the block is linked but the linked block is free block (ie, erase operation is performed on the block). (Path B), if the block is linked and other data is already written in the linked block, so that data cannot be written directly to the link block (path C). Is it.

In the case of the path A in which the flash memory block specified by the physical address is not linked, the free block address is found (step 110), and host data is programmed in this free block (step 112). Since data is recorded in the free block, the status table (ST) of the block is changed from 'free' to 'used data write (used)' (step 114). In the ST table, if both the bit representing the valid data record and the bit representing the invalid data record are '0', for example, the corresponding block is a 'free block'. Therefore, in the ST table change step 114, the bit representing the valid data recording block is changed from '0' to '1'. After changing the ST table, the BiT / link table is changed by recording the link address and link state in the BiT / link table corresponding to the physical address (step 116). That is, the link address indicating the position of the link block is recorded in the BiT / link table, and the bit of the link information corresponding to the page on which the data is recorded is changed to '1', for example.

On the other hand, in the case of the path B in which the linked block is a free block although the link is performed, host data is recorded in the free block designated by the link address (step 120), and the BiT / link information of the block is changed (step 122). ). In this case, the link address does not change in the BiT / Link table and changes the information of the linked page.

On the other hand, in the case of the path C in which the linked block is linked and not the free block, other valid data is already recorded in the linked block (i.e., the primary link block) as shown in FIG. Another free block address is found (step 130), and host data is written to the found free block (i.e., secondary link block) (step 132). After the data is recorded, it is determined whether the utilization of the primary link block (that is, the percentage of the area in which valid data is recorded in one block) exceeds a predetermined reference value (step 134). Here, the reference value is determined as a value that minimizes the time taken to move data between different blocks. For example, the reference value may be 1/2, but is not necessarily limited to 1/2.

If the utilization of the primary link block is less than the reference value in the determination step 134, the primary link block data is moved to the secondary link block (step 136). When the data movement step is finished, the ST tables of the primary link block and the secondary link block are changed (step 142), and the BiT / link information of the basic block is changed (step 148).

On the other hand, if the use degree of the block in the determination step 134 is equal to or greater than the reference value, the valid data in the block (base block) corresponding to the physical address converted in step 105 is moved to the primary link block ( Step 150), the ST table change step 152 for the basic block and the primary link block, and the BiT / link table change step 154 are performed. For example, the ST table of the basic block is changed from 'valid data record (Used)' to 'invalid data record (Dirty'), and the link address in the BiT / link table is changed from the primary link block to the secondary link block.

As can be seen from the operation of the flash memory of Figure 3 and the control method thereof, the present invention does not use the backup and restore operations that occur in all write or program operations in the conventional flash memory system, so the write operation of the flash memory Speed can be greatly improved. In addition, by selectively controlling the data movement according to the block usage of the flash memory, it is possible to maximize the efficiency of the data backup or restore operation.

4 shows the flow of the update operation of the BiT / Link table.

Changing the BiT / link data in the flash memory write operation described above with reference to FIG. 3 is to write data to the BiT / link table (step 170). After writing the data, the block corresponding to the BiT / link table is written. It is determined whether the data is full (ie, full) (step 172). If the BiT / link block is not full, the BiT / link data on the SRAM of the flash memory operation controller is corrected (step 180), the BiT / link data of the flash memory is changed and recorded (step 182), and then the BiT / link address register is stored. Change the value (step 184). On the other hand, if it is determined in step 172 that the block is full, the block is erased (step 174), the BiT / link table is moved (step 176), and the process proceeds to the BiT / link data modification step 180.

5 shows a structure of BiT / link information, which includes an information structure 210 for a basic block, an information structure 220 for a link block, and a link state data information structure 230. The basic block information structure 210 includes a basic block address consisting of 12-bit data of bits' 0 'through' 11 ', a chip address for the basic block represented by bits' 11' and '12', and a bit ' 14 'and' 15 'dummy bits. The link block information structure 220 also includes a 12-bit link block address, a chip address for the link block, and a dummy bit. Following the link block information structure, for example, a 64-bit link state data structure 230 is constructed. The link state data structure 230 indicates which pages of the program block are linked or moved. This example is intended to represent an information structure as a long word. It is also possible to use a different bit structure. If one word represents one block information, eight pages are needed for 1G flash and 16 pages are needed for BiT / link information for 2G flash. In the present invention, the same block as the block for user data is used for storing the BiT / link information, and two blocks may be allocated for the BiT / link table in consideration of erasing of data. In this implementation, three long words are required. For the convenience of the flash memory operation control program, four long words may be used.

6 shows the information structure of the ST table, in which the upper 1k bits, i.e., 0 to 1023, are used as valid data recording information (Used) and the lower 1k bits, ie, 1024 to 2048, are invalid data recording information (Dirty). use. Here, the number of bits varies according to the capacity of the memory, and one bit represents the state of one block. For example, when the value of the valid data write bit is '1', the corresponding block is a used block in which other data is written. Indicates. If both the valid data write bit and the invalid data write bit are '0', for example, this indicates that the block is a free block. Therefore, it is not necessary to use a separate bit for indicating a free block.

Although not explicitly shown in FIGS. 5 and 6, it is preferable that information pages of the BiT / Link table and the ST table have valid information positions, and key values are included at the end of each page. The BiT / Link table and ST table need to be designed to minimize the erase, and if the number of times of use of the BiT / Link table and ST table increases without the erase operation, the BiT / link will not be known which page the valid data is written to. The information of the table and the ST table is preferably designed such that all of the pages in the block include information of the page in which the information of the block in the current flash memory is accurately described. Formerly referred to as a valid information location, this means that at the end of each page, for example, using a 32-bit key value means that in the first use the information in the BiT / Link table or ST table is empty and the value is' It will be 0 ', which can be used to prevent errors that don't find the right information.

7 and 8 illustrate the overall structure of the flash memory operation control apparatus to which the present invention can be applied, the data storage structure of the flash memory, and the operation of the flash memory.

The flash memory operation control device 310 is connected to the host system 300 through the host bus 305, and is connected to the flash memory array 320 through the flash bus 315 to exchange data. The control device 310 includes a controller 312, a flash control block 314, and an ECC block 316, wherein the controller 312 in the control device 310 includes a static random access memory (SRAM), a data buffer, and a BiT. Includes / link buffer, Memory Management Unit (MMU), and more. The memory array 320 includes a plurality of memory units 322A, 322B, ..., 322N. The flash control block 314 supplies a chip select signal CE, a control signal, and an I / O signal to the flash memory array 320, and receives a status signal R / B (Ready / Busy) from the flash memory. As I / O signals, data, address, and command signals are supplied to the flash memory with a time difference.

The flash memories 322 and 324 may have a data storage structure as shown in FIG. 8. That is, one flash memory unit includes a data block 330 of a plurality of blocks, for example, 1,024 or 2,048 memory blocks, and one memory block includes a plurality of pages 340, for example, 64 pages. . One data block 330 may consist of, for example, a 512-byte user data area and a 16-byte ECC data area. The data supplied from the flash control block 314 via the ECC 316 is serial data input, for example 512 + 16-bytes, into the I / O buffer 325 of the flash memory. Importing data from the I / O buffer 325 to the page 340 of the memory block is a write or program operation, whereas moving a data in the page to the I / O buffer is a read operation. Erasing data in a block is an erase operation. As shown in FIG. 8, a program is performed in units of pages, while an erase operation is performed in units of blocks.

Meanwhile, the data storage structure of the present invention includes a block 350 for the BiT / link table and a block 360 for the ST table, as shown in FIG. As described above, the blocks 350 and 360 may include, for example, two blocks.

9 is a block diagram illustrating an information structure of a memory block to which the present invention can be applied. This example is for flash memory above 1G.

In this embodiment, 'block 0', for example, stores information for driving the host system, and 'block 1 to block Z-5' are reserved areas for user data or other data. The block number 'Z' represents the last block located in one flash unit. 'Block Z-4, Block Z-3' is the information structure for the BiT / Link table, 'Block Z-2, Block Z-1' is for the ST table, and the final block 'Block Z' is the chip information. Information structure for recording.

10 illustrates a flow of read operations of a flash memory. A logical address is received from the host system (step 410) and the logical address is examined in a BiT / link buffer in the controller that controls flash memory operation (step 412). If there is information on the logical address in the BiT / Link buffer, the process proceeds directly to step 416 of finding the physical address based on the information. On the other hand, if there is no information on the logical address in the BiT / link buffer, the corresponding data is read from the BiT / link table in the flash memory (step 414) and the physical address is found based on the data (step 416). Data is read from the memory block corresponding to the corresponding physical address and transferred to the I / O buffer (step 418).

11 shows a flow of an operation of erasing an invalid data write block. The erase operation of the invalid data recording block is performed when the host system (eg, the card system) is in an idle state. Referring to FIG. 11, first, an invalid data recording block is searched (step 430), and the retrieved block is deleted. This erase operation (step 432) preferably proceeds until all invalid data write blocks stored in the BT buffer in the controller's memory have been erased. For example, the amount that the BT buffer in the controller's memory reads data from the BT table of the flash memory is one page, and this page may include, for example, block information of four flash memory units. Therefore, the block erase performed in step 432 proceeds until all invalid data write blocks included in the four flash units stored in this ST buffer are erased. The ST data of the erased block is changed (from 'invalid data write block' to 'free block') (step 434), and the ST buffer information in the memory is changed (step 436). In this case, it is preferable to erase the block first before changing the ST information. The reason is that if the power supply of the flash memory is cut off before the ST information is changed and the corresponding block is erased according to the changed information, the wrong ST information is later. This can be used. When the block is first erased as in the present invention, even if the ST information is not changed because the power is cut off during or immediately after the block erase operation, there is no risk of using wrong ST information later.

After changing the ST information in the memory, it is determined whether there is a host access (step 438). If there is an access, the operation terminates an invalid data write block erase operation (step 452) and operates according to the host access. It is determined (step 438). If there are remaining blocks to be erased, the flow returns to step 430, and if no blocks remain, the erase operation ends (step 452).

12 illustrates a flow of an operation of merging basic block data and link block data. The operation corresponds to, for example, a process of moving basic block data included in a path C described with reference to FIG. 3 to a link block, and is invalid. As with the operation of erasing the data write block, it is preferable to proceed when the host system is in the idle state.

The merging or moving of the data begins with a step 510 of checking whether there is a block in which the used block (e.g., primary link block) has more than three quarters of utilization, as shown in FIG. Here, setting the reference value of the utilization survey to 3/4 is only one example, and changing this value to another value is sufficiently possible within the spirit and scope of the present invention.

The original block data (ie, basic block data) is moved to the link block for the retrieved block (step 512). The BiT / link table of the basic block and the link block is changed (step 515), the ST in memory is changed (step 518), and it is determined whether there is a host access (step 520). If there is host access, the data movement operation is terminated (step 530). If there is no host access, it is determined whether a remaining block exists (step 522). If there is no remaining block, the operation ends (step 530). If there is a remaining block, the operation returns to the data usage investigation step 510 and repeats the above process to move the data.

Although specific embodiments of the present invention have been described above with reference to the drawings, this is for the purpose of illustrating the invention and is not intended to limit the protection scope of the invention. Those skilled in the art to which the present invention pertains can easily understand that various embodiments can be modified and modified without departing from the spirit or scope of the present invention. The protection scope of the invention as defined by the following claims is intended to cover all such modifications and variations.

According to the present invention, the operation speed of the flash memory can be greatly improved, and the data movement between the other block and the write block can be controlled most efficiently according to the use amount of the block to write data.

In addition, according to the present invention, it is possible to efficiently write a program for controlling the flash memory, and according to the program, it is possible to speed up the operation speed of the flash memory and extend its service life. In the present invention, the erasing operation or the inter-block data movement of the invalid data recording block is performed when the host system is in the idle state, so that the operation can be performed in the most efficient state when the actual flash memory is operating.

Claims (20)

As a method of controlling the flash memory, Receiving a logical address from a host system, Converting the received logical address into a physical address; Writing data received from a host system to a storage location of a flash memory designated by the physical address, In the recording step, when the storage location of the designated flash memory is linked, the linked storage location is already recorded as valid data, and the utilization of the linked storage location is greater than a reference value, the validity of the designated storage location is valid. Moving data to the linked storage location, and if validity of the linked storage location is less than a reference value, moving valid data of the linked storage location to another linked storage location. Motion control method. The method of claim 1, further comprising: changing the BiT / link table and the ST table for the designated storage location and the linked storage location after moving valid data when the linked storage location has a greater than a reference value. Flash memory operation method characterized in that the progress. 3. The method of claim 2, wherein the BiT / link table and the ST table are each composed of two memory blocks. 2. The BiT / Link table of claim 1, wherein after moving valid data when the utilization of the linked storage location is less than a reference value, the BiT / link table of the designated storage location and the linked storage location and the another linked storage location And changing the ST table. The method of claim 1, wherein the address translation step includes: examining a logical address in the BiT / link buffer; finding a physical address based on the logical address if the BiT / link buffer exists; And reading data from a BiT / Link table if a logical address does not exist. The storage location of claim 1, wherein when the storage location of the designated flash memory is not linked, the storage location where data can be recorded is found, the data is recorded in the storage location found, and the ST table and BiT / And modifying the link table. The storage location of claim 1, wherein when the storage location of the designated flash memory is linked and the linked storage location is a storage location capable of recording data, data is written to the linked storage location, and the BiT of the linked storage location is set. And / or changing the link table. The method of claim 1, wherein the reference value is set to minimize the time taken to move data between storage locations. 2. The method of claim 1, wherein the BiT / link table includes data representing information about each storage location of the flash memory and whether the storage location is linked or whether a current program operation can be performed. . 2. The method of claim 1, wherein the ST table includes data indicating whether each storage location of the flash memory is available or has already been used. 11. The method of claim 10, further comprising: retrieving a storage location in which invalid data is recorded among storage locations indicating that the ST table has already been used; erasing the retrieved invalid data recording storage location; And altering the table. The method of claim 1, wherein the moving of the valid data of the designated storage location to the linked storage location comprises: examining data usage of the linked storage location and determining whether the data exceeds a predetermined criterion. Is a step of moving data when is greater than a predetermined criterion. A method of transferring data between a host system and flash memory and controlling the operation of flash memory, The flash memory includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of pages / sectors, and an operation of writing data to the flash memory in the host system is performed in units of sectors and erases the flash memory. Operation is performed in units of the blocks, and the plurality of memory blocks includes a basic block designated by a physical address corresponding to a logical address transmitted from a host system, a primary link block to which the basic block is linked, and the primary block. The link block includes a secondary link block to which it is linked, The method, Writing data received from a host system to the flash memory; If the utilization of the primary link block is greater than the reference value, the valid data of the primary block is moved to the primary link block. If the utilization of the primary link block is less than the reference value, the valid data of the primary link block is moved. Moving to a secondary link block. The method of claim 13, wherein after the valid data is moved when the utilization degree of the primary link block is less than a reference value, the BiT / link table and the ST table of the basic block, the primary link block, and the secondary link block are changed. And if the utilization of the primary link block is greater than a reference value, after valid data is moved, the step of changing the BiT / link table and the ST table of the basic block and the primary link block is performed. Flash memory operation control method characterized in that the. A flash memory operation control device which transfers data between a host system and flash memory and controls the operation of the flash memory. The flash memory includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of pages / sectors, and an operation of writing data to the flash memory in the host system is performed in units of sectors and erases the flash memory. Operation is performed in units of the blocks, and the plurality of memory blocks includes a basic block designated by a physical address corresponding to a logical address transmitted from a host system, a primary link block to which the basic block is linked, and the primary block. A link block comprising a secondary link block to which the link is linked, wherein the apparatus comprises: Means for writing data received from a host system to the flash memory; If the utilization of the primary link block is greater than the reference value, the valid data of the primary block is moved to the primary link block. If the utilization of the primary link block is less than the reference value, the valid data of the primary link block is moved. And a means for moving to a secondary link block. 16. The apparatus of claim 15, wherein after the valid data is moved when the utilization degree of the primary link block is lower than a reference value, the BiT / link table and the ST table of the basic block, the primary link block, and the secondary link block are changed. And after the valid data is moved when the utilization degree of the primary link block is greater than a reference value, the BiT / link table and the ST table of the basic block and the primary link block are changed. controller. 17. The apparatus of claim 16, wherein the BiT / link table includes a base block address, a chip address for a base block, a link block address, a chip address for a link block, and data representing a link state. . 17. The apparatus of claim 16, wherein the ST table includes data representing valid data record information and invalid data record information. 19. The apparatus of claim 17 or 18, wherein the BiT / link table and the ST table are each composed of two memory blocks. 16. The apparatus of claim 15, wherein the data movement means operates when the host system is in the dormant state.