KR20030007425A - Processor having replay architecture with fast and slow replay paths - Google Patents

Abstract

According to one aspect of the present invention, a microprocessor is provided that includes an execution core, a first replay mechanism, and a second replay mechanism. The execution core performs data inference upon executing the first instruction. The first replay mechanism is used to replay the first instruction through the first replay path when a first type of error is detected that indicates an error in data inference. The second replay mechanism is used to replay the first instruction over the second replay path when a second type of error is detected that indicates an error in data inference.

Description

PROCESSOR HAVING REPLAY ARCHITECTURE WITH FAST AND SLOW REPLAY PATHS

1 shows a block diagram of one embodiment of a processor 100 disclosed in US Pat. No. 5,966,544. The processor 100 illustrated in FIG. 1 includes an I / O ring 111 that operates at a first clock frequency (I / O clock) and a latency tolerance that operates at a second clock frequency (eg, a slow clock). tolerant execution core 121, a latency-intolerant execution sub-core 131 operating at a third clock frequency (e.g., a medium speed clock), and a fourth clock frequency (e.g., a high speed clock). Latency-critical execution sub-core 141. The processor 100 shown in FIG. 1 is also a clock multiplication and / or division unit 110, 120 configured to provide adequate clocking to various portions of the processor 100, ie, sub-cores, as taught in the prior application. , 130). A particular part of the teaching of the prior application, which is most relevant to the present application, is that the execution core may include two or more parts (sub cores) operating at different clock values.

In operation, I / O ring 111 communicates with the rest of the computer system (not shown) by performing various I / O operations such as memory reads and writes at the I / O clock frequency. For example, the processor 100 may read data from an external memory device by performing an I / O operation on the I / O ring 111 at an I / O clock frequency. The various execution subcores 121, 131, 141 may perform various functions or operations on input instructions and / or input data at their respective clock frequencies. For example, the latency tolerant execution subcore 121 may perform an execution operation on the input data to generate a first result. The latency intact sub core 131 may perform an execution operation on the first result to generate a second result. Similarly, the latency critical execution subcore 141 may perform another execution operation on the second result to generate a third result. Various operations performed by various execution subcores may include computational operations, logical operations, and other operations. Those skilled in the art know and understand that the order in which the various operations are performed is not necessarily in accordance with the hierarchical order of the various execution subcores. For example, the input data immediately goes directly to the innermost subcore and the result obtained therefrom can go from the innermost subcore to another subcore or to the I / O ring 111 for write-back. Return to In addition, as disclosed and taught in the prior application, the on-chip cache structure may be staggered from two or more portions of the processor 100. As such, certain operations and / or functions may be performed at one clock frequency for one aspect of the data stored in the on-chip cache, and other operations and / or functions may be different for other aspects of the data stored in the on-chip cache. It may be performed at a clock frequency. For example, a way predictor miss for an on-chip cache may be performed at one clock frequency in one sub-core, and TLB hit / miss detection and / or page fault detection may be performed at another frequency in another sub-core. Can be performed. As such, certain errors and conditions in the executing process may be detected earlier than other errors and conditions.

2 shows a block diagram of one embodiment of a processor 200 disclosed in a prior application that includes a generalized replay structure that facilitates data inference operations. In this embodiment, processor 200 includes a scheduler 231 coupled to multiplex 241 that provides instructions received from instruction cache (I-cache) 231 to execution core 251 for execution. do. Execution core 251 may perform data inference in executing various instructions received from multiplexer 241. The processor 200 shown in FIG. 2 includes a checker unit 281 that sends a copy of the executed instruction back to the execution core 251 for redo when it is determined that there is an error in data inference. However, in this generalized replay structure, the checker unit 281 is located after the execution core 251, the TLB and tag logic 261, and the cache hit / miss logic 271. Some instructions may have been found to have been executed incorrectly (because there was an error in data inference) even before this checker unit detected. In particular, there are cases where certain errors and conditions may be detected that indicate that there is an error in data inference before the TLB / TAG logic 261 and the hit / miss logic 271 are executed. Unfortunately, because of the current position of the checker unit 281, instructions that were incorrectly executed due to errors in data inference will not be sent back to the execution core 251 for redo, ie, replay, until the checker unit 281 is reached. will be. Thus, there is an unnecessary delay from when a command is known to have been executed incorrectly due to a data inference error, until the command is actually resent for reexecution. Thus, system performance is not optimized as much as it could have been if the instructions that had been executed incorrectly had been rerun, i.e., replayed early in processing.

TECHNICAL FIELD The present invention generally relates to the field of processors, and more particularly to a replay architecture having fast and slow replay paths that facilitate data-speculating operations.

Cross Citation of Related Application

This application is part of US 09 / 222,805, filed December 30, 1998, filed December 23, 1996, and is part of US patent application Ser. No. 08 / 746,547, filed November 23, 1996, now patented US 5,966,544. to be. This application and the above applications are both assigned to Intel Corporation of Santa Clara City, California.

The features and advantages of the present invention will be better understood with reference to the accompanying drawings.

1 is a block diagram of one embodiment of a processor including various subcores operating at different frequencies.

2 is a block diagram of one embodiment of a processor having a generalized replay structure.

3 is a flow diagram of one embodiment of a processor pipeline in which the teachings of the present invention are implemented.

4 is a block diagram of one embodiment of a processor having first and second replay mechanisms.

5 is a detailed block diagram of one embodiment of a processor having first and second replay mechanisms.

6 is a flow diagram of one embodiment of a method in accordance with the teachings of the present invention.

According to one aspect of the present invention, a microprocessor is provided that includes an execution core, a first replay mechanism, and a second replay mechanism. The execution core performs data inference upon executing the first instruction. The first replay mechanism is used to replay the first instruction through the first replay path when a first type of error is detected that indicates an error in data inference. The second replay mechanism is used to replay the first instruction over the second replay path when a second type of error is detected that indicates an error in data inference.

In the following detailed description of the embodiments, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details.

In the following description, the teachings of the present invention are used to implement methods, apparatus, and systems that facilitate data inference when executing inputted instructions. In order to shorten the execution time, the execution unit performs data inference when executing the input command. If there is an error in data inference, the input instruction is redone by the execution unit until the correct result is obtained. In one embodiment, if an error of the first or second type is detected, it is determined that there is an error in data inference. An error of the first kind may be detected earlier than an error of the second kind. In one embodiment, the first checker is responsible for redoing, ie, sending the first copy of the entered instruction back to the execution unit for replay when a first type of error is detected for the execution of the entered instruction. The second checker is responsible for redoing, ie, sending a second copy of the entered instruction back to the execution unit for replay if a second type of error is detected for the execution of the entered instruction. In one embodiment, the selector is used to provide the execution unit for execution with the next input instruction, either a first copy of an incorrectly executed instruction or a second copy of an incorrectly executed instruction, according to a predetermined priority list. The teachings of the present invention can be applied to processors or machines that perform data inference upon instruction execution. However, the present invention is not limited to processors or machines that perform data inference, but can also be applied to processors and machines that require many levels of replay mechanism.

3 is a block diagram of one embodiment of a processor pipeline 300 in which the present invention may be implemented. As used herein, the term "processor" refers to a device capable of executing a series of instructions, and includes, but is not limited to, a general purpose microprocessor, special purpose microprocessor, graphics controller, audio processor, video processor, multimedia controller, and microcontroller. . Processor pipeline 300 includes several processing stages starting from fetch stage 310. In the fetch stage, instructions are retrieved and supplied to the pipeline 300. For example, microinstructions may be retrieved from cache memory embedded in or closely associated with the processor, or from external memory via a system bus. The instructions retrieved from the fetch stage 310 are then input to the decode stage 320, where the instructions or microinstructions are referred to as microinstructions or microoperations (herein referred to as UOP or uop) for execution by the processor. Decoded. In the allocating stage 330, processor resources required for execution of the microinstruction are allocated. The next stage in the pipeline is the rename stage 340, where external register references are converted to internal register references to remove false dependencies due to register reuse. In the schedule / dispatch stage 350, each microcommand or UOP is scheduled and dispatched to the execution stage 360. The microinstruction or UOP is then executed at execution stage 60. After execution, the microinstruction is retrieved from the retrieval stage 370.

In one embodiment, the various tiers described above may be organized in three stages. The first stage may be referred to as an in-order front end including a fetch stage 310, a decode stage 320, an allocation stage 330, and a renamed stage 340. During the alignment front end phase, instructions proceed through pipeline 300 according to their original program sequence. The second step may be referred to as an out-of-order execution step including the schedule / dispatch stage 350 and the execution stage 360. During this phase, each instruction is scheduled, dispatched, and executed as soon as its data dependency is resolved and the appropriate execution unit is available, regardless of its sequential position in the original program. The third step refers to an alignment recovery step comprising a recovery stage 370 that retrieves instructions according to their original sequential program order to preserve the integrity and semantics of the program.

In a processor having a replay structure, there are things that can be freely done in the scheduling and execution of input instructions. For example, the input UOP may be dispatched to an execution unit and executed, although its source data may not be ready or unknown. If it is determined that there is an error in data inference in the execution of the input UOP, each UOP can be sent back to the execution unit and replayed (replayed) until the correct result is obtained. Of course, it is desirable to limit the amount of replay, i.e., replay, because the replayed UOP can use available resources and degrade the total system performance. Nevertheless, performing such replays (replays) can benefit from total performance. For example, if most UOPs run correctly in a small number of cycles and only a very small number of UOPs need to be replayed, the lowest common-denominator should wait all UOPs as far as the worst can happen. The total efficiency will be improved.

As taught in the prior application, the on-chip data cache (also called level zero, or L0 data cache) is partitioned such that its data storage array is in a higher clock domain than the logic that provides a hit / miss decision for that array. Can be. TLB and tag logic can also be present in a slower clock domain than data storage arrays. TLB and tag logic are not required but may be present in the same clock domain as the hit / miss logic.

One of the cases where the total performance gain can be obtained is when the execution of the UOP relies on or uses the data from the LO data cache. Rather than having all UOPs wait until their source data is considered valid, it is speculated that their source data exists in the L0 data cache, but it is not clear if it is reasonably dispatching some UOPs early in the process. Better In most cases the LO data cache will be hit and valid data will be used as the source. Only in a few cases will there be errors in data inference and the UOP will be replayed. As such, most UOPs run correctly in a small number of cycles, thus improving overall performance.

4 is a block diagram of one embodiment of a processor 400 having a first (also known as fast or early) and a second (also known as slow or later) replay path to facilitate data inference upon instruction execution. As shown in FIG. 4, the processor 400 is coupled to an instruction cache (not shown) and received from the instruction cache via the selector (eg, multiplexer) 421 to the execution core 431 for execution. A scheduler / dispatcher 411 that schedules and dispatches instructions. In one embodiment, execution core 431 performs data inference upon execution of the input instruction. As described above, the input command can be dispatched and executed even if its source data is not ready or unknown. For example, the execution of the entered instruction may require source data that may or may not exist in the LO data cache. However, as described above, the total performance can be obtained by inferring that the source data required for the execution of the input instruction exists in the LO data cache. The processor 400 further includes a first replay mechanism 441 for replaying input instructions when a first type of error is detected that indicates an error in data inference. In one embodiment, the first kind of error may be detected within the first period. Processor 400 also includes a second replay mechanism 451 that replays input instructions when a second type of error is detected that indicates an error in data inference. In one embodiment, the second type of error may be detected within a second period longer than the first period. As such, if an error of the first kind has already been detected, the present invention will allow the instruction to be replayed much faster than it could have been replayed if it had to wait until an error of the second kind was detected. To be able. As shown in FIG. 4, if a first type of error indicating an error in data inference is detected and it is determined that execution of an input instruction is performed incorrectly, the first replay mechanism (fast or early checker) 441 is determined. Each instruction will be resent to the execution core 431 via the multiplexer 421 for replay (replay). Similarly, if a second type of error is detected indicating that there is an error in data inference or that another error condition exists and the execution of the input instruction is determined to be incorrect, then the second replay mechanism (slow or later checker) 441 is determined. Each instruction will be retransmitted to the execution core 431 via the multiplexer 421 for replay (replay). The functions and operations of the first and second replay mechanisms shown in FIG. 4 are described in more detail below.

FIG. 5 is a detailed block diagram of one embodiment of a processor 500 having first and second replay paths described above with respect to FIG. 4. As shown in FIG. 5, the processor 500 includes a scheduler 511 for scheduling and dispatching instructions received from the instruction cache (not shown) to the execution core 531 for execution via the multiplexer 521. . The function and operation of the multiplexer 521 will be described in detail below. In one embodiment execution core 531 performs data inference upon execution of input instructions received from multiplexer 521. The processor 500 further includes a first delay unit 541 that makes a first copy of the input instruction and holds the first copy for at least one clock cycle in the first clock domain. The processor 500 also includes a first checker 545 coupled to the first delay unit 541 and the execution core 531. In one embodiment, the first checker 545 determines whether there is an error in data inference with respect to the first set of error types, and if it is determined that the error is present, the first checker 547 to re-execute the first copy of the input instruction. Is retransmitted to the execution core. As shown in FIG. 5, in one embodiment the processor 500 is coupled to the first delay unit to make a second copy of the input instruction and retain the second copy for at least one clock cycle in the second clock domain. A second delay unit 551 is further included. The processor 500 includes a second delay unit 551 and a second checker 555 coupled to the first checker 545. In one embodiment, the second checker determines whether there is an error in the instruction execution for the second set of error types, and if it is determined that the error is found, through the second buffer 557 for re-executing the second copy of the input instruction. Configured to retransmit to execution core 531. As illustrated in FIG. 5, the multiplexer 521 may include a scheduler 511, an execution core 531, a first delay unit 541, a first checker 545, a second checker 555, and a first buffer ( 547, and a second buffer 557. In one embodiment, the multiplexer 521 is configured to receive an input instruction and its subsequent instructions from the instruction cache, a first copy of the input instruction from the first checker, and a second copy of the input instruction from the second checker. do. In one embodiment the multiplexer 521 is further configured to selectively provide to the execution core 531 any one of a subsequent instruction, a first copy of an input instruction, or a second copy of an input instruction in accordance with a predetermined priority list. . In one embodiment, a first execution priority is given to a second copy of the input instruction, a second execution priority is given to the first copy of the input instruction, and a third execution priority is given to subsequent instructions. In one embodiment, the first execution priority is higher than the second execution priority, and the second execution priority is higher than the third execution priority. In one embodiment, the first set of error types is a subset of the second set of error types. In another embodiment, the first set of error types is complimentary to the second set of error types. In one embodiment, the first set of error types indicates an error indicating that the level zero cache path predictor is missed, an error indicating that the level zero cache CAM extension is mismatched, and that store forwarding buffer data is unknown. Contains the error to display. In one embodiment, the second set of error types includes an error indicating a TLB miss, an error indicating a page fault, or other error indicating that the instruction was executed incorrectly and that each instruction needed to be replayed. . In one embodiment, the first delay unit 541 is configured to provide a first copy of the input command to the first checker 545 after a predetermined number of clock cycles in the first clock domain. In one embodiment, the predetermined number of clock cycles in the first clock domain corresponds approximately to the time delay of the input command through the execution core.

There are cases where other units in the processor 500 may generate their own instructions to perform the corresponding functions. For example, a memory control unit or memory execution unit (not shown) within processor 500 dispatches instructions for execution within its own pipeline, including UOP or full store operations to handle page splitting and TLB reloading, and the like. There is often a need to do it. This kind of instruction is called a generation instruction because it is generated or produced by any unit in the processor 500 and is not in the instruction flow from the instruction cache. In one embodiment multiplexer 521 is also coupled to receive the generation instruction and send it to execution core 531 for execution. Since the multiplexer 521 can receive instructions from multiple paths at the same time, a certain priority list is needed to determine the execution priority between instructions sent from the multiple paths to the multiplexer 521. For example, the multiplexer receives subsequent instructions from scheduler 511, first copy of input instructions to be replayed from first checker 545, and another to be replayed from second checker 555 in the same processing period or clock cycle. Input instructions and generation instructions from other units (eg, memory control or execution units) may be received. In one embodiment, the multiplexer 521 has a low priority for instructions coming from the instruction cache, a medium priority for replay instructions coming from the first checker, a high priority for replay instructions coming from the second checker, and a generation instruction. Give the highest priority.

As described above, in one embodiment the error condition detected by the first checker 545 may be a subset of the error condition detected by the second checker 555. In this case, the second checker 555 needs to provide reliable checking because the UOP cannot be replayed once the UOP is taken by the second checker. In other embodiments, the error condition handled by the first checker 545 may take precedence over the error condition handled by the second checker 555. In this case, the first checker 545 needs to provide a reliable check rather than the "high but not guaranteed" checking described above for the error set, because the latter checker outputs the early checker. Because do not check again. Thus, subset mode is preferred.

As discussed above, the second checker 555 may provide additional and / or preferential checking for errors not handled by the first checker 545. Which error is handled by which checker depends on several factors, including but not limited to processor performance, design complexity, die area, and so forth. In one embodiment, the second checker 555 is responsible for replaying instructions due to TLB misses and various problems that may occur, for example, in a memory control unit (not shown) of the processor 500. These various problems may include problems or error conditions that are difficult to detect within a short time, such as cache misses following full physical address checks, and incorrect transmissions from storage following full physical address checks.

In one embodiment, the first checker 545 and the second checker 555 cooperate with each other to control the operation of the multiplexer 521. As shown in FIG. 5, the multiplexer 521 generates a selection signal received from the first checker 545 and the second checker 555 and optionally a generation instruction that is not in the instruction flow from the instruction cache. It performs its corresponding function in accordance with another selection signal received from another unit such as a memory control unit (not shown). These selection signals are used by the multiplexer 521 to determine which instructions to send to the execution core 531 for execution in a given processing cycle when one or more instructions from several paths are waiting to be executed. . In one embodiment, the generation instruction has a first execution priority, the instruction coming from the second checker 555 has a second priority lower than the first priority, and the instruction coming from the first checker has a second priority lower than the second priority. A third priority, and subsequent instructions coming from the instruction cache via the scheduler 511, are given a fourth priority that is lower than the third priority.

In one embodiment, once a particular UOP has been sent for fast replay by the first checker 545, the same instantiation of that UOP will result in a slower replay by the second checker 555 because a copy already exists. May not be sent. To prevent this from happening, in one embodiment each UOP may include some special fields that can be used by these checkers to coordinate the replay activity between the first checkers 545 and the second checkers 555. . For example, in one embodiment the UOP may include a field called the NEEDS_FAST_REPLAY field, which is set by the first checker 545 that the first checker 545 wants to send the UOP for fast replay. It is displayed. Each UOP may also include another field called the GOT_FAST_REPLAY field. In one embodiment, the GOT_FAST_REPLAY field is transmitted by mutual cooperation between the first checker 545 and the second checker 555. For example, assume that the first checker wants to send a first instruction for fast replay because a first kind of error was detected. In this case, the first checker 545 sets the corresponding NEEDS_FAST_REPLAY field of each UOP to indicate that this specific UOP needs to be replayed in the fast replay path. If the second checker 555 wants to send a second UOP for slow replays in the same clock cycle, the GOT_FAST_REPLAY field of the first instruction is cleared and the multiplexer 521 is responsible for slow replay UOPs instead of seeking fast replays. Will be controlled to select. Later, when the first UOP reaches the second checker 555, it will be sent for replay in the slow replay path since its corresponding NEEDS_FAST_REPLAY field is already set.

6 shows a flow diagram of one embodiment of a method 600 using fast and slow paths to facilitate data inference tasks. The method 600 begins at block 601 and proceeds to block 605. In block 605 the execution core or unit performs data inference upon executing the input instruction. The method 600 then proceeds from block 605 to block 609. In block 609, it is determined whether a first type of error has been detected. As described above, in one embodiment a first type of error occurs when the LO data cache path predictor is missed, in which case the data cannot exist in the L0 data cache, and the L0 data cache CAM extension is mismatched. (I.e., the path predictor is hit but the tags do not match), or the store transfer buffer data is unknown (i.e. the data is assumed to be transferred from the store transfer buffer but store data is not available). In block 613 the input instruction is re-executed if an error of the first kind is detected. As discussed above, if an error of the first kind is detected, the first checker unit (ie, fast or early checker) will send a copy of the input instruction to replay, i.e., redo, on the fast replay path. The method 600 then proceeds to block 617. In block 617, it is determined whether a second type of error has been detected. In this embodiment the second checker (i.e. low speed or later checker) is responsible for determining whether a second type of error has occurred. In block 621, the input instruction is re-executed if a second kind of error has occurred. As mentioned above, the second checker is responsible for sending a copy of the input instruction for replay on the slow replay path when a second type of error occurs.

The present invention has been described so far in connection with a preferred embodiment. It will be apparent to those skilled in the art that many choices, variations, modifications, and uses are possible in light of the above teachings.

Claims (19)

An execution core that performs data speculation when executing the first instruction; A first replay mechanism for replaying the first instruction through a first replay path when a first type of error is detected indicating an error in the data inference; And A second replay mechanism for replaying the first instruction through a second replay path when a second type of error is detected that indicates an error in the data inference Microprocessor comprising a. The microprocessor of claim 1, wherein the first type of error can be detected within a first period and the second type error can be detected within a second period longer than the first period. The method of claim 1, wherein the first replay mechanism A first delay unit for making a first copy of the first instruction and holding the first copy for at least one clock cycle in a first clock domain; And A first checker that determines whether the first type of error is detected and sends back to the execution core to replay the first copy of the first instruction when the first type of error is detected (checker) Microprocessor comprising a. The method of claim 3, wherein the second replay mechanism A second delay unit that makes a second copy of the first instruction and holds the second copy for at least one clock cycle in a second clock domain; And A second checker that determines whether the second type of error is detected and sends back to the execution core to replay the second copy of the first instruction when the second type of error is detected Microprocessor comprising a. 5. The microprocessor of claim 4, further comprising an instruction cache for the microprocessor to store the first and subsequent instructions and to provide these instructions to the execution core. The method of claim 5, wherein the microprocessor And a selector coupled to receive a subsequent instruction from the instruction cache, a first copy of the first instruction from the first checker, and another instruction from the second checker, The selector may be any one of the subsequent instructions from the instruction cache, the first copy of the first instructions from the first checker, and the other instructions from the second checker according to a predetermined priority scheme. A microprocessor provided to the execution core for executing an instruction. 7. The microprocessor of claim 6, wherein said selector comprises a multiplexer. 7. The method of claim 6, wherein the other instruction is given a first execution priority, the first copy of the first instruction is given a second execution priority that is lower than the first execution priority, and the subsequent instruction is assigned the first execution priority. 2 A microprocessor given a third execution priority lower than the execution priority. 2. The microprocessor of claim 1, wherein the error of the first kind is a subset of the error of the second kind. 2. The microprocessor of claim 1, wherein the first type of error is complimentary to the second type of error. The method of claim 1, wherein the first type of error is an error indicating that the level zero cache path predictor is missed, an error indicating that the level zero cache CAM extension is mismatched, and a store forwarding buffer. ) A microprocessor selected from the group consisting of errors indicating that the data is unknown. 2. The microprocessor of claim 1, wherein the second type of error is selected from the group consisting of an error indicating a TLB miss and an error indicating an incorrect stored transfer according to a full physical address check. 4. The method of claim 3, wherein the first delay unit provides a first copy of the first instruction after a predetermined number of clock cycles in the first clock domain, wherein the predetermined number of clock cycles in the first clock domain Approximately a time delay in which the first instruction passes through the execution core. 7. The microprocessor of claim 6, further comprising means for generating instructions that the microprocessor is not in the instruction flow from the instruction cache. 15. The microprocessor of claim 14, wherein the selector is coupled to receive the generated instruction and send it to the execution core for execution. 16. The apparatus of claim 15, wherein the selector is low priority for instructions coming from the instruction cache, medium priority for replay instructions coming from the first checker, high priority for replay instructions coming from the second checker, and Microprocessor giving highest priority to generated instructions. Performing data inference upon execution of the first instruction in the execution core; Re-executing the first instruction over a first replay path in response to a first type of error indicating that there is an error in the data inference; And Re-executing the first instruction over a second replay path in response to a second type of error indicating that there is an error in the data inference How to include. Means for performing data inference upon execution of the first instruction; Means for re-executing the first instruction over a first replay path in response to a first type of error indicative of an error in the data inference; And Means for re-executing the first instruction over a second replay path in response to a second type of error indicative of an error in the data inference Microprocessor comprising a. An instruction cache that stores the first instruction and provides for execution; A scheduler coupled to the instruction cache, the scheduler scheduling the first instruction received from the instruction cache to dispatch for execution; An execution core coupled to executing the first instruction dispatched from the scheduler, the execution core performing data inference upon execution of the first instruction; A first replay mechanism for retransmitting a first copy of the first instruction to the execution core for redo when a first error is detected indicating an error in the data inference; And A second replay mechanism for retransmitting a second copy of the first instruction to the execution core for redo when a second error is detected indicating an error in the data inference Processing system comprising a.