KR20030005778A - Gate insulator of MOS transistor and method for fabricating the same - Google Patents
Gate insulator of MOS transistor and method for fabricating the same Download PDFInfo
- Publication number
- KR20030005778A KR20030005778A KR1020010041230A KR20010041230A KR20030005778A KR 20030005778 A KR20030005778 A KR 20030005778A KR 1020010041230 A KR1020010041230 A KR 1020010041230A KR 20010041230 A KR20010041230 A KR 20010041230A KR 20030005778 A KR20030005778 A KR 20030005778A
- Authority
- KR
- South Korea
- Prior art keywords
- gate insulating
- mos transistor
- film
- insulating film
- heat treatment
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000012212 insulator Substances 0.000 title 1
- 229910000449 hafnium oxide Inorganic materials 0.000 claims abstract description 20
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000012298 atmosphere Substances 0.000 claims abstract description 13
- 238000004544 sputter deposition Methods 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 229910052692 Dysprosium Inorganic materials 0.000 claims description 8
- 229910052735 hafnium Inorganic materials 0.000 claims description 5
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005546 reactive sputtering Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 abstract description 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 50
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- 238000012512 characterization method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910052771 Terbium Inorganic materials 0.000 description 1
- 238000000560 X-ray reflectometry Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910052747 lanthanoid Inorganic materials 0.000 description 1
- 150000002602 lanthanoids Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
Abstract
Description
본 발명은 MOS 트랜지스터 게이트 절연막 및 그 제조방법에 관한 것으로서, 특히 차세대 게이트 절연막에 적합한 새로운 재질의 MOS 트랜지스터 게이트 절연막및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor gate insulating film and a method of manufacturing the same, and more particularly, to a MOS transistor gate insulating film of a new material suitable for a next generation gate insulating film and a method of manufacturing the same.
최근 차세대 게이트 절연막으로 고유전 박막이 많이 연구되고 있다. 그러나, 100nm급 MOS 소자에의 적용을 고려할 때 요구되는 1nm급의 유효두께와 낮은 누설전류 특성을 만족시킬 수 있는 절연막 형성 공정은 아직 확보되어 있지 않다.Recently, high-k dielectric thin films have been studied as next-generation gate insulating films. However, considering the application to the 100nm class MOS device, an insulating film forming process capable of satisfying the effective thickness of 1 nm class and low leakage current characteristics is not yet secured.
고유전 박막의 누설전류를 줄이기 위한 시도로 도핑(doping)을 이용하려는 시도가 있다. 최근 발표된 벨 연구소(Bell Lab.)의 논문에 따르면 TiO2에 란타나이드(lanthanide) 계의 Nd, Tb, Dy를 적정량 도핑함으로써 누설전류를 개선할 수 있다고 한다(참고: Applied physics letter, vol. 74, No. 20, p.3041, 1999). 그러나, TiO2는 열안정성 및 실리콘 계면과의 반응성 등으로 인해 게이트 절연막으로 응용하기에는 여전히 어려운 점이 있다.Attempts have been made to use doping in an attempt to reduce leakage current of high dielectric thin films. According to a recent paper published by Bell Lab., Leakage currents can be improved by doping TiO 2 with appropriate amounts of lanthanide Nd, Tb and Dy (see Applied physics letter, vol. 74, No. 20, p. 3041, 1999). However, TiO 2 is still difficult to be applied as a gate insulating film due to thermal stability and reactivity with a silicon interface.
따라서, 본 발명이 이루고자 하는 기술적 과제는, 차세대 게이트 절연막에 적합한 새로운 재질의 MOS 트랜지스터 게이트 절연막을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a MOS transistor gate insulating film of a new material suitable for the next generation gate insulating film.
본 발명이 이루고자 하는 다른 기술적 과제는, 상기 기술적 과제를 달성하는 데 적합한 게이트 절연막 제조방법을 제공하는 데 있다.Another object of the present invention is to provide a method of manufacturing a gate insulating film suitable for achieving the above technical problem.
도 1a 내지 도 1c는 본 발명에 따른 MOS 트랜지스터 게이트 절연막 및 그 제조방법을 설명하기 위한 단면도들;1A to 1C are cross-sectional views illustrating a MOS transistor gate insulating film and a method of manufacturing the same according to the present invention;
도 2a 내지 도 2d는 하프늄 산화막에 Dy가 도핑된 경우와 도핑되지 않은 경우에 대한 특성분석 결과이다.2A to 2D show results of characterization of a case in which a hafnium oxide layer is doped with Dy and an undoped case.
< 도면의 주요 부분에 대한 참조번호의 설명 ><Description of Reference Numbers for Main Parts of Drawings>
110: 실리콘 기판 120: 질화막110: silicon substrate 120: nitride film
130: 금속막 130a: Dy 도핑된 하프늄 산화막130 metal film 130a: Dy-doped hafnium oxide film
상기 기술적 과제를 달성하기 위한 본 발명에 따른 MOS 트랜지스터 게이트절연막은, 하프늄 산화막에 Dy가 도핑되어 이루어지는 것을 특징으로 한다.The MOS transistor gate insulating film according to the present invention for achieving the above technical problem is characterized in that the hafnium oxide film is Dy doped.
여기서, 상기 Dy의 도핑량은 1 내지 20 원자% 인 것이 바람직하며, 상기 Dy 도핑된 하프늄 산화막은 원자증착법, 화학기상증착법, 및 반응성 스퍼터링법에 의하여 형성될 수 있다.Here, the doping amount of Dy is preferably 1 to 20 atomic%, and the Dy-doped hafnium oxide film may be formed by atomic deposition, chemical vapor deposition, and reactive sputtering.
상기 다른 기술적 과제를 달성하기 위한 본 발명에 따른 MOS 트랜지스터 게이트 절연막 제조방법은, 실리콘 기판 상에 Hf와 Dy를 증착하여 금속막을 형성하는 단계; 및 상기 금속막이 형성된 결과물을 산소원소 함유 분위기에서 열처리하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a MOS transistor gate insulating film, comprising: forming a metal film by depositing Hf and Dy on a silicon substrate; And heat-treating the resultant product in which the metal film is formed in an oxygen element-containing atmosphere.
여기서, 상기 금속막은 Hf와 Dy 타겟을 각각 마련하고 이를 동시에 스퍼터링하여 형성시킬 수 있으며, 상기 스퍼터링은 10-5내지 1 Torr의 압력범위에서 행하는 것이 바람직하다. 상기 금속막은 3 내지 10 nm 의 두께를 가지는 것이 바람직하며, 또한 Dy를 1 내지 20 원자% 만큼 함유하는 것이 바람직하다.Here, the metal film may be formed by sputtering the Hf and Dy targets respectively, and the sputtering is preferably performed at a pressure range of 10 −5 to 1 Torr. The metal film preferably has a thickness of 3 to 10 nm, and preferably contains 1 to 20 atomic% of Dy.
상기 열처리는 O2분위기에서 행할 수 있는데, 이 때의 열처리는 600 내지 800℃의 온도범위와 10-3내지 760 Torr 의 압력범위에서 행하는 것이 바람직하다. 그리고, 상기 열처리는 H2O 증기 분위기에서도 행할 수 있는데, 이 때의 열처리는 300 내지 500℃의 온도범위 및 10-3내지 103Torr의 압력범위에서 행하는 것이 바람직하다.The heat treatment may be performed in an O 2 atmosphere, and the heat treatment at this time is preferably performed in a temperature range of 600 to 800 ° C. and a pressure range of 10 −3 to 760 Torr. The heat treatment may be performed even in a H 2 O vapor atmosphere. The heat treatment at this time is preferably performed in a temperature range of 300 to 500 ° C. and a pressure range of 10 −3 to 10 3 Torr.
한편, 상기 금속막을 형성하는 단계 이전에 상기 실리콘 기판 상에 질화막을형성하는 단계를 더 포함할 수 있는데, 상기 질화막은 상기 실리콘 기판을 질소함유 분위기에서 열처리하거나, 상기 실리콘 기판을 질소함유 플라즈마에 노출시켜서 형성할 수 있다.Meanwhile, before the forming of the metal film, the method may further include forming a nitride film on the silicon substrate, wherein the nitride film heat-treats the silicon substrate in a nitrogen-containing atmosphere or exposes the silicon substrate to a nitrogen-containing plasma. Can be formed.
이하에서, 본 발명의 바람직한 실시예를 첨부한 도면들을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.
도 1a 내지 도 1c는 본 발명에 따른 MOS 트랜지스터 게이트 절연막 및 그 제조방법을 설명하기 위한 단면도들이다.1A to 1C are cross-sectional views illustrating a MOS transistor gate insulating film and a method of manufacturing the same according to the present invention.
도 1a는 질화막(120)을 형성하는 단계를 설명하기 위한 단면도로서, 구체적으로, 실리콘 기판(110)을 질소함유 분위기에서 열처리하여 실리콘 기판(110) 상에 질화막(120)을 형성한다. 질화막(120)은 실리콘 기판(110)을 질소함유 플라즈마에 노출시켜서 형성시킬 수도 있다.FIG. 1A is a cross-sectional view illustrating a process of forming the nitride film 120. Specifically, the silicon substrate 110 is heat-treated in a nitrogen-containing atmosphere to form the nitride film 120 on the silicon substrate 110. The nitride film 120 may be formed by exposing the silicon substrate 110 to a plasma containing nitrogen.
도 1b는 금속막(130)을 형성하는 단계를 설명하기 위한 단면도이다. 구체적으로, Hf와 Dy 타겟을 각각 마련하고 이를 동시에 스퍼터링(co-sputtering)하여 질화막(120) 상에 3 내지 10 nm 의 두께를 갖는 금속막(130)을 형성한다. 스퍼터링은 10-5내지 1 Torr의 압력범위에서 행한다. 스퍼터링 시에 각 타겟에 인가되는 전력을 5 내지 1000 W 범위 내에서 조절하여 금속막(130) 내의 Dy 양이 1 내지 20 원자% 가 되도록 한다.1B is a cross-sectional view for describing a step of forming the metal film 130. Specifically, Hf and Dy targets are respectively provided and co-sputtered to form a metal film 130 having a thickness of 3 to 10 nm on the nitride film 120. Sputtering is carried out in a pressure range of 10 −5 to 1 Torr. The power applied to each target during sputtering is adjusted within the range of 5 to 1000 W so that the amount of Dy in the metal film 130 is 1 to 20 atomic%.
도 1c는 Dy 도핑된 하프늄 산화막(HfO2; 130a)을 형성하는 단계를 설명하기 위한 단면도이다. 구체적으로, 금속막(130)이 형성된 결과물을 O2분위기에서 열처리하여 산화시킴으로써 Dy 도핑된 하프늄 산화막(130a)을 형성한다. 따라서, 질화막(120)과 Dy 도핑된 하프늄 산화막(130a)이 순차적으로 적층된 게이트 절연막이 형성되게 된다. 열처리는 600 내지 800℃ 의 온도범위와 10-3내지 760 Torr의 압력범위에서 행한다.1C is a cross-sectional view for describing a step of forming a Dy-doped hafnium oxide film (HfO 2 ; 130a). Specifically, the Dy-doped hafnium oxide film 130a is formed by oxidizing a resultant product on which the metal film 130 is formed in an O 2 atmosphere. Accordingly, the gate insulating film in which the nitride film 120 and the Dy-doped hafnium oxide film 130a are sequentially stacked is formed. The heat treatment is carried out in a temperature range of 600 to 800 ° C. and a pressure range of 10 −3 to 760 Torr.
상기 열처리는 O2분위기 대신에 H2O 증기 분위기에서도 행할 수 있으며, 이 때의 열처리는 300 내지 500℃의 온도범위와 10-3내지 103Torr의 압력범위에서 행한다. 질화막(120)을 형성시키는 과정을 생략하여 금속막(130)을 실리콘 기판(110) 상에 바로 형성시킬 수도 있다. 이 경우에는 Dy 도핑된 하프늄 산화막(130a)만이 게이트 절연막 역할을 하게 된다.The heat treatment may be performed in an H 2 O vapor atmosphere instead of an O 2 atmosphere, and the heat treatment at this time is performed in a temperature range of 300 to 500 ° C. and a pressure range of 10 −3 to 10 3 Torr. The metal film 130 may be directly formed on the silicon substrate 110 by omitting the process of forming the nitride film 120. In this case, only the Dy-doped hafnium oxide film 130a serves as a gate insulating film.
Dy 도핑된 하프늄 산화막(130a)은 상기와 같은 방법 외에도 원자증착법(Atomic Layer Deposition method), 화학기상증착법(Chemical Vapor Deposition method), 및 반응성 스퍼터링법(Reactive Sputtering method) 등으로 형성시킬 수도 있다.In addition to the above method, the Dy-doped hafnium oxide film 130a may be formed by an atomic layer deposition method, a chemical vapor deposition method, a reactive sputtering method, or the like.
도 2a 내지 도 2d는 하프늄 산화막에 Dy가 도핑된 경우와 도핑되지 않은 경우에 대한 특성분석 결과이다.2A to 2D show results of characterization of a case in which a hafnium oxide layer is doped with Dy and an undoped case.
도 2a는 C-V 그래프이다. 도 2a를 참조하면, 하프늄 산화막에 Dy가 도핑되더라도 도핑되지 않은 경우와 비슷한 유효두께를 갖는다는 것을 알 수 있다. 도 2a 내에 삽입된 그래프는 X선 반사도(X-ray reflectivity)를 나타낸 것인데, 이 역시 Dy가 도핑된 경우와 도핑되지 않은 경우 모두 비슷한 물리적 두께를 갖는다는 것을보여준다.2A is a C-V graph. Referring to FIG. 2A, it can be seen that even though Dy is doped in the hafnium oxide film, the effective thickness is similar to that of the undoped layer. The graph inserted in FIG. 2A shows X-ray reflectivity, which also shows that both Dy and undoped have similar physical thicknesses.
도 2b는 누설전류를 측정한 결과이다. 도 2b를 참조하면, 하프늄 산화막에 Dy가 도핑되지 않았을 때에 비해 Dy가 도핑되었을 때 누설전류가 획기적으로 줄어들었음을 볼 수 있다.Figure 2b is the result of measuring the leakage current. Referring to FIG. 2B, it can be seen that the leakage current is significantly reduced when Dy is doped, compared to when Dy is not doped in the hafnium oxide film.
도 2c는 Dy 도핑 농도에 따른 AES(Auger Electron Spectroscopy) 분석결과이고, 도 2d는 Dy의 도핑 농도에 따른 하프늄 산화막의 누설전류 및 유효두께를 보여주는 그래프이다. 도 2d를 참조하면, Dy의 도핑농도가 1 내지 20 원자% 일 때에는 Dy 도핑된 하프늄 산화막의 유효두께의 급격한 증가 없이 누설전류가 우수함을 알 수 있다.FIG. 2C is a result of AES (Auger Electron Spectroscopy) analysis according to Dy doping concentration, and FIG. 2D is a graph showing leakage current and effective thickness of hafnium oxide film according to Dy doping concentration. Referring to FIG. 2D, it can be seen that when the doping concentration of Dy is 1 to 20 atomic%, the leakage current is excellent without a sharp increase in the effective thickness of the Dy-doped hafnium oxide film.
상술한 바와 같은 Dy 도핑된 하프늄 산화막을 게이트 절연막으로 사용하게 되면 차세대에 적합한 유효두께를 가질 뿐만 아니라 누설전류가 매우 적은 게이트 절연막을 얻을 수 있게 된다.When the Dy doped hafnium oxide film as described above is used as the gate insulating film, it is possible to obtain a gate insulating film having an effective thickness suitable for the next generation and having a very low leakage current.
본 발명은 상기 실시예에만 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의해 많은 변형이 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.
Claims (17)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0041230A KR100379621B1 (en) | 2001-07-10 | 2001-07-10 | Gate insulator of MOS transistor and method for fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0041230A KR100379621B1 (en) | 2001-07-10 | 2001-07-10 | Gate insulator of MOS transistor and method for fabricating the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030005778A true KR20030005778A (en) | 2003-01-23 |
| KR100379621B1 KR100379621B1 (en) | 2003-04-10 |
Family
ID=27714240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2001-0041230A KR100379621B1 (en) | 2001-07-10 | 2001-07-10 | Gate insulator of MOS transistor and method for fabricating the same |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100379621B1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1480274A2 (en) * | 2003-04-30 | 2004-11-24 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device having gate stack including oha film and method of manufacturing the same |
| KR100613098B1 (en) * | 2004-12-29 | 2006-08-16 | 동부일렉트로닉스 주식회사 | Method for fabricating the gate oxide of semiconductor device |
| KR100618815B1 (en) * | 2003-11-12 | 2006-08-31 | 삼성전자주식회사 | Semiconductor device having different gate dielectric layers and method for manufacturing the same |
| WO2011156225A3 (en) * | 2010-06-08 | 2012-04-19 | Henkel Corporation | Wafer backside coating containing reactive sulfur compound |
| US20180022858A1 (en) * | 2014-12-24 | 2018-01-25 | Kcc Corporation | Highly elastic polyester modified urethane resin and clear coat composition containing same |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5292673A (en) * | 1989-08-16 | 1994-03-08 | Hitachi, Ltd | Method of manufacturing a semiconductor device |
| US5923056A (en) * | 1996-10-10 | 1999-07-13 | Lucent Technologies Inc. | Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials |
| US6020243A (en) * | 1997-07-24 | 2000-02-01 | Texas Instruments Incorporated | Zirconium and/or hafnium silicon-oxynitride gate dielectric |
| US6727148B1 (en) * | 1998-06-30 | 2004-04-27 | Lam Research Corporation | ULSI MOS with high dielectric constant gate insulator |
| KR100363082B1 (en) * | 1999-09-21 | 2002-11-30 | 삼성전자 주식회사 | Method for forming a gate insulating film having a dualistic thickness in process of fabrication of a transistor |
| KR100545706B1 (en) * | 2000-06-28 | 2006-01-24 | 주식회사 하이닉스반도체 | Semiconductor device manufacturing method |
-
2001
- 2001-07-10 KR KR10-2001-0041230A patent/KR100379621B1/en not_active IP Right Cessation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1480274A2 (en) * | 2003-04-30 | 2004-11-24 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device having gate stack including oha film and method of manufacturing the same |
| KR100618815B1 (en) * | 2003-11-12 | 2006-08-31 | 삼성전자주식회사 | Semiconductor device having different gate dielectric layers and method for manufacturing the same |
| KR100613098B1 (en) * | 2004-12-29 | 2006-08-16 | 동부일렉트로닉스 주식회사 | Method for fabricating the gate oxide of semiconductor device |
| WO2011156225A3 (en) * | 2010-06-08 | 2012-04-19 | Henkel Corporation | Wafer backside coating containing reactive sulfur compound |
| US20180022858A1 (en) * | 2014-12-24 | 2018-01-25 | Kcc Corporation | Highly elastic polyester modified urethane resin and clear coat composition containing same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100379621B1 (en) | 2003-04-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4791332B2 (en) | Semiconductor structure including double metal gate and manufacturing method thereof (self-alignment integration of double metal gate) | |
| KR100636856B1 (en) | ULSI MOS with high dielectric constant gate insulator | |
| JP3703373B2 (en) | MOSFET and gate dielectric manufacturing method | |
| KR100204083B1 (en) | Tasin oxygen diffusion barrier in multilayer structure | |
| TW564549B (en) | Semiconductor device and the manufacturing method thereof | |
| TW536744B (en) | Method for improved plasma nitridation of ultra thin gate dielectrics | |
| US20040175961A1 (en) | Two-step post nitridation annealing for lower EOT plasma nitrided gate dielectrics | |
| US20050062136A1 (en) | Multilayer high k dielectric films and method of making the same | |
| US20090294876A1 (en) | Method for deposition of an ultra-thin electropositive metal-containing cap layer | |
| JP3746478B2 (en) | Manufacturing method of semiconductor device | |
| US20010024860A1 (en) | Method for manufacturing a gate structure incorporating therein aluminum oxide as a gate dielectric | |
| KR20040072051A (en) | Semiconductor device and method for manufacturing the same | |
| JP2005317647A (en) | Semiconductor device and its fabrication process | |
| US6767847B1 (en) | Method of forming a silicon nitride-silicon dioxide gate stack | |
| KR100379621B1 (en) | Gate insulator of MOS transistor and method for fabricating the same | |
| KR100928023B1 (en) | Semiconductor device and manufacturing method | |
| KR100359489B1 (en) | Method of fabricating gate dielectric for use in semiconductor device | |
| KR20010063463A (en) | Method of manufacturing a semiconductor device | |
| US20070034974A1 (en) | Semiconductor device and manufacturing method thereof | |
| US20050189598A1 (en) | Logic embedded-memory integrated circuits | |
| KR100373165B1 (en) | Method of manufacturing a semiconductor device utilizing a gate dielelctric | |
| KR100593131B1 (en) | Method of manufacturing a semiconductor device | |
| KR20020035982A (en) | Method for forming gate of semiconductor device | |
| KR20020049196A (en) | Method for forming metal silicate film for gate dielectric | |
| JP2003101014A (en) | Method of manufacturing semiconductor device having high dielectric constant metal oxide insulating film, and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20121211 Year of fee payment: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20131211 Year of fee payment: 12 |
|
| FPAY | Annual fee payment |
Payment date: 20141218 Year of fee payment: 13 |
|
| FPAY | Annual fee payment |
Payment date: 20161205 Year of fee payment: 14 |
|
| R401 | Registration of restoration | ||
| FPAY | Annual fee payment |
Payment date: 20170224 Year of fee payment: 15 |
|
| LAPS | Lapse due to unpaid annual fee |