KR20030003418A - Method for manufacturing capacitor - Google Patents

Method for manufacturing capacitor Download PDF

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Publication number
KR20030003418A
KR20030003418A KR1020010039157A KR20010039157A KR20030003418A KR 20030003418 A KR20030003418 A KR 20030003418A KR 1020010039157 A KR1020010039157 A KR 1020010039157A KR 20010039157 A KR20010039157 A KR 20010039157A KR 20030003418 A KR20030003418 A KR 20030003418A
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South Korea
Prior art keywords
capacitor
storage node
film
doped polysilicon
polysilicon
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KR1020010039157A
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Korean (ko)
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KR100761405B1 (en
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금동렬
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains

Abstract

PURPOSE: A method for fabricating a capacitor is provided to prevent a bridge between storage nodes by restraining the growth of HSG(Hemi-Spherical Grain) on a projection portion of the storage node. CONSTITUTION: An interlayer dielectric(22) is formed on a semiconductor substrate(21). A contact hole is formed by etching the interlayer dielectric(22). A polysilicon plug(23) is formed by depositing and etching a polysilicon layer on the interlayer dielectric(22). A capacitor oxide layer(24) is formed on the interlayer dielectric(22). A concave portion is formed by etching selectively the capacitor oxide layer(24). A lightly doped polysilicon is formed on the capacitor oxide layer(24). A photoresist layer is coated on an entire surface of the semiconductor substrate(21). A storage node is formed by performing a CMP process for the photoresist layer and the lightly doped polysilicon. Impurities are implanted into a projection portion(27a) of the remaining storage node. The photoresist layer is removed. An HSG(28) is grown on a surface of the storage node.

Description

캐패시터 제조방법{METHOD FOR MANUFACTURING CAPACITOR}Capacitor manufacturing method {METHOD FOR MANUFACTURING CAPACITOR}

본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 실린더형 하부전극의 셀간 브릿지를 방지하도록 한 캐패시터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor to prevent the inter-cell bridge of a cylindrical lower electrode.

최근에 반도체소자의 집적도가 증가함에 따라 반도체소자의 크기, 즉 단위셀의 크기가 작아지고 소자 동작에 요구되는 일정한 기준의 충전용량을 확보하기 위하여 많은 연구가 진행되고 있다.Recently, as the degree of integration of semiconductor devices increases, many researches have been conducted to ensure the size of semiconductor devices, that is, the size of unit cells, become smaller and to ensure a predetermined charging capacity required for device operation.

그리고, 셀의 크기가 0.15㎛이하로 작아지고 지속적으로 집적화되면서 0.13㎛의 소자개발이 이루어지고 있는데, 이러한 집적화된 소자의 동작에 요구되는 충전용량을 확보하기 위해 종래 3차원 구조를 갖는 NO(Nitride Oxide) 실린더형 (Cylinder)의 캐패시터 대신 유전상수값이 높은 탄탈륨산화막(Ta2O5) 캐패시터가 개발되었다.In addition, as the size of the cell becomes smaller than 0.15 μm and continuously integrated, the device development of 0.13 μm is being performed. In order to secure the charge capacity required for the operation of the integrated device, NO (Nitride) having a conventional three-dimensional structure is obtained. Oxide) Tantalum oxide (Ta 2 O 5 ) capacitors with high dielectric constants have been developed in place of cylindrical capacitors.

상술한 바와 같은 집적화된 소자의 캐패시터의 표면적을 증가시켜 셀 동작에 필요로 하는 일정 용량 이상의 충전용량을 확보하기 위해 공정 개발과 동시에 소자의 신뢰성 확보가 반도체 소자의 고집적화에서 해결해야 할 과제이다.In order to increase the surface area of the capacitor of the integrated device as described above to secure the charging capacity of a certain capacity or more required for cell operation, securing the reliability of the device at the same time as the process development is a problem to be solved in the high integration of the semiconductor device.

이러한 캐패시터의 표면적을 증가시키기 위해 최근에 스토리지노드(하부전극)의 표면을 요철화시켜 표면적을 증가시키기 위해 비정질 실리콘(Amorphous silicon; a-Si)막상에 시딩(Seeding)후 고진공 열처리(High vacuum annealing)를 실시하여 선택적으로 HSG(Hemi-Spherical Grain)막을 형성하는 방법을 적용하고 있다. 그리고, 스토리지노드의 표면을 요철화시키는 다른 방법으로는 MPS(Meta stable PolySilicon) 공정이 있다.In order to increase the surface area of the capacitor, high vacuum annealing after seeding on an amorphous silicon (a-Si) film to increase the surface area by unevening the surface of the storage node (lower electrode) recently. (Hemi) to selectively form a HSG (Hemi-Spherical Grain) film is applied. In addition, another method of roughening the surface of the storage node is a meta stable polysilicon (MPS) process.

도 1은 종래기술에 따라 제조된 캐패시터를 도시한 도면이다.1 is a view showing a capacitor manufactured according to the prior art.

도 1을 참조하여 종래기술의 캐패시터의 제조 방법을 설명하면, 트랜지스터 및 비트라인(도시 생략)의 제조 공정이 완료된 반도체기판(11)상에 층간절연막(12)을 형성한 후, 층간절연막(12)을 선택적으로 식각하여 반도체기판(11)의 표면이 노출되는 콘택홀을 형성한다. 계속해서, 콘택홀을 포함한 층간절연막(12)상에 폴리실리콘막을 형성한 후, 층간절연막(12)의 표면이 드러날때까지 폴리실리콘막을 화학적기계적연마(Chemical Mechanical Polishing; CMP) 또는 에치백(Etchback)하여 콘택홀에 매립되는 폴리실리콘플러그(13)를 형성한다.Referring to FIG. 1, a method of manufacturing a capacitor of the related art is described. After the interlayer insulating film 12 is formed on a semiconductor substrate 11 on which transistors and bit lines (not shown) are manufactured, an interlayer insulating film 12 is formed. ) Is selectively etched to form a contact hole through which the surface of the semiconductor substrate 11 is exposed. Subsequently, after the polysilicon film is formed on the interlayer insulating film 12 including the contact hole, the polysilicon film is chemically mechanically polished (CMP) or etchback until the surface of the interlayer insulating film 12 is exposed. ) To form a polysilicon plug 13 embedded in the contact hole.

다음으로, 폴리실리콘플러그(13)가 매립된 층간절연막(12)상에 스토리지노드의 높이를 결정짓는 캐패시터 산화막(14)을 형성한 후, 감광막에 의한 스토리지노드마스크(도시 생략)로 캐패시터산화막(14)을 식각하여 폴리실리콘플러그(13)에 정렬되는 스토리지노드가 형성될 영역(이하 오목부라 약칭함)을 노출시킨다.Next, after forming the capacitor oxide film 14 which determines the height of the storage node on the interlayer insulating film 12 in which the polysilicon plug 13 is embedded, the capacitor oxide film (not shown) is formed as a storage node mask (not shown). 14) is etched to expose an area (hereinafter abbreviated as recess) for forming a storage node aligned with the polysilicon plug 13.

다음으로, 노출된 오목부를 포함한 캐패시터산화막(14)상에 폴리실리콘을 형성한 다음, 캐패시터산화막(14)이 드러날때까지 폴리실리콘을 화학적기계적연마하여 이웃한 셀간 서로 분리되며 폴리실리콘으로 이루어진 스토리지노드(15)를 오목부내에만 형성한다.Next, polysilicon is formed on the capacitor oxide film 14 including the exposed recesses, and then polysilicon is chemically mechanically polished until the capacitor oxide film 14 is exposed, and the neighboring cells are separated from each other and are made of polysilicon storage nodes. (15) is formed only in the recessed part.

계속해서, 스토리지노드(15) 표면의 산화막을 제거하기 위한 습식세정을 실시한 후, 스토리지노드(15)의 표면에 반구형 폴리실리콘, 즉 HSG(16)을 형성한다.Subsequently, after wet cleaning for removing the oxide film on the surface of the storage node 15 is performed, hemispherical polysilicon, that is, HSG 16 is formed on the surface of the storage node 15.

상술한 종래기술에서는 캐패시터의 유효면적을 최대한 크게 확보하기 위하여 스토리지노드 사이의 공간(spacing)을 줄였다.In the above-described prior art, spacing between storage nodes has been reduced in order to secure the largest effective area of the capacitor.

그러나, 이웃한 셀간 스토리지노드를 격리시키기 위해 화학적기계적연마를실시하는데, 이 때, 디싱(Dishing) 현상으로 인해 캐패시터산화막이 아래로 조금 내려앉게 되어 스토리지노드가 약간 돌출하는 형태가 나타나는 문제점이 있으며, 더욱이 후속 세정공정에 의해 이러한 돌출은 더욱 심하다.However, chemical mechanical polishing is performed to isolate the storage nodes between neighboring cells. At this time, the storage oxide slightly protrudes due to the dishing phenomenon, causing the storage node to slightly protrude. Moreover, this protrusion is even more severe with subsequent cleaning processes.

또한, 캐패시터의 유효면적을 극대화하기 위하여 HSG를 형성하는데, 이 때, 스토리지노드간의 좁은 공간에서 HSG가 서로 만나게 되어 스토리지노드간 브릿지(Bridge)(A)를 발생시키는 문제점이 있다.In addition, in order to maximize the effective area of the capacitor to form the HSG, in this case, there is a problem in that the HSG meets each other in a narrow space between the storage nodes to generate a bridge (A) between the storage nodes.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여 안출된 것으로, 스토리지노드간의 좁은 공간에서 HSG가 서로 접촉됨에 따른 스토리지노드간 브릿지를 방지하는데 적합한 캐패시터의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and an object of the present invention is to provide a method of manufacturing a capacitor suitable for preventing bridges between storage nodes due to HSG contact with each other in a narrow space between storage nodes.

도 1은 종래기술에 따라 제조된 캐패시터를 도시한 도면,1 is a view showing a capacitor manufactured according to the prior art,

도 2a 내지 도 2c는 본 발명의 실시예에 따른 캐패시터의 제조 방법을 나타낸 도면.2A to 2C illustrate a method of manufacturing a capacitor according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체기판 22 : 층간절연막21 semiconductor substrate 22 interlayer insulating film

23 : 폴리실리콘플러그 24 : 캐패시터 산화막23 polysilicon plug 24 capacitor oxide film

25 : 저도핑 폴리실리콘 26 : 감광막25 low-doped polysilicon 26 photosensitive film

27 : 스토리지노드 27a : 돌출부27: storage node 27a: protrusion

28 : HSG28: HSG

상기의 목적을 달성하기 위한 본 발명의 캐패시터의 제조 방법은 반도체기판상에 하부전극의 높이를 결정짓는 캐패시터산화막을 형성하는 단계, 상기 캐패시터산화막을 선택적으로 식각하여 상기 반도체기판의 표면이 노출되는 오목부를 형성하는 단계, 상기 오목부를 포함한 캐패시터산화막상에 저도핑 폴리실리콘을 형성하는 단계, 상기 저도핑 폴리실리콘상에 연마방지막을 도포하는 단계, 상기 캐패시터산화막의 표면이 드러날때까지 상기 연마방지막과 상기 저도핑 폴리실리콘을 화학적기계적연마하여 상기 오목부내에만 상기 저도핑 폴리실리콘으로 이루어진 스토리지노드를 형성하는 단계, 상기 화학적기계적연마후 잔류하는 상기 스토리지노드의 돌출부에 불순물을 이온주입하는 단계, 상기 연마방지막을 제거하는 단계, 및 상기 스토리지노드의 표면에 반구형 실리콘을 성장시키는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a capacitor of the present invention for achieving the above object is to form a capacitor oxide film for determining the height of the lower electrode on the semiconductor substrate, selectively etching the capacitor oxide film to expose the surface of the semiconductor substrate Forming a portion, forming a low-doped polysilicon on the capacitor oxide film including the concave portion, applying an anti-polishing film on the low-doped polysilicon, and the anti-polishing film and the substrate until the surface of the capacitor oxide film is exposed. Chemically polishing low-doped polysilicon to form a storage node made of the low-doped polysilicon only in the concave portion, ion implanting impurities into the protrusions of the storage node remaining after the chemical mechanical polishing, the anti-polishing film Removing the, and the storage Growing hemispherical silicon on the surface of the node.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2d는 본 발명의 실시예에 따른 캐패시터 형성 방법을 나타낸 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a capacitor according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 트랜지스터 및 비트라인(도시 생략)의 제조 공정이 완료된 반도체기판(21)상에 층간절연막(22)을 형성한 후, 감광막에 의한 콘택마스크(도시 생략)로 층간절연막(22)을 식각하여 반도체기판(21)의 표면이 노출되는 콘택홀을 형성한다.As shown in FIG. 2A, after forming the interlayer insulating film 22 on the semiconductor substrate 21 on which the manufacturing process of the transistor and the bit line (not shown) is completed, the interlayer insulating film is formed by a contact mask (not shown) by a photosensitive film. The hole 22 is etched to form a contact hole through which the surface of the semiconductor substrate 21 is exposed.

계속해서, 콘택홀을 포함한 층간절연막(22)상에 폴리실리콘막을 형성한 후, 층간절연막(22)의 표면이 드러날때까지 폴리실리콘막을 화학적기계적연마(CMP) 또는 에치백하여 콘택홀에 매립되는 폴리실리콘플러그(23)를 형성한다.Subsequently, after the polysilicon film is formed on the interlayer insulating film 22 including the contact hole, the polysilicon film is embedded in the contact hole by chemical mechanical polishing (CMP) or etching back until the surface of the interlayer insulating film 22 is exposed. The polysilicon plug 23 is formed.

다음으로, 폴리실리콘플러그(23)가 매립된 층간절연막(22)상에 스토리지노드의 높이를 결정짓는 캐패시터 산화막(24)을 16000Å ∼ 20000Å의 두께로 형성한 후, 감광막에 의한 스토리지노드마스크(도시 생략)로 캐패시터산화막(24)을 건식 식각하여 폴리실리콘플러그(23)에 정렬되는 스토리지노드가 형성될 영역(이하 오목부라 약칭함)을 노출시킨다.Next, a capacitor oxide film 24 for determining the height of the storage node on the interlayer insulating film 22 having the polysilicon plug 23 embedded therein is formed to a thickness of 16000 GPa to 20000 GPa, and then a storage node mask using a photosensitive film (not shown). The capacitor oxide film 24 is dry etched to expose a region (hereinafter referred to as a concave portion) in which the storage node aligned with the polysilicon plug 23 is to be formed.

다음으로, 노출된 오목부를 포함한 캐패시터산화막(24)상에내지의 농도로 저도핑 폴리실리콘(25)을 형성한 다음, 상기 저도핑 폴리실리콘(25)을 포함한 전면에 감광막(26)을 도포한다.Next, on the capacitor oxide film 24 including the exposed recesses. To After forming the low-doped polysilicon 25 at a concentration of, the photosensitive film 26 is applied to the entire surface including the low-doped polysilicon 25.

이 때, 감광막(26)외에 캐패시터산화막(24)와 식각선택비를 가진 물질, 예컨대 USG(Undoped Silicon Glass)를 이용할 수 있다.In this case, in addition to the photoresist layer 26, a material having an etching selectivity with the capacitor oxide layer 24, for example, USG (Undoped Silicon Glass) may be used.

도 2b에 도시된 바와 같이, 캐패시터산화막(24)이 드러날때까지 감광막(26)과 저도핑 폴리실리콘(25)을 동시에 화학적기계적연마하여 이웃한 셀간 서로 분리되는 스토리지노드(27)를 오목부내에만 잔류시킨다.As shown in FIG. 2B, only the storage node 27 separated from each other between neighboring cells by chemical mechanical polishing of the photoresist layer 26 and the low-doped polysilicon 25 simultaneously until the capacitor oxide layer 24 is exposed is provided in the concave portion. Remain.

이 때, 화학적기계적연마공정의 고유특성인 디싱현상으로 인해 감광막(26a)과 캐패시터산화막(24a)이 스토리지노드(27)보다 아래로 내려앉는다.At this time, the photosensitive film 26a and the capacitor oxide film 24a are lowered below the storage node 27 due to dishing, which is a unique characteristic of the chemical mechanical polishing process.

계속해서, 감광막(26a)과 캐패시터산화막(24a)이 내려앉아 드러나는 스토리지노드(27)의 돌출부(27a)에 P31소스(phosphorous)를내지의 농도로이온주입한다. 이 때, 감광막(26a)은 이온주입시 마스크로 이용된다.Subsequently, a P 31 source is applied to the protruding portion 27a of the storage node 27 where the photosensitive layer 26a and the capacitor oxide layer 24a are exposed. To At a concentration of Ion implantation. At this time, the photosensitive film 26a is used as a mask during ion implantation.

따라서, 스토리지노드(27)는 오목부내에 지지되는 저도핑영역과 돌출된 고도핑영역으로 이루어진다.Therefore, the storage node 27 is composed of a low doping region and a protruding high doping region which are supported in the recess.

도 2c에 도시된 바와 같이, 감광막(26)을 제거한 후, 드러난 스토리지노드의 표면에 620℃ , 1 ∼ 3torr, SiH4의 개스 분위기에서 HSG(28)를 성장시킨다. 이 때, HSG(28)의 성장속도는 도핑농도에 반비례하는데, 즉, 고도핑영역인 돌출부(27a)보다 저도핑영역에서 더 빨리 성장되며, 고도핑영역에서는 HSG(28)의 성장이 억제된다.As shown in FIG. 2C, after the photosensitive film 26 is removed, the HSG 28 is grown on a surface of the exposed storage node in a gas atmosphere of 620 ° C., 1 to 3 torr, and SiH 4 . At this time, the growth rate of the HSG 28 is inversely proportional to the doping concentration, that is, it grows faster in the low doping region than the protrusion 27a which is the high doping region, and the growth of the HSG 28 is suppressed in the high doping region. .

결국, 고도핑영역인 돌출부에서 HSG의 성장이 억제되므로 이웃한 스토리지노드간 브릿지를 방지할 수 있다.As a result, since the growth of the HSG is suppressed in the protrusion, which is a highly doped region, bridges between neighboring storage nodes can be prevented.

본 발명의 다른 실시예로서, 스토리지노드의 폴리실리콘을 증착할 때, 고도핑 폴리실리콘과 저도핑폴리실리콘을 적층하여 저도핑폴리실리콘상에만 HSG를 성장시킬 수 있다.As another embodiment of the present invention, when depositing polysilicon of the storage node, the HSG may be grown only on the low doped polysilicon by stacking the highly doped polysilicon and the low doped polysilicon.

그리고, 스토리지노드의 표면에 국부적으로 HSG를 성장시킬 수 도 있다.It is also possible to grow HSG locally on the surface of the storage node.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같은 본 발명은 불순물이 이온주입된 돌출부에서의 HSG 성장을 억제시켜 이웃한 스토리지노드간 브릿지를 방지하므로써 스토리지노드의 공간을 더욱 줄여 셀크기를 축소시키고 소자의 신뢰성 및 수율을 향상시킬 수 있는 효과가 있다.As described above, the present invention can suppress the bridge between neighboring storage nodes by inhibiting HSG growth in the protrusion into which the impurities are implanted, thereby further reducing the space of the storage node, thereby reducing the cell size and improving the reliability and yield of the device. It has an effect.

Claims (3)

반도체소자의 제조 방법에 있어서,In the manufacturing method of a semiconductor device, 반도체기판상에 하부전극의 높이를 결정짓는 캐패시터산화막을 형성하는 단계;Forming a capacitor oxide film determining a height of a lower electrode on a semiconductor substrate; 상기 캐패시터산화막을 선택적으로 식각하여 상기 반도체기판의 표면이 노출되는 오목부를 형성하는 단계;Selectively etching the capacitor oxide layer to form a recess in which the surface of the semiconductor substrate is exposed; 상기 오목부를 포함한 캐패시터산화막상에 저도핑 폴리실리콘을 형성하는 단계,Forming low-doped polysilicon on the capacitor oxide film including the concave portion, 상기 저도핑 폴리실리콘상에 연마방지막을 도포하는 단계;Applying an anti-polishing film on the low-doped polysilicon; 상기 캐패시터산화막의 표면이 드러날때까지 상기 연마방지막과 상기 저도핑 폴리실리콘을 화학적기계적연마하여 상기 오목부내에만 상기 저도핑 폴리실리콘으로 이루어진 스토리지노드를 형성하는 단계;Chemically polishing the anti-polishing film and the low-doped polysilicon until the surface of the capacitor oxide film is exposed to form a storage node made of the low-doped polysilicon only in the recess; 상기 화학적기계적연마후 잔류하는 상기 스토리지노드의 돌출부에 불순물을 이온주입하는 단계;Implanting impurities into protrusions of the storage node remaining after the chemical mechanical polishing; 상기 연마방지막을 제거하는 단계; 및Removing the anti-polishing film; And 상기 스토리지노드의 표면에 반구형 실리콘을 성장시키는 단계Growing hemispherical silicon on the surface of the storage node 를 포함하여 이루어짐을 특징으로 하는 캐패시터의 제조 방법.Method for producing a capacitor, characterized in that comprises a. 제 1 항에 있어서,The method of claim 1, 상기 스토리지노드의 돌출부에 불순물을 이온주입하는 단계에서,In the step of ion implanting impurities into the protrusion of the storage node, 상기 불순물은 P31소스를 포함하되, 그 농도가내지의 농도인것을 특징으로 하는 캐패시터의 제조 방법.The impurity comprises a P 31 source, the concentration of To Method for producing a capacitor, characterized in that the concentration of. 제 1 항에 있어서,The method of claim 1, 상기 연마방지막은 감광막 또는 USG 중 어느 하나를 포함함을 특징으로 하는 캐패시터의 제조 방법.The anti-polishing film is a manufacturing method of a capacitor, characterized in that it comprises any one of a photosensitive film or USG.
KR1020010039157A 2001-06-30 2001-06-30 Method for manufacturing capacitor KR100761405B1 (en)

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