KR20030002448A - Memory device having circuit for scrambling data - Google Patents

Abstract

PURPOSE: A memory device including an encryption circuit is provided to protect data although an encryption algorithm is disclosed without degrading a performance of a memory device. CONSTITUTION: A memory(1) stores data. An address buffer(2) buffers an address(ADD) inputted from an exterior. A low decoder(3) decodes a low address(RADD). A word line driving unit(4) drives a word line in accordance with a signal decoded by the low decoder(3). A column control unit(5) receives data from an exterior or outputs data to an exterior in accordance with a column address(CADD). A sense amp(6) senses and amplifies data stored in the memory(1). A key latch(7) is enabled in accordance with a key load signal(KL) and stores a key signal in accordance with data inputted from an exterior. Elements of the column control unit(5) are described as follows. A column decoder decodes a column address inputted from the address buffer(2). A hash table stores encryption method capable of being selected by the key signal of the key latch(7). An encryption control unit selects a bit line in accordance with a decoded signal of the column decoder, controls an input/output of data, and performs a data encryption in accordance with a method of the hash table corresponded to the key signal of the key latch(7).

Description

Memory device having a circuit for encryption {Memory device having circuit for scrambling data}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly, to a memory device including an encryption circuit including a circuit having a function of encrypting data for protecting data in a memory device.

Recently, with the development of information technology (IT) technology, a means for encrypting and protecting respective data for each process performed in one processor has been invented.

For example, a smart card has a built-in encryption means for encrypting important data or programs stored in the card so that routines of the program do not leak to the outside.

As a conventional method for protecting data, at the system level, the operating system (OS) has a function of preventing each process from modifying data of another process.

On the other hand, the microprocessor includes a function of protecting data in segments or pages to assist with OS level performance.

However, this method has a problem in that the performance of the memory device is degraded and the encryption itself is meaningless when the address scramble algorithm, which is a decoding method, is leaked.

An object of the present invention for solving such a problem is to protect data even if an encryption algorithm is known, without degrading the performance of the memory device.

1 is a block diagram showing an important part of a memory device including an encryption circuit according to the present invention.

FIG. 2 is a block diagram illustrating a detailed block of a column controller in the block diagram of FIG. 1. FIG.

FIG. 3 is a conceptual diagram illustrating an example of a method of scrambled 1 byte of data into 2 bytes in the convex diagram of FIG. 1. FIG.

<Description of Symbols for Major Parts of Drawings>

1: Memory 2: Address Buffer

3: row decoder 4: word line driver

5: column control unit 6: sense amplifier

7: key latch 8: column decoder

9: hash table 10: encryption control unit

A memory device including the encryption circuit of the present invention for achieving the above object comprises: a memory device for storing data, comprising: key storage means for storing a key signal in accordance with a load signal; Table storage means for storing a plurality of encryption methods performed by a key signal; And selectively connecting a bit line and a data bus, receiving an encryption method corresponding to a key signal stored in the key storage means from a table storage means, encrypting the input data, or decrypting the encrypted data and transmitting the encrypted data to the data bus. Characterized in that it comprises a cryptographic control means.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing an important part of a memory device including an encryption circuit according to the present invention.

The memory device includes a memory unit 1 for storing data DATA, an address buffer 2 for buffering an address ADD input from the outside, a row decoder 3 for decoding a row address RADD, In response to the signal decoded by the row decoder 3, the word line driver 4 driving the word line and the data DATA are externally input or output data DATA according to the column address CADD. The column control unit 5 to be sensed, the sense amplifier 6 for sensing and amplifying the data DATA stored in the memory unit 1, and the data DATA which are enabled according to the key load signal KL and input from the outside. And a key latch 7 for storing a key signal K.

2 is a block diagram showing a detailed block of the column control unit 5 of the memory device according to the present invention.

The column control unit 5 stores a column decoder 8 for decoding the column address CADD input from the address buffer 2 and an encryption method selectable by the key signal K of the key latch 7. The bit line BL is selected according to the hash table 9 and the decoded signal of the column decoder 8, the input / output of the data DATA is controlled, and the key signal of the key latch 7 is selected. And an encryption control unit 10 which performs data encryption according to the method of the hash table 9 corresponding to (K).

The encryption principle of the present invention is to modify the address decoder (here, the column control section 5) of the memory device in order to protect the program stored in the on-chip memory implemented inside the processor, so that the address of the memory is irregular. Is an address scrambling method in which is allocated.

That is, when reading data from the memory device, the number of bits output to the sense amplifier is much larger than the number of bits of the memory word, so that the correct data when the password is not known by scattering one word into several words (DATA) is not readable.

3 is a conceptual diagram illustrating an example of a method of distributing 1 byte of data DATA into 2 bytes of words.

As shown, the positions and order in which each bit is scattered are changed. The space of one byte remaining in the scrambled data in FIG. 3 stores the next data DATA selected by the column address. Here, there are several ways to store the data DATA in the remaining space.

The security level in this way increases exponentially with how many words one word is scrambled.

When a word line is selected in the memory device, the number of bits output through the sense amplifier is 8 words or more.

If only one of these bit scramble methods leaks, the circuit's structure can easily be decoded if it leaks. To secure a certain level of security regardless of circuit leakage, a method of scrambling using a secret key is used.

For example, if the key signal K is 8 bits long, up to 256 different scramble methods can be selected.

Here, words selected by the same word line are encrypted using the same key signal (K).

Since the circuit for implementing the method of using the key signal K signal is complicated and the area occupied by the circuit is increased, it adopts a scramble method that can be implemented through a simple circuit to use the characteristics of the key signal K. The method of selecting from the adopted scramble method is used.

Thus, the adopted scramble scheme is to use the scramble scheme stored in the hash table 9 and stored according to the key signal K.

For example, a method of using only a few bits among the bits of the key signal K and a method of selecting one of two types using parity of the key signal K may be used. .

In this case, the input / output data DATA is selectively inverted and stored according to the bit pattern of the key signal K in order to compensate for the problem of not using all the methods of the key signal K while simplifying a circuit for implementing the same. .

As an example of such a method, there is a method of exclusive-OR sum XOR of data DATA and key signal K for each bit.

Each process using the memory device first selects a key signal K to be used for the area of the data DATA to be protected, then provides a value of the key signal K to the data input of the memory device, and then loads a key. Apply the signal KL.

When the key load signal KL is enabled, after the key signal K is stored in the key latch 5, the data DATA is read and written by the same method as that of a general memory device. Here, the key signal K used for reading and writing data DATA is stored separately.

Looking at the light operation in the initial state as follows.

First, the input data DATA carried on the data bus DB is selectively inverted (using XOR) in accordance with the key signal K value.

The encryption control unit 10 selects one of various scramble methods stored in the hash table 9 from a predetermined key signal K. FIG.

At this time, only bits corresponding to the address designated by the column address CADD are enabled and transmitted through the sense amplifier 6, and data DATA is written to the cell connected to the word line selected by the row address RADD. You lose.

Operation by other control signals and address signals for controlling the memory device is the same as that of a general memory device.

Meanwhile, the read operation is as follows.

First, data DATA stored in a cell connected to a word line selected by the row address RADD is loaded on the bit line BL, amplified by the sense amplifier 6, and transmitted to the encryption controller 10.

In this case, since the data DATA corresponding to the address to be read is bit scrambled and stored, the words are arranged in the original manner through the reverse process of writing.

Here, the key signal K in the read operation has the same value as the key signal K in the write operation.

Subsequently, the data DATA is exclusively logical sum XORed with the key signal K value according to the column address CADD and transferred to the data bus DB.

As described above, the memory device according to the present invention has an effect of performing complex encryption without delay in a read or write operation.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

A memory device for storing data, the memory device comprising: Key storage means for storing a key signal in accordance with the load signal; Table storage means for storing a plurality of encryption methods performed by a key signal; Selectively connecting a bit line and a data bus, receiving an encryption method corresponding to a key signal stored in the key storage means from a table storage means, encrypting the input data or deciphering the encrypted data and transmitting the encrypted data to the data bus; Memory device comprising an encryption circuit characterized in that it comprises an encryption control means. The method of claim 1, The key storage means, And a storage circuit for storing an integer multiple of the data word. The method of claim 2, The key storage means, And a cryptographic circuit for designating a position of data to be stored using a lower bit among address signals according to the load signal. The method of claim 1, The encryption control means, And an exclusive logic sum of data and respective bits of the key signal to perform an encryption function according to a key signal value. The method of claim 1, The encryption control means, And a cryptographic circuit for encrypting a function of data and key signal values in a one-to-one correspondence using a table look-up method.