KR20030002430A - System and method for repairing fail cell in semiconductor memory device - Google Patents

Abstract

PURPOSE: A repair system of a semiconductor memory device and a method thereof are provided, which reduces a layout area of the memory device by removing a repair fuse and control circuit in the memory, and improves repair efficiency by performing a repair using an EEPROM, and increases a memory access time by removing a redundancy block. CONSTITUTION: A memory module(100) comprises a number of DRAMs(110) and an EEPROM(120) having fail address information as to the DRAMs, and a memory control part(200) transferring a command signal to generate a repair address to replace a fail address to the EEPROM after comparing the fain address information read from the EEPROM with an address for a write/read operation and then transferring signal indication which DRAM is failed to the memory module. The failed DRAM among the above DRAMs is repaired using the repair address transferred from the EEPROM.

Description

System and method for repairing fail cell in semiconductor memory device

The present invention relates to a repair system and method for a semiconductor memory device, and more particularly, to a repair system and a fail address stored in an EEPROM, in which a defective cell is repaired by storing a memory location and address information where a fail is generated in an EEPROM. The present invention relates to a method of repairing a cell in which a fail has occurred by comparing information with memory address information to be accessed.

In general, when any one of a large number of fine cells constituting a DRAM occurs, the DRAM may not function properly. Therefore, in this case, a redundancy scheme is adopted in which yield is increased by replacing defective cells by using spare memory cells installed in the DRAM in advance.

This redundancy scheme is to replace the defective cells with rows / column redundancy cells when the memory cells are checked as defective and to use the chips without discarding them.

The conventional repair method mainly uses a method of installing a redundancy cell, a control circuit, and a repair fuse in the DRAM, and replacing a failed memory cell with a redundancy cell using the control circuit and the repair fuse. . However, this method requires a large amount of repair fuse and additional control circuitry.

In addition, since the current repair method can only repair within each bank, when more failures occur than the number of fuses that can repair each bank, the failing memory cell can be repaired longer. There will be no.

In addition, there is a problem that the memory access time is increased due to the repair block.

Accordingly, an object of the present invention for solving such a problem is to reduce the layout area of the semiconductor memory device by removing the repair fuse and the control circuit in the memory.

Another object of the present invention is to improve the repair efficiency of a semiconductor memory device by performing repair using EEPROM.

Another object of the present invention is to increase the memory access time by eliminating redundancy blocks.

1 is a block diagram of a repair system of a semiconductor memory device according to a preferred embodiment of the present invention.

2 is a flowchart illustrating a repair method of a semiconductor memory device according to a preferred embodiment of the present invention.

The repair system for a semiconductor memory device according to the present invention for achieving this object is

A memory module comprising a plurality of devices and an EEPROM having fail address information for the plurality of devices;

After comparing the fail address information read from the EEPROM with an address for a write / read operation, a command signal for generating a repair address for replacing a fail address to the EEPROM is transmitted, and a device fails to the memory module. It has a memory control unit for transmitting a signal indicating whether or not it has occurred,

The failing device among the plurality of devices may be repaired using a repair address delivered from the EEPROM.

In addition, the repair method of a semiconductor memory device according to the present invention,

Testing the memory module to store fail address information in the EEPROM;

Reading EEPROM on the memory module and storing fail address information for each device in a memory controller;

Comparing fail address information for each device read from the EEPROM with address information for a read / write operation;

If the two address information is identical, transmitting a command signal to generate a repair address for replacing a fail address to the EEPROM, and transmitting a signal to the memory module indicating which device has failed;

Generating a repair address for replacing the fail address according to a command signal for generating the repair address; And

And repairing the cell of the device in which the fail is generated by using the repair address transferred from the EEPROM.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of a repair system for a semiconductor memory device according to an exemplary embodiment of the present invention, which includes a memory module 100, a memory controller 200, and a first address including a plurality of DRAMs 110 and EEROM 120. The bus line 300 includes a command data line 400, a control bus line 500, and a second address bus line 600.

Here, the EEPROM 120 stores fail address information for each DRAM 110 that is known after testing the memory module 110 and generates a repair address for replacing the fail address.

The memory controller 200 compares fail address information for each DRAM 110 read from the EEPROM 120 with an address for a write / read operation, and then generates a repair address for replacing the fail address with the EEPROM. A signal is transmitted to the memory module, which signals which device has failed.

The first address bus line 300 is used when the memory controller 200 accesses the DRAM 110 on the memory module 100.

The command data line 400 is used to transmit a signal indicating which device on the memory module has failed.

The control bus line 500 is used to transmit a command signal to the EEPROM 120 to generate a repair address for replacing the fail address.

The second address bus line 600 is used to transfer the repair address from the EEPROM 120 to the failing device 110.

Hereinafter, the operation of the repair system of the semiconductor memory device shown in FIG. 1 will be described in more detail with reference to FIG. 2.

First, after each memory 110 is tested, a memory having a certain amount of fail or less is made into the memory module 100, and after the memory module 100 is tested (S1), the fail on the memory module 100 is performed. The location and address information of the generated memory are stored in the EEPROM (S2).

Next, when power is applied to the system, the memory controller 200 reads the EEPROM 120 on the memory module 100 and stores fail address information for each memory (S3).

The system performs a read / write operation to perform various operations, in which the memory controller 200 compares fail address information for each memory 110 read from the EEPROM 120 with an address for a read / write operation. After (S4), if the two information match, the command signal to generate a repair address for replacing the fail address to the EEPROM (120) via the control bus line 500, and transmits the command signal through the command bus line (400) The memory module 100 transmits a signal indicating which device has failed.

Next, when the EEPROM 120 receives a command signal for generating a repair address for replacing the fail address through the command bus line 400, the EEPROM 120 generates a repair address for replacing the fail address (S5).

Subsequently, the generated repair address is transferred to the failing device 110 on the memory module 100 (S6), and the cell of the failing device 110 is repaired using the repair address (S7).

As described above, the present invention can reduce the layout area because the repair fuse and the control circuit in the memory can be removed by performing the repair using the EEPROM.

In addition, by performing the repair using the EEPROM, the repair efficiency can be improved because the repair does not have to be performed for each bank.

In addition, since the redundancy block inside the memory can be removed by performing the repair using the EEPROM, the memory access time can be reduced.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (7)

A memory module comprising a plurality of devices and an EEPROM having fail address information for the plurality of devices; After comparing the fail address information read from the EEPROM with an address for a write / read operation, a command signal for generating a repair address for replacing a fail address to the EEPROM is transmitted, and a device fails to the memory module. It has a memory control unit for transmitting a signal indicating whether or not it has occurred, The failing device of the plurality of devices is repaired by using a repair address delivered from the EEPROM. The method of claim 1, And the EEPROM generates the repair address according to a command signal for generating the repair address, and then transfers the generated repair address to a device on which the fail on the memory module is generated. The method of claim 1, And a control bus line used to transmit a command signal for generating a repair address for replacing the fail address from the memory controller to the EEPROM. The method of claim 1, And a command bus line, which is used to transmit a signal indicative of which device has failed from the memory controller to the memory module. The method of claim 1, A first address bus line used when the memory controller accesses the plurality of devices on the memory module; And And a second address bus line used to transfer the repair address transferred to the EEPROM to each device on the memory module. Testing the memory module to store fail address information in the EEPROM; Reading EEPROM on the memory module and storing fail address information for each device in a memory controller; Comparing fail address information for each device read from the EEPROM with address information for a read / write operation; If the two address information is identical, transmitting a command signal to generate a repair address for replacing a fail address to the EEPROM, and transmitting a signal to the memory module indicating which device has failed; Generating a repair address for replacing the fail address according to a command signal for generating the repair address; And Repairing a cell of a device in which a fail is generated by using the repair address transferred from the EEPROM. The method of claim 6, And transmitting the repair address transferred from the EEPROM to a device on which the fail on the memory module is generated via an address bus line.