KR20030002426A - Stress voltage generating circuit - Google Patents

Abstract

PURPOSE: A stress voltage generation circuit is provided, which improves a reliability by generating a stable stress voltage during a reliability test of a device. CONSTITUTION: A voltage generation unit(100) controls and outputs an output voltage by sensing a variation of a current and a variation of a threshold voltage of a diode device corresponding to a signal inputted from the external. And a voltage drop unit(101) controls and outputs a variation amount of a stress voltage(Vstress) by an output voltage applied from the voltage generation unit. The voltage generation unit comprises the first diode part controlling an output voltage according to the variation of the current and the variation of the threshold voltage by an external power supply voltage applied from the external, and a resistor device connected between an output port of the output voltage and a ground port. The voltage down unit comprises the second diode part dropping a voltage by being connected between the external power supply voltage and the output port of the stress voltage, and a switching device switched according to the output voltage applied from the voltage generation unit by being connected between the output port of the stress voltage and the ground port.

Description

Stress voltage generating circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stress voltage generating circuit, and in particular, by controlling stress points of a stress voltage generating unit in response to a change in a threshold voltage or a current of a diode caused by a process change and a temperature change, stable stress in a device reliability test. It relates to a stress voltage generation circuit for generating a voltage.

In general, semiconductor integrated circuits need to reduce chip power consumption, minimize influence of external noise, and improve device reliability and stable operation.

To this end, the semiconductor integrated circuit generates an internal power supply voltage Vint that is lower than the external power supply voltage Vext having a large change factor, and uses the internal circuit to operate the internal circuit.

There may be a number of ways to make such a stable internal power supply voltage Vint. However, in general, a current mirror type voltage drop converter converting an external power supply voltage Vext to an internal power supply voltage Vint using a reference potential as shown in FIG. 1. converter).

Referring to FIG. 1, most of the voltage drop converters take the form of differential amplifiers. First, the first reference potential generator 10 receives the external power supply voltage Vext to generate the first reference potential VR1, and the first reference. The reference potential VR1 applied by the potential generator 10 is potential-amplified by the amplifier 20 to generate a second reference potential VR2.

The second reference potential generator 30 applies a stress voltage to the second reference potential VR2 applied by the amplifier 20 to output the final voltage VR, and the internal power supply driver 40 supplies the final voltage VR. As a reference, an internal power supply voltage Vint is generated and applied to the internal circuit.

2 is a detailed circuit diagram of the first reference potential generator 10 of the conventional internal power supply voltage generator having such a configuration.

Referring to FIG. 2, the first reference potential generator 10 is a circuit for generating the reference potential VR1, and is configured by the configuration of the current mirror type PMOS transistors P1, P2, PMOS transistors P3, P4, and NMOS transistors N1, N2. The first reference potential VR1, which is approximately the threshold voltage of the NMOS transistor, is generated.

3 is a detailed circuit diagram of an amplifier 20 that amplifies the first reference potential VR1 applied from the first reference potential generator 10 and generates a second reference potential VR2.

Referring to FIG. 3, the amplifier 20 includes an operating amplifier (A1) to amplify a voltage value of the first reference potential VR1 at a threshold voltage level generated by the first reference potential generator 10. The second reference potential VR2 is generated, and the second reference potential VR2 is generated by adjusting the resistors R1 and R2 according to the formula of the second reference potential VR2 = (1 + R2 / R1) * VR1.

FIG. 4 is a detailed block diagram of the second reference potential generator 30. The stress voltage unit 31 that generates the stress voltage Vstress, the stress voltage Vstress and the amplifier 20 applied from the stress voltage unit 31 are shown in FIG. Comparing the second reference potential applied from the ()) is composed of a comparator 35 for generating a high voltage of the stress voltage Vstress or the second reference potential as the final voltage VR.

FIG. 5 is a detailed circuit diagram of the stress voltage unit 31 of the second reference potential generator 30 of FIG. 4.

Referring to FIG. 5, the stress voltage unit 31 receives a power supply voltage Vext through a source terminal, and a source terminal of each of the drain terminals of the PMOS transistors P5 and P6 and PMOS transistors P5 and P6 of the current mirror structure in which the gate terminals are commonly connected. PMOS transistors P7 and P8 with current mirrors connected to each other and gate terminals connected to each other, and current mirror type NMOS transistors N3 and N4 with drain terminals connected to the drain terminals of the PMOS transistors P7 and P8 and common gate terminals respectively. And a voltage generator 32 for outputting the output voltage V1 through the common drain terminal of the PMOS transistor P8 and the NMOS transistor N4.

In addition, the stress voltage unit 31 is connected in series between the power supply terminal Vext and the output terminal of the stress voltage Vstress, and is connected between the PMOS diodes P9 and P10 having the gate terminal and the drain terminal connected in common, and between the output terminal of the stress voltage Vstress and the ground terminal. And a voltage drop unit 33 formed of an NMOS transistor N5 receiving an output voltage V1 applied from the voltage generator 32 through the gate terminal.

However, the conventional stress voltage unit 31 having such a configuration has a problem in that the stress point is changed by changing the threshold voltage and current of the PMOS transistor and the NMOS transistor according to the process change and the ambient temperature change.

In other words, when testing with excessive stress (voltage and temperature) in order to ensure the reliability of the device, there is a problem that the screen is reduced due to excessive stress or too little stress on the device due to process changes or changes in voltage conditions. have.

The present invention has been made to solve the above problems, and by controlling the stress point of the stress voltage generation unit in response to the change of the threshold voltage or current of the diode caused by the process change and temperature change, when testing the reliability of the device The purpose is to improve the reliability by generating a stable stress voltage.

1 is a block diagram of a general internal power supply voltage generator.

FIG. 2 is a detailed circuit diagram of the first reference potential generator of FIG. 1. FIG.

FIG. 3 is a detailed circuit diagram of the amplifier of FIG. 1. FIG.

4 is a detailed configuration diagram illustrating a second reference potential generator of FIG. 1.

FIG. 5 is a detailed circuit diagram of the stress voltage unit of FIG. 4. FIG.

6 is a detailed circuit diagram of a stress voltage generation circuit according to the present invention.

7 to 11 show other embodiments of the present invention.

<Explanation of symbols for main parts of drawing>

10: first reference potential generating unit 20: amplifying unit

30: second reference potential generating unit 31: stress voltage unit

35: comparison unit 40: internal power driver

100: voltage generator 101: voltage drop unit

The stress voltage generation circuit of the present invention for achieving the above object, the voltage generation to detect the change in the current and the threshold voltage of the diode element corresponding to the input signal from the outside and to control the output voltage accordingly accordingly And a voltage drop means for controlling and outputting a change range of the stress voltage by the output voltage applied from the means and the voltage generating means.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

6 is a detailed circuit diagram of the stress voltage generating circuit of the present invention.

Referring to FIG. 6, the stress voltage generating circuit of the present invention has a PMOS diode P11 and P12 connected in series between the power supply voltage terminal Vext and the output terminal of the output voltage V2, and the gate and drain terminals are commonly connected, and the output terminal and the ground terminal of the output voltage V2. And a voltage generator 100 composed of a resistor R3 connected therebetween.

In addition, the stress voltage generation circuit is connected in series between the power supply voltage terminal Vext and the output terminal of the stress voltage Vstress, and is connected between the PMOS diodes P13 and P14 in which the gate terminal and the drain terminal are commonly connected, and are connected between the output terminal of the stress voltage Vstress and the ground terminal. A voltage drop unit 101 including a PMOS transistor P15 to which an output voltage V2 is applied from the voltage generator 100 through a terminal is provided.

The present invention having such a configuration controls the gate voltage of the PMOS transistor P15 of the voltage drop unit 101 by the output voltage V2 applied through the voltage generator 100.

That is, when the current of the PMOS diodes P11 and P12 decreases or the threshold voltage increases, the voltage generator 100 lowers the output voltage V2 to lower the gate voltage of the PMOS transistor P15 of the voltage drop unit 101.

On the contrary, the voltage generator 100 increases the gate voltage of the PMOS transistor P15 of the voltage drop unit 101 by increasing the output voltage V2 as the current of the PMOS diodes P11 and 12 increases or the threshold voltage decreases.

Therefore, when the threshold voltage of the PMOS diodes P11 and P12 increases or the current decreases, the voltage generator 100 may push the break point of the stress point so that a small stress may be applied at the same Vext. However, the PMOS transistor may be reduced by reducing the output voltage V2. By increasing the resistance value of P15, the break point of the stress point can be pushed forward.

On the contrary, when the threshold voltages of the PMOS diodes P11 and P12 decrease or the current increases, the potential of the output voltage V2 is increased to increase the resistance, thereby pushing back the break point of the stress point.

On the other hand, Figure 7 is another embodiment of a stress voltage generation circuit according to the present invention.

Referring to FIG. 7, the voltage generator 102 includes PMOS transistors P16 and P17 that receive a power supply voltage Vext through a source terminal and have a gate terminal connected to each other. In the PMOS transistor P17, a gate terminal and a drain terminal are commonly connected.

The voltage generator 102 includes a PMOS transistor P18 and a PMOS transistor P19 having a source terminal connected to the drain terminals of the PMOS transistors P18 and P19, a gate terminal connected to each other, and a gate terminal and a drain terminal commonly connected to each other. The NMOS transistor N6 is connected to the drain terminal of the transistors P18 and P19, respectively, and the gate terminal is commonly connected, and the NMOS transistor N7 is connected to the gate terminal and the drain terminal, and the common drain terminal of the PMOS transistor P18 and NMOS transistor N6 is formed. Output voltage V3 through.

In addition, the voltage drop unit 103 is connected in series between the power supply terminal Vext and the output terminal of the stress voltage Vstress, and is connected between the PMOS diodes P20 and P21 to which the gate terminal and the drain terminal are commonly connected, and between the output terminal of the stress voltage Vstress and the ground terminal. The PMOS transistor P22 receives the output voltage V3 applied from the voltage generator 102 through the gate terminal.

The voltage generator 102 having such a configuration controls the gate terminal of the PMOS transistor P22 of the voltage drop unit 103 by the output voltage V3 output through the drain terminal of the PMOS transistor P18.

Therefore, in the configuration of FIG. 7, by controlling the gate terminal of the PMOS transistor P22 of the voltage drop section 103 by the output voltage V3 output by the PMOS transistor P18, it is possible to reduce the change of the stress point by the PMOS transistor. do.

Of course, by operating only with a PMOS transistor, the stress point is not changed by the NMOS transistor.

8 is another embodiment of a stress voltage generation circuit according to the present invention.

Referring to FIG. 8, the voltage generator 104 is an NMOS diode connected between a resistor R4 connected between a power supply voltage terminal Vext and an output terminal of an output voltage V4, and an output terminal of the output voltage V4 and a ground terminal, and a gate terminal connected to a drain terminal. It consists of N8.

In addition, the voltage drop unit 105 is connected in series between the power supply terminal Vext and the output terminal of the stress voltage Vstress, and is connected between the NMOS diodes P9 and P10 having the gate terminal and the drain terminal connected in common, and between the output terminal of the stress voltage Vstress and the ground terminal. Thus, the NMOS transistor N11 receives an output voltage V4 applied from the voltage generator 104 through the gate terminal.

The voltage generator 104 having such a configuration controls the gate terminal of the NMOS transistor N11 of the voltage drop unit 105 by the output voltage V4 output through the drain terminal of the NMOS diode N8.

Therefore, in the configuration of FIG. 8, by controlling the gate terminal of the NMOS transistor N11 of the voltage drop section 103 by the output voltage V4 output by the NMOS diode N8, it is possible to reduce the change of the stress point by the NMOS transistor. do.

Of course, by operating only with an NMOS transistor, the stress point is not changed by the PMOS transistor.

On the other hand, Figure 9 is another embodiment of a stress voltage generation circuit according to the present invention.

Referring to FIG. 9, the voltage generator 106 includes PMOS transistors P23 and P24 that receive a power supply voltage Vext through a source terminal and have a gate terminal connected to each other. The PMOS transistor P24 has a gate terminal and a drain terminal connected in common.

The voltage generator 106 includes a PMOS transistor P25 and a PMOS transistor P26 having a source terminal connected to the drain terminals of the PMOS transistors P23 and P24, a gate terminal connected to each other, and a gate terminal and a drain terminal connected in common, respectively, and a PMOS transistor. NMOS transistor N12 with drain terminal and common gate terminal connected to drain terminal of transistors P25 and P26 respectively, and NMOS transistor N13 with gate terminal and drain terminal connected in common, and the common drain terminal of PMOS transistor P26 and NMOS transistor N13 Output the output voltage V5 through.

In addition, the voltage drop unit 107 is connected in series between the power supply terminal Vext and the output terminal of the stress voltage Vstress, and is connected between the NMOS diodes N14 and N15 having the gate terminal and the drain terminal connected in common, and between the output terminal of the stress voltage Vstress and the ground terminal. The NMOS transistor N16 receives an output voltage V5 applied from the voltage generator 106 through the gate terminal.

The voltage generator 106 having such a configuration controls the gate terminal of the NMOS transistor N16 of the voltage drop unit 107 by the output voltage V5 outputted through the drain terminal of the NMOS transistor N13.

Therefore, in the configuration of FIG. 9, by controlling the gate terminal of the NMOS transistor N16 of the voltage drop section 107 by the output voltage V5 output by the NMOS transistor N13, it is possible to reduce the change of the stress point by the NMOS transistor. do.

Of course, the stress point is not changed by the PMOS transistor by operating only with the NMOS transistor.

On the other hand, Figure 10 is another embodiment of a stress voltage generating circuit according to the present invention.

Referring to FIG. 10, the voltage generator 108 includes PMOS transistors P27 and P28 that receive a power supply voltage Vext through a source terminal and have a gate terminal connected to each other. The PMOS transistor P28 has a gate terminal and a drain terminal connected in common.

The voltage generator 108 includes a PMOS transistor P29 and a PMOS transistor P30 having a source terminal connected to the drain terminals of the PMOS transistors P27 and P28, a gate terminal connected to each other, and a gate terminal and a drain terminal commonly connected to each other. The NMOS transistor N17 is connected to the drain terminal of the transistors P29 and P30 and the drain terminal is connected to the gate terminal, and the NMOS transistor N18 is connected to the gate terminal and the drain terminal.

Therefore, the output voltage V6 is output through the common drain terminal of the PMOS transistor P29 and the NMOS transistor N17, and the output voltage V7 is output through the common drain terminal of the PMOS transistor P30 and the NMOS transistor N18.

Here, the output voltages V6 and V7 have the same Vgs (voltage difference between the gate and source) even when the power supply voltage Vext changes. In the case of the output voltage V6, the Vgs of the PMOS transistor P33 is about the power supply voltage Vext-2Vt (threshold voltage). It is always close to zero and the output voltage V7 is about the threshold voltage Vt, so the Vgs of NMOS transistor N21 always maintains about Vt.

In addition, the voltage drop unit 109 is connected in series between the power supply terminal Vext and the output terminal of the stress voltage Vstress, and is connected between the PMOS diodes P31 and P32 having the gate terminal and the drain terminal connected in common, and between the output terminal of the stress voltage Vstress and the ground terminal. The PMOS transistor P33 receives the output voltage V6 applied from the voltage generator 108 through the gate terminal.

In addition, the voltage drop unit 109 is connected in series between the power supply terminal Vext and the output terminal of the stress voltage Vstress, and is connected between the NMOS diodes N19 and N20 having a common gate terminal and a drain terminal, and between the output terminal of the stress voltage Vstress and the ground terminal. Therefore, the NMOS transistor N21 receives an output voltage V7 applied from the voltage generator 108 through the gate terminal.

The voltage generator 108 having such a configuration controls the gate terminal of the PMOS transistor P33 of the voltage drop unit 109 by the output voltage V6 output through the drain terminal of the PMOS transistor P29.

The gate terminal of the NMOS transistor N21 of the voltage drop unit 109 is controlled by the output voltage V7 output through the drain terminal of the NMOS transistor N18.

Therefore, in the circuit of FIG. 10, even if the power supply voltage Vext changes, the PMOS transistor P33 and the NMOS transistor N21 are controlled by the output voltages V6 and V7 having the same Vgs value.

That is, the output voltage V6 is about Vext-2Vt, so the Vgs of the PMOS transistor P33 is always close to zero, and the output voltage V7 is about the threshold voltage Vt, so the Vgs of the NMOS transistor N21 always maintains about Vt.

Therefore, when the threshold voltage of the PMOS diode decreases or the current increases, or when the threshold voltage of the NMOS transistor increases or the current decreases, the amount of change in the stress point may be canceled.

In addition, when the threshold voltage of the PMOS diode increases or the current decreases, or when the threshold voltage of the NMOS transistor decreases or the current decreases, the amount of change of the stress point may be canceled out.

On the other hand, Figure 11 is another embodiment of a stress voltage generating circuit according to the present invention.

Referring to FIG. 11, the first voltage generator 110 includes PMOS transistors P34 and P35 that receive a power supply voltage Vext through a source terminal and have a common gate terminal connected thereto. The PMOS transistor P35 has a common connection between a gate terminal and a drain terminal. And a PMOS transistor P36 and a PMOS transistor P37 having a source terminal connected to the drain terminals of the PMOS transistors P34 and P35 and a gate terminal connected to each other, and a gate terminal and a drain terminal connected in common, respectively, and the drain terminals of the PMOS transistors P36 and P37. And an NMOS transistor N22 having a drain terminal connected to each other and a gate terminal connected to each other, and an NMOS transistor N23 having a gate terminal and a drain terminal connected to each other, and outputting an output voltage V8 through a common drain terminal of the PMOS transistor P37 and the NMOS transistor N23. .

In addition, the second voltage generator 111 is connected in series between the power supply voltage terminal Vext and the output terminal of the output voltage V9, and the PMOS diodes P41 and P42 having the gate terminal and the drain terminal connected in common, and between the output terminal and the ground terminal of the output voltage V9. It consists of a resistor R5 connected to output the output voltage V9.

In addition, the voltage drop unit 112 is connected in series between the power supply terminal Vext and the output terminal of the stress voltage Vstress, and is connected between the NMOS diodes N24 and N25 having the gate terminal and the drain terminal connected in common, and between the output terminal of the stress voltage Vstress and the ground terminal. Therefore, the NMOS transistor N26 receives an output voltage V8 applied from the first voltage generator 110 through the gate terminal.

In addition, the voltage drop unit 112 is connected in series between the power supply terminal Vext and the output terminal of the stress voltage Vstress, and is connected between the PMOS diodes P38 and P39 in which the gate terminal and the drain terminal are commonly connected, and the output terminal of the stress voltage Vstress and the ground terminal. The PMOS transistor P40 receives the output voltage V9 applied from the second voltage generator 111 through the gate terminal.

The first voltage generator 110 having such a configuration controls the gate terminal of the NMOS transistor N26 of the voltage drop unit 112 by the output voltage V8 output through the drain terminal of the NMOS transistor N23.

The second voltage generator 111 controls the gate terminal of the PMOS transistor P40 of the voltage drop unit 112 by the output voltage V9 output through the drain terminal of the PMOS transistor P42.

Accordingly, in the circuit of FIG. 11, the NMOS transistor N26 and the PMOS transistor P40 are controlled by the output voltages V8 and V9 output by the NMOS transistor and the PMOS transistor, respectively, so that the threshold voltage of the PMOS diode decreases or the current increases. When the threshold voltage of the NMOS transistor increases or the current decreases, the amount of change in the stress point can be canceled.

In addition, when the threshold voltage of the PMOS diode is increased or the current is decreased, the amount of change of the stress point may be canceled out even when the threshold voltage of the NMOS transistor is decreased or the current is decreased.

As described above, the stress voltage generation circuit of the present invention provides an effect of improving the reliability by generating a stable stress voltage regardless of the process change and temperature change during the test of the device.

Claims (12)

Voltage generating means for detecting a change in current and a change in threshold voltage of a diode element corresponding to a signal input from the outside and controlling and outputting the output voltage accordingly; And And a voltage drop means for controlling and outputting a change range of the stress voltage by the output voltage applied from the voltage generation means. The method of claim 1, wherein the voltage generating means A first diode part controlling an output voltage according to a change in current and a change in threshold voltage by an external power supply voltage applied from the outside; And And a resistance element connected between the output terminal of the output voltage and the ground terminal. The method of claim 2, wherein the voltage drop means A second diode connected between the external power supply voltage and an output terminal of the stress voltage to drop a voltage; And And a switching element connected between an output terminal of the stress voltage and a ground terminal and switched according to an output voltage applied from the voltage generating means. The method of claim 2, wherein the first diode portion A stress voltage generation circuit comprising a plurality of PMOS diodes connected in series between an external power supply voltage terminal and an output terminal of an output voltage and having a common connection between a gate terminal and a drain terminal. The method of claim 3, wherein the second diode portion A stress voltage generation circuit comprising a plurality of PMOS diodes connected in series between an external power supply voltage terminal and an output terminal of a stress voltage, and having a gate terminal and a drain terminal connected in common. The method of claim 3, wherein the switching device And a PMOS transistor connected in series between the output terminal of the stress voltage and the ground terminal to receive the output voltage through a gate terminal. The method of claim 1, wherein the voltage generating means A stress voltage generator circuit comprising: a current mirror type differential amplifier comprising a PMOS transistor and an NMOS transistor; and a voltage generator for outputting an output voltage from the PMOS transistor. The method of claim 7, wherein the voltage drop means A PMOS diode unit connected between the external power supply voltage and an output terminal of the stress voltage to drop a voltage; And And a PMOS switching element connected between an output terminal of the stress voltage and a ground terminal and switched according to an output voltage applied from the voltage generating means. The method of claim 1, wherein the voltage generating means A resistor connected between an external power supply voltage terminal and an output terminal of the output voltage; And And a NMOS diode connected between the resistance element and the ground terminal, the gate terminal and the drain terminal of which are commonly connected. The method of claim 9, wherein the voltage drop means An NMOS diode unit connected between the external power supply voltage and an output terminal of the stress voltage to drop a voltage; And And an NMOS transistor connected between the NMOS diode unit and a ground terminal and switched according to an output voltage applied from the voltage generating means. The method of claim 1, wherein the voltage generating means A current mirror type differential amplifier consisting of a PMOS transistor and an NMOS transistor generates a first output voltage having a reduced threshold voltage at an external power supply voltage from the PMOS transistor, and a second output voltage having a constant value from the NMOS transistor. Stress voltage generation circuit, characterized in that consisting of negative. The method of claim 11, wherein the voltage drop means A PMOS diode unit connected between the external power supply voltage and an output terminal of the stress voltage to drop a voltage; A PMOS switching element connected between the first PMOS diode unit and a ground terminal and switched according to a first output voltage applied from the voltage generating means; An NMOS diode unit connected between the external power supply voltage and an output terminal of the stress voltage to drop a voltage; And And an NMOS switching element connected between the NMOS diode part and a ground terminal and switched according to a second output voltage applied from the voltage generating means.