KR20030002236A - Equalization and precharge control signal generating device of data bus - Google Patents

Abstract

PURPOSE: An apparatus for generating equalization and precharge control signals of a data bus is provided to improve reduction of margins of an equalizing time and a precharge time in a data bus by controlling differently an enable time and a disable time of equalization and precharge of the data bus in a writing process and a reading process. CONSTITUTION: The first pulse generation portion(10) controls a rising time of a data bus precharge control signal(dbeq) according to an inputting state of a y pre-pulse signal(yprep) and a read signal(rd). The second pulse generation portion(20) controls a falling time of the data bus precharge control signal(dbeq) according to an output of the first pulse generation portion(10) and the read signal(rd). The first pulse generation portion(10) is formed with the first NAND gate(nd1) for receiving the y pre-pulse signal(yprep), the first delay portion(D1), an AND gate(ad1) for receiving a delay signal of the first delay portion(D1), the second delay portion(D2), an inverter(iv3), and a second NAND gate(nd2). The second pulse generation portion(20) is formed with a NAND gate(nd3), the third delay portion(D3), an AND gate(ad2), the fourth delay portion(D4), an inverter(iv4), and the fourth NAND gate(nd4). A buffer portion(30) buffers an output of the third NAND gate(nd3) and outputs a data bus precharge control signal(dbeq).

Description

Equalization and precharge control signal generating device of data bus

The present invention relates to an apparatus for generating an equalization and precharge control signal for a data bus, and more particularly, to maximize an operating frequency margin during high-speed operation by controlling precharge and equalization signals of a data bus differently during read and write. An apparatus for generating an equalization and precharge control signal for a data bus that enables high-speed operation.

1 is a block diagram of a conventional device for generating an equalization and precharge control signal for a data bus.

FIG. 1 is a circuit diagram for controlling the timing of a data bus precharge signal dbeq, and includes a first delay unit 1 that receives a y prepulse signal yprep having pulse width information of a column select signal yi and delays it for a predetermined time. Inverts the output of the first delay unit 1 and generates the pulse signal after a predetermined time delay after receiving the inverter iv0 outputting the y prepulse signal yprep to the pulse generator 2 and the output of the inverter iv0. And a buffer unit 4 for buffering the pulse signal applied from the pulse generator 2 and outputting the data bus precharge signal dbeq.

The pulse generator 2 described above is composed of the second delay unit 3 and the NAND gate nd0, and the output of the inverter iv0 is input to the input terminals of the second delay unit 3 and the NAND gate nd0, respectively, and the second delay unit The output of (3) is input to the other input terminal of the NAND gate nd0.

The buffer unit 4 is composed of an even number of non-inverting inverters iv1 and iv2 to buffer the pulse signal applied from the pulse generator 2 to output the data bus precharge signal dbeq.

Here, the y prepulse signal yprep is input to the first delay unit 1 as a signal having pulse width information of the column selection signal yi during the column operation.

The data bus precharge signal dbeq is a signal used to control the equalization and precharge of the data bus. Since the operation timing is centered on the column selection signal yi, the second delay part of the pulse generator 2 is performed. According to (3), the y prepulse signal yprep is delayed for a predetermined time.

Referring to the timing diagram of FIG. 2, the operation of the conventional data bus equalization and precharge control signal generator having the above configuration will be described below.

2, since the synchronous DRAM operates in synchronization with a clock, a write command wt or a read command rd is input according to the clock signal clk.

Next, among the plurality of column addresses, the column select signal yi corresponding to the address applied together with the write command wt or the read command rd is enabled in pulse form. In the period typw where the column select signal yi is high, the precharge pcg of the data bus It is released and data is transferred to the data bus.

Then, in the section eq & pcg section in which the column select signal yi is low, the data select signal is precharged and equalized by the data bus precharge signal dbeq as a preparation section for receiving the next data.

Therefore, the data bus precharge signal dbeq is centered on the pulses of the column select signal yi. When the column command is applied to generate the column select signal yi and the data bus precharge signal dbeq, the reference of the pulse of the column select signal yi is used. The y prepulse signal yprep that becomes a pulse is enabled and generates various control signals using the signal.

At this time, the time point at which the pulse of the data bus precharge signal dbeq is enabled is determined by the write command wt, and the time point when disabled is determined by the read command rd.

That is, the write driver enable signal bwen must be enabled by tbw time before the column select signal yi because the data must be written to the data bus before the column select signal yi is enabled.

Therefore, the databus precharge signal dbeq must be enabled tm0 hours before the write driver enable signal bwen, so that the precharge pcg must be released, and tm0 + tbw hours must be enabled before the column select signal yi is enabled. It is enabled after a delay as small as t0 at the time of enabling the pulse signal yprep.

On the other hand, during the read command rd, data is output to the cell and then applied to the data bus sense amplifier to amplify the small amount of voltage transmitted to the data bus. A signal for enabling the data bus sense amplifier is a data bus enable. The signal is dbsastp.

Since the databus enable signal dbsastp is enabled tsa later than the column select signal yi, the databus precharge signal dbeq is also relatively precharged after the time of tm1.

As a result, the databus precharge signal dbeq must be enabled according to both the write command wt and the read command rd, so that the enable time at the write time and the disable time at the read time result in a larger than the pulse width of the column select signal yi. do.

Accordingly, the high-speed operation of the semiconductor memory device has a problem in which the data bus precharge signal dbeq is low, that is, the precharge and equalization time are reduced, causing a failure in the high-speed operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and controls the equalization and precharge enable and disable times of the data bus at write and read time, respectively, so that the data bus can be operated at a high speed operation of the semiconductor memory device. The purpose is to improve the reduction in the margin of equalization and precharge time.

1 is a block diagram of a device for generating an equalization and precharge control signal for a conventional data bus.

2 is an operation timing diagram of an equalization and precharge control signal generator of a conventional data bus.

3 is a block diagram of an equalization and precharge control signal generator of a data bus according to the present invention;

4 is an operation timing diagram of an equalization and precharge control signal generator of a data bus according to the present invention;

5 is another embodiment of an equalization and precharge control signal generator of a data bus according to the present invention;

6 is another embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

10: first pulse generator 20: second pulse generator

30,70: buffer unit 40: light delay unit

50: lead delay unit 60: logic operation unit

The equalization and precharge control signal generator of the data bus of the present invention for achieving the above object delays a prepulse signal having pulse width information of a column selection signal at write time by a first delay time and prepulse at read time. A first pulse generating means for delaying the signal by a second delay time greater than the first delay time and outputting it as a first signal, delaying the first signal at the time of writing by a third delay time, and removing the first signal at the time of reading. And a second pulse generating means for delaying the fourth delay time larger than the three delay time and outputting the second signal, and a buffer portion for buffering the second signal and outputting the data bus precharge control signal. The rising time of the data bus precharge control signal is controlled, and the polling time of the data bus precharge control signal is controlled by the second signal.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a block diagram of an apparatus for generating an equalization and precharge control signal for a data bus according to the present invention.

3 is a circuit for controlling the timing of the data bus precharge control signal dbeq, wherein a first pulse is generated to control the rising time of the data bus precharge control signal dbeq according to whether the y prepulse signal yprep and the read signal rd are input. And a second pulse generator 20 for controlling the polling time of the data bus precharge control signal dbeq according to the output of the first pulse generator 10 and the input of the read signal rd. At the time of writing, the polling time of the data bus precharge control signal dbeq is controlled quickly, and at the time of read, the rising time of the databus precharge control signal dbeq is controlled slowly.

The above-described first pulse generator 10 includes the NAND gate nd1 and delay unit D1 to which the y prepulse signal yprep is input, the AND gate ad1 and delay unit D2 to which the delay signal of the delay unit D1 is input, and the delay unit D2. The inverter iv3 inverts the delay signal and outputs it to the NAND gate nd2, and the NAND gate nd2 receives the NAND operation of the inverted signal and the read signal rd of the inverter iv3 and outputs one end of the AND gate ad1. The NAND operation of the output of the prepulse signal yprep and the AND gate ad1 is output to the second pulse generator 20.

In addition, the second pulse generator 20 may include the NAND gate nd3 and the delay unit D3 to which the output of the NAND gate nd1 of the first pulse generator 10 is input, and the AND gate ad2 and the delay signal of the delay unit D3. Inverter iv4, which inverts the delay signal of delay unit D4, delay unit D4, and outputs to NAND gate nd4; The NAND gate nd3 performs a NAND operation on the output of the NAND gate nd1 and the output of the AND gate ad2 of the first pulse generator 10, and outputs the output to the buffer unit 30.

The buffer unit 30 includes a plurality of non-inverting inverters iv5 and iv6 to buffer the output of the NAND gate nd3 of the second pulse generator 20 to output the data bus precharge signal dbeq.

The first pulse generator 10 of the present invention having such a configuration is a circuit for controlling the delay of the rising time of the data bus fetch control signal dbeq according to the y prepulse signal yprep.

First, when the y prepulse signal yprep transitions high, the read signal rd is low at the time of writing, so the output of the NAND gate nd1 is high, and the NAND gate nd1 is low after the delay time t0 of the delay unit D1.

The second pulse generator 20 is a circuit for controlling the delay of the polling time of the data bus fetch control signal dbeq according to the y prepulse signal yprep.

First, when a low signal is input from the first pulse generator 10, a high signal is output through the NAND gate nd3 regardless of the output of the AND gate ad2.

Subsequently, when a high signal is input to the buffer unit 30 through the NAND gate nd3 of the second pulse generator 20, a high signal is output after time t0 through the non-inverting inverters iv5 and iv6.

When the y prepulse signal yprep transitions low, the output of the NAND gate nd1 becomes high without passing through the delay units D1 and D2 regardless of the output of the AND gate ad1 in the first pulse generator 10.

Subsequently, when a high signal is input to the second pulse generator 20, the read signal is low, so the output of the NAND gate nd2 becomes high, and the output of the NAND gate nd3 is after the delay time t2 hours of the delay unit D3. It goes low.

Next, when the low signal is input to the buffer unit 30 by the NAND gate nd3 of the second pulse generator 20, the low signal is finally output through the non-inverting inverters iv5 and iv6.

Therefore, as shown in FIG. 4, when writing, the delay time of the data bus precharge signal dbeq becomes t0 at rising and t2 at polling.

On the other hand, if the y pre-pulse signal yprep input to the first pulse generator 10 transitions high during read, the output of the AND gate ad1 of the first pulse generator 10 will be reduced since the read signal rd is in a high state. After rising of the y pre-pulse signal yprep, the state becomes high after the delay time t0 + t1 of the delay units D1 and D2.

Subsequently, the NAND gate nd1 of the first pulse generator 10 outputs a low signal to the second pulse generator 20 after a time t0 + t1.

The second pulse generator 20 is high after the time t0 + t1 through the NAND gate nd3 regardless of the output of the AND gate ad2 according to the low signal applied from the NAND gate nd1 of the first pulse generator 10. Outputs the signal of.

The buffer 30 receiving the high signal outputs the data bus precharge signal dbeq high through the non-inverting inverters iv5 and iv6.

On the contrary, when the y prepulse signal yprep transitions low, the output of the NAND gate nd1 becomes high without passing through the delay units D1 and D2 regardless of the output of the AND gate ad1 of the first pulse generator 10.

Subsequently, a high signal is input to the second pulse generator 20 and the read signal rd is in a high state, so that the output of the AND gate ad2 of the second pulse generator 20 is polled after the y prepulse signal yprep. The NAND gate nd3 becomes low after the time t2 + t3 because the state becomes high after the delay time t2 + t3 of the delay units D3 and D4.

The output of the buffer unit 30 outputs the last low signal through the non-inverting inverters iv5 and iv6.

Therefore, the delay time of the data bus precharge signal dbeq at the read time becomes to + t1 at the rising time and t2 + t3 at the polling time.

On the other hand, the operation of the equalization and precharge control signal generator of the data bus of the present invention will be described with reference to the timing diagram of FIG.

Referring to FIG. 4, the present invention quickly controls an enable time of the data bus precharge signal dbeq at the time of a write command wt using a flag signal that distinguishes a command between write and read, and disables the column selection signal yi. Quickly control to disable within minimum time after disable.

In addition, during the read command rd, the enable time of the data bus precharge signal dbeq is controlled to a minimum time to be enabled before the enable time of the column select signal yi, and the disable time is after the disable of the data bus enable signal dbsastp. Control to disable in minimum time.

Therefore, according to the present invention, the enable time and the disable time of the data bus precharge signal dbeq are controlled differently at the time of writing and reading, thereby further securing the equalization eq and the precharge pcg time margin at high speed operation.

As a result, the databus precharge signal dbeq differs in the enable time and the pulse width, respectively, during the write and read commands.

As can be seen from the waveform in FIG. 4, it can be seen that in the continuous operation of the light and the read, the equalization time of the present invention represented by the solid line is relatively more secured than the prior art equalization time indicated by the dotted line.

On the other hand, Figure 5 shows another embodiment of the present invention.

Referring to FIG. 5, in the configuration of FIG. 3 of the present invention, delay units D7 and D10 may be further provided in the read signal rd input units of the first pulse generator 10 and the second pulse generator 20.

The delay units D7 and D10 can control the timing of the circuit for delaying the y prepulse signal yprep when the read signal rd is applied.

On the other hand, Figure 6 shows another embodiment of the present invention.

Referring to FIG. 6, the apparatus of FIG. 6 separately configures the write delay unit 40 and the read delay unit 50, and receives the y prepulse signal yprep and the read signal rd, respectively.

Under the control of the write / lead flag signal, the outputs of the two delay units 40 and 50 are logically operated through the oragate 60, and the data bus is formed through the buffer unit 70 formed of the non-inverting inverters iv7 and iv8. Output the precharge signal dbeq.

That is, the write delay unit 40 operating at the time of the write command determines the delay time through the write delay device at the time of writing. At this time, the read delay unit 50 is disabled.

On the contrary, when the read command is performed, the delay time is determined through the read delay unit 50, and when the two signals output through the delay units 40 and 50 through the oragate 60 are logically operated together, the write and The databus precharge signal dbeq can be controlled differently at read time.

As described above, the data bus equalization and precharge control signal generator of the present invention improves the frequency problem of high speed operation by reducing the problem of failing during high speed operation, and reduces the size of the equalization and precharge transistors. There is an advantage that the size can be reduced.

Claims (11)

Delaying the prepulse signal having the pulse width information of the column selection signal at the time of the first delay time by the first delay time, and delaying the prepulse signal at the read time by the second delay time larger than the first delay time and outputting the first signal First pulse generating means; Second pulse generation means for delaying the first signal by a third delay time when writing and delaying the first signal by a fourth delay time greater than the third delay time and outputting the second signal as a second signal; And And a buffer unit for buffering the second signal to output the data bus precharge control signal. The rising time of the data bus precharge control signal is controlled by the first signal, and the polling time of the data bus precharge control signal is controlled by the second signal. Control signal generator. The method of claim 1, wherein the first pulse generating means Delay means for delaying the prepulse signal by the first delay time when writing and delaying the prepulse signal by the second delay time when reading; And Logic operation means for outputting the first signal by logical operation of the prepulse signal and the output signal delayed by the delay means according to the input state of the read signal, the equalization and precharge control signal generation of the data bus Device. The method of claim 2, wherein the delay means A first delay unit which delays the rising time of the prepulse signal by the first delay time and outputs the same by writing the first delay time; A second delay unit which delays the rising time of the prepulse signal by the fifth delay time and outputs the read time; And And an inverter for inverting and outputting the delay signal of the second delay unit. Equalizing and precharge control signal generation device of a data bus, characterized in that configured to not pass through the first delay unit and the second delay unit when polling the prepulse signal. 4. The logical operation means according to claim 3, A first NAND gate which receives the output of the inverter and the read signal and performs a logical operation; A first and gate for receiving an output of the first delay unit and an output signal of the first NAND gate and performing a logical operation; And a second NAND gate configured to receive the prepulse signal and the output signal of the first and gate and perform a logical operation. The method of claim 2, wherein the first pulse generating means An equalization and precharge control signal generator of a data bus, further comprising a delay unit for controlling a delay of a read time at an input terminal of a read signal. The method of claim 1, wherein the second pulse generating means Delay means for delaying the first signal by the third delay time when writing and delaying the first signal by the fourth delay time when reading; And Generation of equalization and precharge control signals of a data bus, characterized in that it comprises a logical operation means for outputting the second signal by logical operation of the first signal and the output signal delayed by the delay means according to the input state of the read signal. Device. The method of claim 6, wherein the delay means A first delay unit configured to delay and output the polling time of the first signal by the third delay time during writing; A second delay unit configured to delay and output the polling time of the first signal by the six delay time during reading; And And an inverter for inverting and outputting the delay signal of the second delay unit. And an equalizing and precharging control signal generator of a data bus, wherein the pre-pulse signal is configured not to pass through the first delay unit and the second delay unit. The method of claim 6, wherein the logical operation means A third NAND gate which receives the output of the inverter and the read signal and performs a logical operation; A second and gate configured to receive an output of the first delay unit and an output signal of the third NAND gate and perform a logical operation; And a fourth NAND gate configured to receive the first signal and the output signal of the second and gate and perform a logical operation. The method of claim 6, wherein the second pulse generating means An equalization and precharge control signal generator of a data bus, further comprising a delay unit for controlling a delay of a read time at an input terminal of a read signal. A write delay unit controlling and outputting a delay time of a control signal when enabling the write signal; A read delay unit controlling and outputting a delay time of the control signal when the read signal is enabled; A logic operation unit configured to logically output an output of the write delay unit and the read delay unit; And And a buffer unit for outputting a data bus precharge signal by buffering an output pulse of the logic operation unit. The method of claim 10, And the write delay unit and the read delay unit operate relative to each other.