KR20030002225A - Method for fabricating capacitor in semiconductor device - Google Patents
Method for fabricating capacitor in semiconductor device Download PDFInfo
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- KR20030002225A KR20030002225A KR1020010038979A KR20010038979A KR20030002225A KR 20030002225 A KR20030002225 A KR 20030002225A KR 1020010038979 A KR1020010038979 A KR 1020010038979A KR 20010038979 A KR20010038979 A KR 20010038979A KR 20030002225 A KR20030002225 A KR 20030002225A
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- South Korea
- Prior art keywords
- film
- plate electrode
- capacitor
- conductive film
- forming
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- 239000003990 capacitor Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000010408 film Substances 0.000 claims description 60
- 239000010409 thin film Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229910003071 TaON Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중커패시터 제조 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a capacitor manufacturing process in a semiconductor device manufacturing process.
반도체 소자의 미세화에 따른 메모리셀의 커패시터 면적 축소와 안정적인 동작을 확보하기 위한 용량 확보가 포인트이며, 각 사에서 여러 가지 연구를 하고 있는데, 크게 스택 커패시터(stack capacitor) 구조와 트랜치(trench capacitor) 구조로 분류할 수 있다. 스택 커패시터 구조는 실리콘(Si) 기판상에 3차원 구조의 커패시터를 만든 것이고, 트랜치 구조는 실리콘 기판에 깊은 홀(hole)을 파서, 커패시터을 기판 내부에 형성하여, 커패시터 용량을 얻는 것이다.The point is to reduce the capacitor area of the memory cell and secure the capacity to secure stable operation according to the miniaturization of semiconductor devices, and various companies are doing various researches, which are largely stack capacitor structure and trench capacitor structure. Can be classified as The stack capacitor structure is a three-dimensional capacitor made on a silicon (Si) substrate, the trench structure is to dig a deep hole in the silicon substrate, to form a capacitor inside the substrate to obtain a capacitor capacity.
트랜치 커패시터의 이점은 기판내부에 커패시터를 형성하기 때문에 커패시터 형성 후에도 평탄한 표면을 유지할 수 있으며, 로직 프로세스에 비해서, 고온 열처리가 필요한 커패시터 형성을 트랜치스터 형성 전에 실시하기 때문에, 트랜지스트의 고성능화가 쉽다는 점을 들 수 있다. 단점으로서는 커패시터 용량 확보를 위해서 깊고, 큰 어스펙트 비(aspect ratio)의 트랜치의 가운데에 커패시터를 형성하기 때문에 미세화가 되면 메모리 셀를 안정적으로 만드는 것이 곤란하게 된다는 점이다.The advantage of the trench capacitor is that the capacitor is formed inside the substrate, so that a flat surface can be maintained even after the capacitor is formed, and compared to the logic process, since the formation of a capacitor requiring high temperature heat treatment is performed before the formation of the transistor, it is easy to increase the performance of the transistor. There is a point. The disadvantage is that it is difficult to make the memory cell stable when miniaturized because the capacitor is formed in the center of the deep and large aspect ratio trench to secure the capacitor capacity.
한편, 스택 커패시터(stack capacitor)를 이용한 메모리 셀의 장점은, 메모리 셀를 축소하기 쉽다는 것과 만들기 쉽다는데 있다. 트랜지스터 형성 후에 커패시터 형성을 하기 때문에, 차후 고온 처리가 필요한 BST등의 고유전체 막을 이용한 커패시터의 도입이 용이하다는 점도 큰 매력이 된다. 그러나 트랜치 커패시터의 단점은 기판상에 입체 커패시터를 형성하는 것에 따라 발생하는 메모리 셀 영역과 로직부의 평면 단차가 고밀도 다층배선 형성, 콘택 형성에 대해서 장벽이 된다는 점이다.On the other hand, the advantages of memory cells using stack capacitors are that they are easy to shrink and easy to make. Since the capacitor is formed after the transistor is formed, it is also a great attraction that it is easy to introduce a capacitor using a high-k dielectric film such as BST that requires high temperature treatment in the future. However, the disadvantage of the trench capacitor is that the planar step difference between the memory cell region and the logic portion generated by the formation of the three-dimensional capacitor on the substrate is a barrier to the formation of high density multilayer wiring and contact.
또, 트랜지스터 형성 후에 커패시터 형성을 하기 때문에 커패시터 형성에 필요한 열처리가 트랜지스터의 고성능화에 영향을 준다는 점을 들 수 있다. 이러한 점들을 종합해서 볼 때 메모리셀을 만들기 쉽고, 셀사이즈를 축소하기 쉬운 스택 커패시터를 주로 선택한다.In addition, since the capacitor is formed after the transistor is formed, the heat treatment necessary for capacitor formation affects the performance of the transistor. Taken together, the stack capacitors are mainly selected for making memory cells easy and reducing cell size.
그러나, 종래기술에 따른 스택 커패시터를 형성 공정은 전하저장전극 상에 유전체 박막 및 플레이트전극을 적층하는 방식을 사용하기 때문에 셀 영역과 주변회로 영역 간에 단차가 심하게 발생하였으며, 이에 따라 후속 금속 콘택 공정이 용이하지 못하였다.However, since the stack capacitor forming process according to the related art uses a method of stacking a dielectric thin film and a plate electrode on a charge storage electrode, a step is severely generated between the cell region and the peripheral circuit region. It was not easy.
또한, 종래기술은 유전막을 사이에 두고 배치된 상, 하부전극들이 하나의 전극만을 이용하므로, 도핑(Doping) 농도에 따라 유전막 사이에서 공핍 폭(depletion width)이 크게 나타나 셀 커패시턴스가 작아지므로 센싱 마진(Sensing Margin)이 떨어지므로 소자의 동작 특성이 열화되는 문제점이 있었다.In addition, in the related art, since the upper and lower electrodes disposed with the dielectric film interposed therebetween use only one electrode, the margin of sensing is increased due to the large depletion width between the dielectric films according to the doping concentration, thereby decreasing the cell capacitance. Since (Sensing Margin) is falling there was a problem that the operating characteristics of the device deteriorated.
본 발명은 셀 영역과 주변회로 영역 간의 단차를 줄이고, 셀 커패시턴스를 확보할 수 있는 반도체 소자의 커패시터 제조방법을 제공함을 그 목적으로 한다.An object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device capable of reducing the step difference between the cell region and the peripheral circuit region and ensuring cell capacitance.
도1 내지 도7은 본 발명의 일 실시예에 따른 커패시터 제조 공정도.1 to 7 are diagrams illustrating a capacitor manufacturing process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
22 : 제1 산화막22: first oxide film
23 : 제1 플레이트전극용 전도막23: conductive film for first plate electrode
25 : 제2 산화막25: second oxide film
26 : 제2 플레이트전극용 전도막26: conductive film for second plate electrode
28 : 유전체 박막28: dielectric thin film
29 : 전하저장전극용 전도막29: conductive film for charge storage electrode
상기 목적을 달성하기 위한 본 발명의 일 측면에 따르면, 소정의 도전 구조및 절연 구조가 형성된 기판 상에 제1 절연막을 형성하는 단계; 셀 영역의 상기 제1 절연막 상에 제1 플레이트전극용 전도막을 형성하는 단계; 상기 제1 플레이트전극용 전도막이 형성된 전체 구조 상부에 제2 절연막을 형성하는 단계; 커패시터 형성 영역의 상기 제2 절연막, 상기 제1 플레이트전극용 전도막 및 상기 제1 절연막을 선택적으로 식각하는 단계; 상기 제2 절연막, 상기 제1 플레이트전극용 전도막 및 상기 제1 절연막이 노출된 패턴의 측벽에 제2 플레이트전극용 전도막을 형성하는 단계; 상기 제2 플레이트전극용 전도막 표면을 구상화하는 단계; 구상화된 상기 제2 플레이트전극용 전도막 표면에 유전체 박막을 형성하는 단계; 및 상기 도전 구조와 콘택되며 상기 유전체 박막을 덮도록 전하저장전극을 형성하는 단계; 를 포함하는 반도체 소자의 커패시터 제조방법이 제공된다.According to an aspect of the present invention for achieving the above object, a step of forming a first insulating film on a substrate on which a predetermined conductive structure and an insulating structure are formed; Forming a conductive film for a first plate electrode on the first insulating film in the cell region; Forming a second insulating film on the entire structure in which the conductive film for the first plate electrode is formed; Selectively etching the second insulating film, the conductive film for the first plate electrode, and the first insulating film in the capacitor formation region; Forming a second plate electrode conductive film on sidewalls of the pattern in which the second insulating film, the first plate electrode conductive film, and the first insulating film are exposed; Spheroidizing a surface of the conductive film for the second plate electrode; Forming a dielectric thin film on a surface of the spherical conductive film for the second plate electrode; And forming a charge storage electrode in contact with the conductive structure and covering the dielectric thin film. There is provided a capacitor manufacturing method of a semiconductor device comprising a.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도1 내지 도7은 본 발명의 일 실시예에 따른 반도체 소자의 커패시터의 제조 공정도이다.1 to 7 are manufacturing process diagrams of a capacitor of a semiconductor device according to an embodiment of the present invention.
본 실시예에 따르면, 먼저 도1에 도시한 바와 같이, 반도체기판(10)상에 소정영역에 소자분리막(11)을 형성하고, 게이트절연층(12), 게이트전극(13), 게이트하드마스크(14), 스페이서(15) 및 소오스/드레인 영역(도시되지 않음)으로 구성되는 모스 트랜지스터와, 랜딩 플러그 콘택(19) 및 비트라인(18)를 형성한다. 도면부호 16은 층강절연막을 나타낸 것이다. 이어서, 전체 구조 상부에 층간절연층(20) 및 식각베리어층(21)을 차례로 증착하고, 이를 선택 식각하여 랜딩 플러그 콘택(19)을 노출시키는 전하저장전극 콘택홀을 형성한 다음, 전하저장전극 콘택홀 내에 폴리실리콘 플러그(31)를 형성한다. 계속하여, 전체 구조 상부에 제1 산화막(22) 및 제1 플레이트전극용 전도막(23)을 차례로 증착하고, 셀 영역을 덮는 포토레지스트 패턴(24)을 사용하여 제1 플레이트전극용 전도막(23)을 건식 식각한다. 여기서, 제1 산화막(22)으로는 HDP(High Density Plasma), USG(Undoped Silicate Glass), PSG(Phospho Silicate Glass), PE-TEOS(Plasma Enhanced Tetra Ethyl OrthoSilicate), LP-TEOS(Low Pressure Tetra Ethyl Ortho Silicate Glass), BPSG(Boro-Phospho-Silicate Glass) 등을 사용할 수 있으며, 제1 플레이트전극용 전도막(23)으로는 폴리실리콘이나 금속을 사용한다.According to the present embodiment, first, as shown in FIG. 1, an isolation layer 11 is formed in a predetermined region on the semiconductor substrate 10, and the gate insulating layer 12, the gate electrode 13, and the gate hard mask are formed. (14), a MOS transistor composed of a spacer 15 and a source / drain region (not shown), a landing plug contact 19 and a bit line 18 are formed. Reference numeral 16 denotes a layered steel insulating film. Subsequently, the interlayer insulating layer 20 and the etching barrier layer 21 are sequentially deposited on the entire structure, and then selectively etched to form a charge storage electrode contact hole exposing the landing plug contact 19. The polysilicon plug 31 is formed in the contact hole. Subsequently, the first oxide film 22 and the first plate electrode conductive film 23 are sequentially deposited on the entire structure, and the first plate electrode conductive film (using the photoresist pattern 24 covering the cell region) is deposited. 23) Dry etch. Here, the first oxide layer 22 may include HDP (High Density Plasma), USG (Undoped Silicate Glass), PSG (Phospho Silicate Glass), PE-TEOS (Plasma Enhanced Tetra Ethyl OrthoSilicate), LP-TEOS (Low Pressure Tetra Ethyl) Ortho Silicate Glass (BOSG), Boro-Phospho-Silicate Glass (BPSG), and the like may be used. As the conductive film 23 for the first plate electrode, polysilicon or a metal may be used.
이어서, 도 2에 도시된 바와 같이 포토레지스트 패턴(24)을 제거하고 전체 구조 상부에 제2 산화막(25)을 증착한다.Next, as shown in FIG. 2, the photoresist pattern 24 is removed and a second oxide film 25 is deposited on the entire structure.
계속하여, 도3에 도시된 바와 같이 커패시터가 형성될 영역의 상기 제2 산화막(25), 제1 플레이트전극용 전도막(23) 및 제1 산화막(22)을 선택적으로 식각하여 폴리실리콘 플러그(19)를 오픈시킨다.Subsequently, as illustrated in FIG. 3, the second oxide film 25, the first plate electrode conductive film 23, and the first oxide film 22 in the region where the capacitor is to be formed are selectively etched to form a polysilicon plug ( Open 19).
다음으로, 도4에 도시된 바와 같이 전체 구조 표면을 따라 제2 플레이트전극용 전도막(26)을 증착한다. 이때, 제2 플레이트전극용 전도막(26)으로는 폴리실리콘(또는 비정질실리콘)을 사용한다.Next, as shown in FIG. 4, the conductive film 26 for the second plate electrode is deposited along the entire structure surface. In this case, polysilicon (or amorphous silicon) is used as the conductive film 26 for the second plate electrode.
이어서, 도5에 도시된 바와 같이 에치백(Etch Back) 공정을 진행하여 제1 및제2 산화막(22, 25)의 측벽 부분에만 제2 플레이트전극용 전도막(26)을 잔류시키고, 그 표면에 반구형 실리콘 그레인(27)을 증착한다.Subsequently, as shown in FIG. 5, an etch back process is performed to leave the conductive film 26 for the second plate electrode only on the sidewall portions of the first and second oxide films 22 and 25, and on the surface thereof. Hemispherical silicon grains 27 are deposited.
계속하여, 도6에 도시된 바와 같이 전체 구조 표면을 따라 유전체 박막(28)을 증착하고, 에치백 공정을 진행하여 반구형 실리콘 그레인(27) 상부에만 유전체 박막이 잔류되도록 한다. 여기서 유전체 박막(28)으로는 PZT(Pb(Zr,Ti)O3), TiO, STO(SrTiO3), TaO, TaON, ONO(Oxide-Nitride-Oxide), NO(Oxide-Nitride-Oxide) 또는 BST((Ba,Sr)TiO3) 등을 사용할 수 있다.Subsequently, as shown in FIG. 6, the dielectric thin film 28 is deposited along the entire structure surface, and the etch back process is performed so that the dielectric thin film remains only on the hemispherical silicon grains 27. The dielectric thin film 28 may include PZT (Pb (Zr, Ti) O 3 ), TiO, STO (SrTiO 3), TaO, TaON, Oxide-Nitride-Oxide (ONO), Oxide-Nitride-Oxide (NO), or BST. ((Ba, Sr) TiO 3 ) and the like can be used.
다음으로, 도7에 도시된 바와 같이 전체 구조 상부에 전하저장전극용 전도막(29)을 증착하고, 화학기계연마(CMP) 공정을 실시하여 전하저장전극용 전도막(29)이 셀 단위로 격리되도록 한다. 여기서, 전하저장전극용 전도막(29)으로는 폴리실리콘막을 사용할 수 있다. 한편, CMP 공정 후에 급속열처리(RTP, Rapid ThermalProcessing) 또는 퍼니스(furnace) 열처리를 실시하여 유전체 박막(28)의 계면 특성을 확보할 수 있다.Next, as shown in FIG. 7, the conductive film 29 for the charge storage electrode is deposited on the entire structure, and the chemical mechanical polishing (CMP) process is performed to form the charge storage electrode conductive film 29 in units of cells. To be isolated. Here, a polysilicon film may be used as the conductive film 29 for the charge storage electrode. Meanwhile, after the CMP process, rapid thermal processing (RTP) or furnace (heat furnace) heat treatment may be performed to ensure interfacial characteristics of the dielectric thin film 28.
상기와 같은 공정을 진행하는 경우, 플레이트전극이 2개의 전도막으로 구성되기 때문에 커패시터의 공핍 폭을 줄일 수 있으며, 구상화 공정을 통해 셀 커패시턴스를 확보할 수 있다. 또한, 셀 영역과 주변회로 영역 간의 단차를 제거할 수 있다.In the above process, since the plate electrode is composed of two conductive films, the depletion width of the capacitor can be reduced, and cell capacitance can be secured through the spheroidization process. In addition, the step between the cell region and the peripheral circuit region can be eliminated.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
예컨대, 상기의 공정은 COB(Capacitor on Bit Line) 구조 또는 박스(Box)형 스택(Stack) 구조의 커패시터 형성시에도 적용할 수 있다.For example, the above process may be applied to the formation of a capacitor having a COB (Capacitor on Bit Line) structure or a box-type stack structure.
또한, 전술한 실시예에서는 구상화 공정으로 반구형 실리콘 그레인을 형성하는 경우를 일례로 들어 설명하였으나, 본 발명은 전하저장전극용 전도막으로 금속막을 사용하여 소정의 열처리를 통해 그 표면을 구상화하는 경우에도 적용된다.In addition, in the above-described embodiment, the case of forming the hemispherical silicon grains in the spheroidizing process is described as an example. However, the present invention also uses a metal film as the conductive film for the charge storage electrode to form the surface through a predetermined heat treatment. Apply.
이상에서 살펴본 바와 같이 셀 영역과 주변회로 영역의 단차를 최소화하여 후속 금속 콘택 공정을 용이하게 하는 효과가 있으며, 셀 캐패시턴스를 확보하여 센싱 마진을 개선하는 효과가 있다.As described above, there is an effect of facilitating subsequent metal contact processes by minimizing the step difference between the cell region and the peripheral circuit region, and improving the sensing margin by securing the cell capacitance.
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