KR20030000351A - Memory system capable of changing the termination resistance of bus channel - Google Patents

Abstract

PURPOSE: A memory system to change a terminal resistance value of a bus channel is provided to change the terminal resistance value of the bus channel to an optimal value according to a load condition of the memory system. CONSTITUTION: The system includes a memory controller(20), the bus channel(22), two memory modules(24,26), the first memory slot(28), the second memory slot(30), a switching circuit(32) and the channel terminal resistances(Rterm1-RtermN). The memory modules include a plurality of memory devices and the channel terminal resistances are connected with a terminal voltate(Vterm). The main controller(20) controls the input/output of the data to the memory modules(24,26) through the bus channel(22). The memory modules(24,26) acts as the load of the bus channel(22) by connecting to the memory slots(28,30). The switching circuit(32) connects the optimal one among the channel terminal resistances(Rterm1-RtermN) with the bus channel(22).

Description

Memory system capable of changing the termination resistance of a bus channel

The present invention relates to a memory system, and more particularly to a memory system that can change the channel termination resistance.

Typical memory systems include memory controllers, memory modules and bus channels. The memory module includes a plurality of memory elements. The bus channel connects a memory controller and a plurality of memory modules through memory slots. The memory module acts as a load on the bus channel, degrading the electrical characteristics of the bus channel. In other words, the parasitic components of the memory module reduce the bandwidth of the bus channel and cause impedance mismatching. Thus, especially when the memory system operates at a high frequency, the signal passing through the bus channel is deformed, thereby degrading signal integrity.

In order to prevent the degradation of the signal fidelity of the bus channel described above, a channel termination resistor is attached to the end of the bus channel. 1 is a diagram illustrating a conventional memory system having one channel termination resistor. Referring to FIG. 1, a conventional memory system includes a memory controller 10, a bus channel 12, memory modules 14 and 16, memory slots 18 and 19, and a channel termination resistor Rterm. . Here, the memory modules 14 and 16 are mounted in the memory slots 18 and 19, respectively, and are connected to the bus channel 12. The channel termination resistor (Rterm) reduces reflected waves due to impedance mismatch of the bus channel termination, thereby reducing channel noise and improving signal fidelity.

However, depending on the load condition of the memory system, such as the type and number of memory modules mounted in the memory slot, the electrical characteristics appearing in the bus channel and the noise generated accordingly appear slightly different. Therefore, the channel termination resistance value that gives the best signal fidelity of the bus channel also varies slightly.

However, in the conventional memory system, when the memory system is completed, the channel termination resistance value is fixed to one. Therefore, there is a problem in that the optimum channel termination resistance value cannot be changed according to the load condition of the memory system.

An object of the present invention is to provide a memory system capable of changing the channel termination resistance value to an optimal value according to the load condition of the memory system.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a conventional memory system having one channel termination resistor.

2 is a diagram illustrating a memory system capable of changing a channel termination resistance value, which is a temporary example of the present invention.

3A to 3D schematically illustrate a change in a signal passing through a bus channel according to a change in channel termination resistance when the single bank module is mounted only in a first memory slot of a memory system according to an embodiment of the present invention. Drawing.

4A to 4D illustrate a signal passing through a bus channel according to a change in channel termination resistance when a double bank module is mounted in a first memory slot and a second memory slot of a memory system according to an embodiment of the present invention. It is a figure which shows a change schematically.

In order to achieve the above object, the memory system of the present invention comprises at least one memory module; A memory controller controlling the memory module through a bus channel; A plurality of resistors each having a different resistance value; And a switching circuit connecting one of the resistors and the bus channel according to the configuration of the memory module.

The objects, features and advantages of the present invention described above will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

2 is a diagram illustrating a memory system according to an exemplary embodiment of the present invention. Referring to FIG. 2, a memory system according to an embodiment of the present invention may include a memory controller 20, a bus channel 22, two memory modules 24 and 26, a first memory slot 28, and a second memory system. A memory slot 30, a switching circuit 32, and N channel termination resistors Rterm1, ..., RtermN are provided. The memory modules 24 and 26 include a plurality of memory devices, and the channel termination resistors Rterm1,..., RtermN are commonly connected to the terminal voltage Vterm.

The memory controller 20 controls data to be input / output to the memory modules 24 and 26 through the bus channel 22.

The memory modules 24 and 26 are mounted in the memory slots 28 and 30 and serve as a load of the bus channel 22. The memory modules 24 and 26 may be a single bank module or a double bank module. In the case of a memory slot equipped with a single bank module, one memory device is connected to a bus channel. In the case of a double bank module, two memory elements are connected to the bus channel. The single bank module and the double bank module act as loads of different characteristics on the bus channel.

The switching circuit 32 connects one optimal channel termination resistor among the N resistors Rterm1, ..., RtermN to the bus channel 22. That is, the switching circuit 32 may selectively connect the channel termination resistor suitable for the load condition of the memory system according to the embodiment of the present invention to the bus channel 22 to effectively reduce the reflected wave of the high frequency signal. Thus, the noise of the bus channel 22 can be significantly reduced, and the signal fidelity can be significantly improved.

3A to 4D are diagrams for describing what is the best channel termination resistance value for a memory system after mounting memory modules having different characteristics in a memory slot. That is, this is a diagram showing an eye pattern measured by the memory module 24 of the first memory slot 28 when a write operation is performed to the memory system according to an embodiment of the present invention. .

3A to 3D illustrate a signal passing through a bus channel 22 according to a change in channel termination resistance when a single bank module is mounted only in a first memory slot 28 of a memory system according to an embodiment of the present invention. It is a figure which shows schematically a change of. 3A to 3D are diagrams showing cases where the channel termination resistance values are 30 (Ω), 50 (Ω), 70 (Ω), and 90 (Ω), respectively. 3A to 3D, the magnitude of the signal voltage increases as the channel termination resistance value increases. In addition, the size of the aperture due to the eye opening gradually increases, thereby improving signal fidelity as a whole.

4A to 4D illustrate a bus according to a change in a channel termination resistance value when a double bank module is mounted in a first memory slot 28 and a second memory slot 30 of a memory system according to an embodiment of the present invention. A diagram schematically illustrating a change in the signal passing through the channel 22. 4A to 4D are diagrams showing cases where the channel termination resistance values are 30 (Ω), 50 (Ω), 70 (Ω), and 90 (Ω), respectively. 4A to 4D, the size of the aperture in the eye pattern does not increase as the channel termination resistance value increases, but only the channel noise due to overshoot in the upper and lower portions of the aperture greatly increases. .

Therefore, when the single bank module is mounted only in the first memory slot 28, the signal termination resistance in the bus channel 22 can be improved by using the channel termination resistance value of about 90 (Ω). On the contrary, when the double bank module is mounted in both memory slots 28 and 30, if the channel termination resistance value is about 30 to 50 (Ω), the signal fidelity in the bus channel 22 can be improved. have.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. .

The memory system of the present invention described above may change the channel termination resistance value according to the load of the bus channel. Therefore, since the optimum channel termination resistance value can be selected, the noise of the high frequency signal is reduced, and the high frequency characteristic of the bus channel is improved. In addition, the high speed operation of the memory system can be effectively performed.

Claims (1)

At least one memory module; A memory controller controlling the memory module through a bus channel; A plurality of resistors each having a different resistance value; And And a switching circuit for selectively connecting one of the resistors and the bus channel according to the configuration of the memory module.