KR200264241Y1 - Data generation device for digital summator performance verification of modem output for code division multiple access base station - Google Patents

Abstract

The present invention relates to a data generation circuit for testing the performance of a circuit for digitally summing the output of a code division multiple access mobile communication system base station modem. Conventionally, the output of a mobile communication system base station modem is summed with 16 bit digital serial data. Since there was no means to test the performance of the digital summing circuit, the quality and reliability of the service could not be guaranteed. By implementing a data generating circuit to test the performance of the digital summing system, the digital summing was connected to the jig during system manufacturing. It is characterized by checking the normal operation of the machine to establish the accuracy of the shipping system.

Description

A data generator for verifying digital summator performance of a modem output for a multi-connection base station.

The present invention relates to a data generation circuit for testing the performance of a circuit that digitally sums the output of a code division multiple access (CDMA) mobile communication system base station modem. It is a sawtooth wave data generating circuit for testing a TMA (Transmission Intermediate Frequency Modulation Board Assembly).

In general, a digital adder installed in a CDMA mobile communication system sums up 16-bit digital serial data received from modems in a plurality of channel cards and generates a single data signal. Since the data is calculated by summing up the data to be transmitted, if an error occurs, the subscriber cannot receive the correct communication and a communication error occurs.

However, in the related art, since there was no means for testing the performance of the digital summing circuit for summing the output of the mobile communication system base station modem with 16-bit digital serial data, service quality and reliability could not be guaranteed.

Therefore, the present invention implements a sawtooth wave generation circuit for testing the performance of the digital summer, and when the system is manufactured, it can be connected to a jig to confirm the normal operation of the digital summer and then shipped. There is a characteristic to make.

In other words, the inventive sawtooth wave data generation circuit generates even and odd parallel digital data of 8 bits in accordance with a clock signal for generating data (a 2.4576 MHz signal generated by dividing the system clock by eight; referred to as chip × 2). A data generation unit to perform; A control unit which is a 3-bit (octal) counter for generating three octal control signals in accordance with a system clock signal (19.6608 MHz signal; hereafter referred to as chip x 16); Even data, which is an 8 × 1 data selector that receives even data and odd data, which are parallel data of 8 bits each, is converted into serial digital data of 1 bit according to the three control signals, and then generated by a digital summer. When the saw-tooth wave data generator generates 8-bit even / odd serial data, the digital summer adds the 8-bit even / odd data to 16-bit data. This is converted into an analog signal through a D / A converter (not shown) so that the sawtooth wave is detected by the oscilloscope.

Referring to the configuration of the present invention with reference to the accompanying drawings as follows.

As shown in FIG. 1, the data generator for verifying the performance of the digital summator of the modem output for the code division multiple access base station includes a data generator 10, a controller 20, an even data transmitter 30, and It is comprised by the odd data transmission part 40. FIG.

The data generator 10 receives a chip × 2 signal, which is a clock signal for data generation, and a counter reset signal indicating the start of data, and inputs even and odd parallel digital data of 8 bits for sawtooth wave generation, respectively. The even data transmitter 30 and the odd data transmitter 40 are generated.

In addition, the control unit 20 receives a chip × 16 signal used to generate data in accordance with the modem system for the mobile communication base station and a counter reset signal indicating the start of the data as an input control signal a, b, It serves to generate an octal control signal for controlling parallel data consisting of 8 bits such as c to the even data transmitter 30 and the odd data transmitter 40.

Meanwhile, the even data transmitter 30 receives 8-bit parallel even data from the data generator 10 and octal control such as control signals a, b, and c of FIG. 2 from the controller 20. When the signal is input, the 8-bit parallel even data is selected according to the octal control signal, and the 8-bit data is converted into even-bit data by one bit and then output to the digital summer.

In addition, the odd data transmitter 40 receives 8 bits of parallel odd data from the data generator 10 at the same time as the control signals a, b, and c of FIG. 2 from the controller 20. When the binary control signal is inputted, the 8-bit parallel odd data is selected according to the octal control signal, and the 8-bit data is converted into odd-numbered serial data of each bit and then output to the digital summer.

Referring to the operation of the present invention sawtooth data generating circuit configured as described above is as follows.

First, the timing diagrams of the input signal and the control signal of each block are shown for convenience of operation description. As shown in FIG. 2, when the counter reset signal 0000 _(hex) occurs, one data starts from that time. Three control signals a, b, and c in the controller 20 are (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0 (1,0,1) (1,1,0) (1,1,1) That is, the control unit 20 generates eight control signals from 0 to 7 to the even / odd data transmitters 30 and 40 so that the even / odd data transmitters 30 and 40 are octal control signals. Through 1-bit data is sequentially selected from 8-bit parallel data to output 8-bit serial data. In addition, in order to divide a total of 16-bit signals into even and odd numbers, the timings of the even data and the odd data are divided by 8 clocks of the chip × 16 clock signals in order to alternately apply the control signals without being simultaneously applied.

First, the data generator 10 receives a chip × 2 signal, which is a clock signal for data generation, and a counter reset signal indicating the start of data, and inputs even and odd parallel digital data by 8 bits for sawtooth generation, respectively. The even data transmitter 30 and the odd data transmitter 40 are generated.

In this case, the data generator 10 may be used as a triangular wave data generation circuit if the up counter and the down counter are implemented sequentially instead of using the counter only as an up counter. The signal input to the down-up terminal of the high signal should be input when the FFFF (hex) signal generation, and the low signal is input when the 0000 (hex) signal generation.

In addition, the control unit 20 receives a chip × 16 signal used to generate data in accordance with the modem system for the mobile communication base station and a counter reset signal indicating the start of the data as an input control signal a, b, An octal control signal for controlling parallel data consisting of 8 bits such as c is generated to the even data transmitter 30 and the odd data transmitter 40.

Then, the even data transmitter 30 receives 8-bit parallel even data from the data generator 10 and octal control such as control signals a, b, and c of FIG. 2 from the controller 20. After receiving the signal, the 8-bit parallel even data is converted from the 0th bit to the 7th bit (ie A ₀ , A ₂ , A ₄ , A ₆ , A ₈ , A ₁ 0 according to the octal control signal). , A ₁₂ , A ₁₄ , A ₁₆ ) selects 8 × 1 data, converts it into even serial data of 1 bit, and outputs it to the digital summer.

On the other hand, the odd data transmitter 40 receives 8-bit parallel odd data from the data generator 10 and octets such as control signals a, b, and c of FIG. 2 from the controller 20. After receiving the control signal, the 8-bit parallel odd data is written from the 0th bit to the 7th bit (ie A ₁ , A ₃ , A ₅ , A ₇ , A ₉ , A ₁₁ according to the octal control signal). , A ₁₃ , A ₁₅ , A ₁₇ ), selects 8 × 1 data, converts it into odd serial data of 1 bit, and outputs it to the digital summer.

Then, the digital summer adds even / odd digital serial data simultaneously generated by the even / odd data transmitters 30 and 40 to output 16-bit serial digital data, which is analogized by a D / A converter (not shown). Is converted into a signal.

Therefore, the operator detects the waveform of the output signal of the D / A converter through an oscilloscope to confirm whether it is a desired sawtooth wave, thereby verifying the performance of the digital summer.

In addition, when the data generator 10 uses a plurality of data transmitters 30 and 40, it is possible to perform a performance test in the case of multiple channel cards.

As described in detail above, the present invention implements a data generation circuit for testing the performance of a circuit that digitally sums the output of the base station modem for a CDMA mobile communication system, and tests the performance before shipping, thereby providing the subscriber with the quality and reliability of the service. There is a feature to guarantee.

1 is a block diagram of a data generator of the present invention,

2 is a timing diagram of the present invention sawtooth wave data generation circuit.

Explanation of symbols on the main parts of the drawings

10: data generator 20: controller

30: Even Data Transmitter 40: Odd Data Transmitter

Claims (3)

In order to verify the performance of the digital totalizer of the modem output for the coarse multiple access base station, a clock signal and a counter reset signal are generated as inputs, and an arbitrary number is counted to generate even and odd parallel digital data by 8 bits. A data generator 10; A control unit 20 which is a 3-bit (octal) counter having three control signals for receiving a system clock signal and a counter reset signal as inputs and controlling parallel data consisting of 8 bits; The 8-bit parallel even data of the data generator 10 is converted into even serial digital data of 1 bit by selecting 8 × 1 data according to a control signal transmitted from the controller 20 and then generated by the digital summer. An even-numbered data transmission unit 30; And converting 8-bit parallel odd data of the data generator 10 into 8-bit data according to a control signal transmitted from the controller 20 and converting it into odd serial digital data of one bit, and then converting it into the digital adder. A data generator for digital summator performance verification of a modem output for a code division multiple access base station, characterized in that it comprises an odd data transmitter (40) to generate. The method of claim 1, The control unit 20 verifies the performance of the digital adder of the modem output for the code division multiple access base station, characterized in that the counter reset signal is connected to the clear terminal so that the system clock signal and the counter reset signal are synchronized. Data generator. The method of claim 1, The data generator 10 may input a signal input to the down-up terminal of the counter so that a high signal is input when an FFFF (hex) signal is generated, and a 0000 (hex) signal is generated, so that the data generator 10 may be used as a triangular wave data generation circuit. A data generator for verifying the performance of a digital adder of a modem output for a code division multiple access base station, characterized in that a low signal is inputted to the base station.