KR200248167Y1 - Analog-Phase Fixed Loop with Holdover - Google Patents

Abstract

The present invention is an analog-phase locked loop (A-PLL) with a holdover function, which is the biggest advantage of the Digital Processing-Phase Lock Loop (DP-PLL) without a microprocessor and firmware. Loop, in the conventional analog-phase fixed loop, the output phase of the reference clock value is completely dependent, so that the output of the error occurs when the reference clock is out of phase and the desired output value cannot be obtained. By adding a digital-phase fixed loop, a switch, and a reference clock fault detection unit to the existing analog-phase fixed loop, the analog-phase fixed loop can be digitally eliminated without expensive microprocessors or time-consuming firmware. It is characterized by having a holdover function which is the biggest function of the process-phase lock loop.

Description

Analog-Phase Fixed Loop with Holdover

1 is a block diagram of a conventional analog-phase locked loop.

2 is a configuration block diagram of an analog-phase locked loop having a holdover function of the present invention.

* Explanation of symbols for main parts of the drawings

10: phase comparator 20: lowpass filter

30: voltage controlled oscillator 40: frequency divider

50: reference clock failure detection unit 60: switch control unit

70: digital-phase fixed loop 71: analog / digital converter

72: memory unit 73: memory control unit

74: digital / analog converter

The present invention is for a phase locked loop, in particular the hold of the biggest advantage of the Digital Processing-Phase Lock Loop (DP-PLL) without a microprocessor or firmware. This is for an analog-phase locked loop (A-PLL) with an over function.

In general, a conventional analog-phase locked loop includes a phase modulator 10 for receiving an output of a reference clock and a feed-backed frequency divider and outputting a signal that varies linearly with a phase difference, as shown in FIG. A low pass filter 20 for removing high frequency components of the phase difference output from the phase modulator; A voltage controlled oscillator 30 for outputting a different frequency according to the volt value; It is composed of a frequency divider 40 to adjust the frequency of each other in order to compare the phase of the frequency and the reference frequency output from the voltage controlled oscillator, the analog-phase fixed loop configured as described above is applied to the reference clock value supplied. Since the output phase was completely dependent, the output of the abnormality of the reference clock could not obtain the desired output value due to the wrong phase value.The digital signal with the holdover function that the output signal does not change even when the reference clock fails. Process-phase locked loops required expensive microprocessors and memory to perform holdover functions, and they took a long time to implement in firmware.

Therefore, the present invention is characterized in that the analog-phase fixed loop has a holdover function which is the largest function of the digital processing-phase fixed loop without a microprocessor or firmware.

That is, the reference clock failure detection unit for determining whether or not the reference clock in the existing analog-phase fixed loop; A switch controller which determines an input signal according to whether or not the reference clock is abnormal; A digital-phase fixed loop for holding over function is additionally configured, and the input voltage of the voltage controlled oscillator is memorized and the voltage value memorized in the case of the reference clock failure is input to the switch controller to provide a normal reference clock to provide an output clock. Keep up.

Hereinafter, an analog-phase locked loop having a holdover function according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a functional diagram of an analog-phase locked loop having a holdover function according to an embodiment of the present invention, and the analog-phase locked loop having a holdover function according to an embodiment of the present invention is a phase modulator (10). ), A lowpass filter 20, a voltage controlled oscillator 30, a frequency divider 40, a reference clock failure detector 50, a switch controller 60, and a digital-phase locked loop 70. .

The phase modulator 10 receives the output of the reference clock and the feed-backed frequency divider 40 and outputs a clock signal that varies linearly according to the phase difference to the low pass filter 20.

In addition, the lowpass filter 20 receives a clock signal output from the phase modulator 10 and removes a high frequency component, and then outputs it to the switch controller 60 and the digital-phase locked loop 70. It plays a role. In addition, the voltage controlled oscillator 30 serves to output a different frequency according to the volt value.

In addition, the frequency divider 40 serves to match the frequencies of each other to compare the phase of the frequency output from the voltage controlled oscillator 30 and the reference frequency.

In addition, the reference clock failure detection unit 50 receives a reference clock and determines whether the reference clock fails, and when the failure is detected, the control signal corresponding to the switch control unit 60 and the digital-phase fixed loop, respectively, are detected. It serves to output to 70.

In addition, the switch controller 60 receives a control signal from the reference clock failure detection unit 50 and switches to another path for outputting a normal reference clock.

The digital-phase locked loop (D-PLL) 70 receives a normal reference clock from the low pass filter 20 and stores the normal reference clock, and then, from the reference clock failure detector 50, When the control signal is input, the stored normal reference clock serves to supply the normal reference clock to the system through the switch control unit 60. As shown in FIG. 2, the analog / digital converter 71 and the memory unit 72, a memory controller 73, and a digital / analog converter 74.

The analog-to-digital converter 71 configured in the digital-phase locked loop 70 converts the phase difference value of the analog output from the low pass filter 20 into digital.

In addition, the memory unit 72 configured in the digital-phase locked loop 70 stores a phase difference value converted from the analog / digital converter 71 into a digital value.

In addition, the memory control unit 73 configured in the digital-phase locked loop 70 controls the memory unit 72 when a control signal is input from the reference clock failure detection unit 50.

In addition, the digital-to-analog converter 74 configured in the digital-phase locked loop 70 inputs a basic clock stored in the memory 72 under the control of the memory controller 73 when a reference clock failure is detected. It converts into an analog value and outputs the voltage to the voltage controlled oscillator 30 through the switch controller 60.

Referring to the operation of the analog-phase fixed loop having a holdover function as described above.

First, a case in which a normal reference clock is input will be described. The phase comparator 10 receives a signal fed back from the normal reference clock and the frequency divider 40 and compares phases with each other to compare the low pass. Output to the filter 20.

Then, the low pass filter 20 receives a normal reference clock and removes a high frequency component of the phase difference, and then, to the switch controller 60 and the analog / digital converter 71 in the digital-phase locked loop 70. Output

On the other hand, the reference clock failure detection unit 50 receives a normal reference clock input from the outside to determine the failure and outputs a control signal when the normal reference clock to the switch control unit 60 and the memory control unit 73 do.

Subsequently, when the switch control unit 60 receives a normal control signal from the reference clock fault detection unit 50, the switch control unit 60 blocks a path from which the normal reference clock is input from the digital / analog converter 74. While maintaining a path for receiving a reference clock from the low pass filter 20, a normal reference clock is received from the low pass filter 20 and output to the voltage controlled oscillator 30.

At this time, the analog-to-digital converter 71 in the digital-phase locked loop 70 changes the phase difference value of the analog reference clock digitally when the normal reference clock is input from the low pass filter 20. .

Then, the memory unit 72 receives the digital reference clock from the analog / digital converter 71, stores the digital reference clock, and outputs the digital reference clock to the digital / analog converter 74.

Subsequently, when the digital / analog converter 74 receives a normal digital reference clock from the memory unit 73, the digital / analog converter 74 converts the normal digital reference clock into a normal analog reference clock and outputs the converted analog reference clock to the switch controller 60.

On the other hand, a case in which a reference clock with a failure is input will be described. First, the phase comparator 10 receives a feed-back signal from the frequency reference 40 and the reference clock with a failure, and compares phases with each other. Output to the low pass filter (20).

Then, the lowpass filter 20 receives a reference clock with a failure and removes a high frequency component of the phase difference, and then, to the switch controller 60 and the analog / digital converter 71 in the digital-phase locked loop 70. Output On the other hand, the reference clock failure detection unit 50 receives a reference clock with a failure input from the outside to determine whether a failure, and then outputs a control signal when the failure occurs to the switch controller 60 and the memory controller 73. do.

Subsequently, when the switch control unit 60 receives a control signal when a failure occurs from the reference clock failure detection unit 50, the switch control unit 60 blocks a path for receiving a reference clock from the low pass filter 20. In order to supply a normal reference clock from the digital / analog converter 74, a path is shifted and the normal reference clock stored in the memory unit 72 is input from the digital / analog converter 74. 30).

At this time, the analog-to-digital converting unit 71 receives a reference clock with a failure from the low pass filter 20, and digitally outputs the phase difference value of the analog reference clock.

At this time, when the memory control unit 73 receives a control signal when a failure occurs from the reference clock failure detection unit 50, the reference block in which the failure is input from the low pass filter 20 corresponds to the control signal. It is blocked from being stored in the memory unit 72.

Thereafter, the memory unit 72 blocks the digital reference clock from the analog / digital converter 71 and outputs the stored normal digital reference clock to the digital / analog converter 74.

Subsequently, when the digital / analog converter 74 receives a normal digital reference clock from the memory unit 73, the digital / analog converter 74 converts the normal digital reference clock into a normal analog reference clock and outputs the converted analog reference clock to the switch controller 60.

At this time, a holdover function for inputting a normal reference clock input from the digital / analog converter 74 to a system is provided.

As described in detail above, when the failure of the reference clock is detected, the present invention receives and uses the phase difference value stored in the memory unit 72 to continue the output clock of the voltage controlled oscillator in the analog-phase fixed loop. In addition to the holdover function that allows it to be retained, the addition of simple circuitry enables the holdover function, which is an important feature of digital processing-phase locked loops without expensive microprocessors and firmware.

Claims (2)

A phase modulator 10 which receives a reference clock and a feed-back signal and outputs a reference clock that varies linearly with the phase difference; A low pass filter 20 for removing high frequency components of the reference clock output from the phase modulator, a voltage controlled oscillator 30 for outputting a different frequency according to a volt value, and a frequency and a reference frequency output from the voltage controlled oscillator In an analog-phase fixed loop composed of frequency dividers 40 that match frequencies with each other to compare a number of phases, a reference clock failure detection unit 50 for determining whether a reference clock has failed and the reference clock failure detection unit A switch controller 60 which receives an input signal by determining an input signal according to whether or not the reference clock determined at 50 is abnormal; An analog-phase locked loop having a holdover function, characterized by the addition of a Digital-Phase Lock Loop (D-PLL) 70 to enable a holdover function. 2. The digital-phase lock loop (70) according to claim 1, further comprising: an analog / digital converter (71) for converting a phase difference value of the analog output from the low pass filter (20) into digital; A memory unit 72 for storing a phase difference value converted from the analog / digital converter 71 into a digital value; A memory controller 73 controlling the memory unit 72 according to the output of the reference clock failure detector 50 and a base clock stored in the memory unit 72 under the control of the memory controller 73 when a reference clock failure is detected; The analog-phase fixed loop having a holdover function, characterized in that consisting of a digital / analog converter (74) for receiving and converting to an analog value to output to the voltage controlled oscillator (30) through the switch control unit (60).