KR200224775Y1 - multiplex clock generating board - Google Patents

Abstract

The present invention provides a synchronous clock supply unit for supplying a test synchronous clock signal to the hierarchical devices of the synchronous transmission system, and an asynchronous clock supply unit configured to supply test asynchronous clock signals to the hierarchical devices of the asynchronous transmission system. Provided is a multiple clock generation board comprising a clock supply, an oscillator for supplying a reference clock signal to the synchronous and asynchronous clock supply, and a MUX for selectively switching the output signal of the synchronous and asynchronous clock supply to an external test stair device. .

The present invention as described above is to supply all the necessary clock signal to each of the hierarchy of SDH or PDH transmission equipment developed in various types from a single clock board, each of the hierarchy of SDH or PDH system first developed Therefore, it is not necessary to manufacture a separate clock generator every time it is tested. Therefore, the manufacturing cost of the transmission system can be considerably reduced, and a clock signal synchronized with one clock board as a whole can be supplied to each developed device for testing. Therefore, it is possible to clearly carry out the characteristic test of each hierarchical device which is a part of the whole system, thus improving the reliability of the test considerably.

Description

Multiplex clock generating board

The present invention relates to a multiple clock generation board, and in particular, the clock signal required for each of the hierarchical devices of the SDH or PDH transmission equipment developed in various types By supplying all of my clock boards, multiple clock generation boards can significantly reduce the manufacturing costs of the transmission system, as there is no need to build a separate clock generator each time each hierarchy of SDH or PDH system is first developed and tested. It's about.

In general, the transmission technology began with the spiral carrier in the 1910s, developed into the analog transmission technology, and in the form of the digital transmission technology. Later, the digital transmission technology has been developed since the 1960s with the development of the DS1 channel bank with a 1.544Mbps transmission rate. It was. Moreover, such digital technology has been applied to the field of exchange technology in the mid-1970s. It has revolutionized the multiplexing of wired transmission systems by introducing the digital relay switch called 4ESS. In addition, the digital transmission method has been developed into an optical transmission method using an optical cable as a transmission medium. Currently, the digital transmission method is changing from an asynchronous PDH transmission system to a synchronous SDH transmission system.

However, such transmission systems usually include a clock generation circuit for synchronizing the signals transmitted between nodes, for example, between exchanges or within nodes. In this clock generation circuit, a phase locked loop (PLL) is usually formed. The phase locked loop is designed in an analog manner, called a PDH (PLESIOCHRONOUS DIGITAL HIERARCHY) method, while the digital synchronization method is SDH (SYNCHRONOUS) It is called DIGITAL HIERARCHY) method. Recently, a digitally designed SDH device is widely used. In the SDH device of such a transmission system, an offset detection method for offset detection of a reference clock signal input from the outside for signal synchronization is provided. It is provided with a preset detection device. Therefore, when each of the above-described devices of the SDH or PDH, such as DS1, DS2, DS3, DS4E, etc., is newly developed, a test clock generation circuit for testing is built in from the beginning or a voltage controlled oscillator (VCXO) and a PLL circuit are used. Individual clock boards are included and tested separately.

Then, referring to the conventional test clock board as described above with reference to FIG. 1, the VCXO 71 generating the main clock signal and supplying the test clock devices 70 to the test clock devices 70, and the test clock devices from the VCXO 71 ( A PLL 72 that detects a clock signal supplied to 70, compares it with an input reference clock signal, and inputs the phase difference signal to the VCXO 71; and an oscillator that supplies an input reference clock signal to the PLL 72. 73).

On the other hand, referring to the operation of the conventional clock board as described above, first, such a clock board is manufactured for the test every time the stair device of the PDH or SDH transmission system is manufactured, for example, if the manufactured stair device is DS1 clock board The VCXO 71 at 74 supplies a test signal of 1.544 MHz to the above-described fabrication device, for example, the DS1 70 for testing. At this time, the clock signal supplied to the DS1 70 is fed back by the PLL 72, and the PLL 72 receives the detected main clock signal from the 1.544 MHz input reference clock signal inputted from the oscillator 73. After comparison, the phase difference signal is input to the VCXO 71. Then, the VCXO 71 corrects the main clock signal by the input phase difference correction signal of the input PLL 72 and inputs it back to the DS1 70.

However, such a conventional clock board can be clocked separately whenever each of the hierarchy devices of the PDH or SDH transmission equipment, for example, DS1, DS2, DS3, DS4E, etc., are manufactured and tested. Since the boards had to be manufactured separately, there was a drawback that the manufacturing cost of the transmission system was significantly increased, including the manufacturing time of the clock board.

In addition, the clock board as described above is applied to each of the staircase devices constituting a system to test the clock signal produced separately, so that the synchronization of the system is not properly made accordingly the test reliability is significantly lowered There was this.

Therefore, the present invention is designed to solve the above problems, and by supplying all the clock signals individually required for each of the staircase devices of the SDH or PDH transmission equipment developed in various types, all from one clock board, SDH In addition, the purpose of the present invention is to provide a multi-clock generation board that significantly reduces the manufacturing cost of the transmission system since there is no need to manufacture a separate clock generation device each time each of the hierarchy devices of the PDH system is first developed and tested.

Another object of the present invention is to supply a test signal that is synchronized from one clock board to each of the developed devices so that the characteristics of each of the devices can be clearly tested. It is also to provide a multiple clock generation board that significantly improves.

The present invention for achieving the above object is a synchronization clock supply unit for supplying a test synchronization clock signal to the hierarchy device of the synchronous transmission system, and the synchronization clock supply unit and configured in the one of the boards of the asynchronous transmission system Experimental Asynchronous Clock A multiple clock comprising an asynchronous clock supply for supplying a call, an oscillator for supplying a reference clock signal to the synchronous and asynchronous clock supply, and a MUX for selectively switching the output signal of the synchronous and asynchronous clock supply to an external test stair device Provides a creation board.

1 is an explanatory diagram illustrating a test clock board for hierarchical devices of a conventional transmission system.

2 is a block diagram of the device of the present invention.

3 is an explanatory diagram for explaining the control of the MUX applied to the device of the present invention.

<Description of the sign>

1: Synchronous clock supply unit 2: Asynchronous clock supply unit

3: oscillator 4: mux

5: VCXO 6: first divider

7: PLL 8: 2nd divider

9: second divider 10: dip switch

11: Threshold 12: PLL

Hereinafter, the present invention will be described in detail based on the accompanying drawings.

The board of the present invention is composed of a synchronous clock supply unit (1) for supplying a test synchronous clock signal to the hierarchical devices of the synchronous transmission system, and the synchronous clock supply unit (1) and a board configured to test the hierarchical devices of the asynchronous transmission system. An asynchronous clock supply unit 2 for supplying an asynchronous clock signal, an oscillator 3 for supplying a reference clock signal to the synchronous and asynchronous clock supply units 1, 2, and an output signal of the synchronous and asynchronous clock supply unit 2; Consists of MUX (4) which selectively switches to external test stair.

The synchronous clock supply unit 1 divides the VCXO 5 that generates and supplies the main clock signal, for example, 622.080 MHz, and the main clock signal of the VCXO 5 to divide the first synchronous clock, that is, STM-1 ( 155.520 MHz) and the second synchronous clock, i.e., STM-4 (622.080 MHz), to output the first divider 6 and the first synchronous clock of the first divider 6 to feed back from the oscillator 3 A PLL 7 is compared with the supplied reference clock signal and then inputs the phase difference signal to the VCXO 5.

In addition, the asynchronous clock supply unit 2 divides the main clock signal of the VCXO 8 which generates and supplies a main clock signal, for example, 139.264 MHz, and the main clock signal of the VCXO 8 to generate a plurality of asynchronous clocks. Clock signal: first asynchronous clock DS1 (1.544 MHz), second asynchronous clock DS2 (6.312 MHz), third asynchronous clock DS3 (44.736 MHz), fourth asynchronous clock DS4E (139.264 MHz), fifth A second divider 9 for outputting asynchronous clock DS3E (34.368 MHz), a sixth asynchronous clock DS2E (8.448 MHz), and a seventh asynchronous clock DS1E (2.048 MHz), and the second divider 9 And a PLL 12 which feeds back a ninth synchronous clock, compares it with a reference clock signal supplied from the oscillator 3, and then inputs the phase difference signal to the VCXO 5.

In addition, the MUX (4) is provided with a 4-bit dip switch 10 that can adjust the output, there is an Enable terminal to adjust the output.

Here, if the MSB of the 4 bits of the dip switch 10 is '0', the output of the asynchronous clock supply unit 2 is configured so that the output of the synchronous clock supply unit 1 is selected.

The MUX 4 may be configured as a field programmable gate array (FPGA).

Next, the operation and effects of the above apparatus will be described.

In order to operate the board of the present invention, first connect the hierarchical device 11 of the manufactured PDH or SDH transmission system to the output terminal of the MUX (4), and then apply a 'high signal' to the enable terminal of the MUX (4) The position 10 is used to select the clock signal of the hierarchy 11 as shown in FIG. 3.

For example, if the STM-1 of the PDH system is connected to the MUX 4, the selection value of the dip switch 10 is set to '1000'. If the DS4E of the SDH system is connected, the '0011' is set and set up. Give it.

Then, the VCXO 5 of the synchronous clock supply unit 1 provided in the multi-clock board of the present invention generates a clock signal of 622 MHz and inputs it to the first divider 6. Therefore, the first divider 6 divides the main clock signal of the input VCXO 5 to divide the first synchronous clock, that is, STM-1 (155.520 MHz) and the second synchronous clock, that is, STM-4 (622.080 MHz). To MUX (4). At this time, the PLL 7 feeds back the first synchronous clock of the first divider 6 divided by a quarter of the main clock signal, compares it with the reference clock signal supplied from the oscillator 3, and then phase difference the signal. Is corrected by inputting to VCXO (5).

At the same time, the VCXO 8 of the asynchronous clock supply unit 2 also generates a clock signal of 139.264 MHz and inputs it to the second divider 9. Accordingly, the second divider 9 divides the main clock signal of the input VCXO85, thereby providing a plurality of asynchronous clock signals, that is, a first asynchronous clock DS1 (1.544 MHz) and a second asynchronous clock DS2 (6.312 MHz). , Third asynchronous clock DS3 (44.736 MHz), fourth asynchronous clock DS4E (139.264 MHz), fifth asynchronous clock DS3E (34.368 MHz), sixth asynchronous clock DS2E (8.448 MHz), seventh asynchronous clock in Input to MUX (4) with DS1E (2.048MHz). At this time, the PLL 12 feeds back the seventh asynchronous clock of the second divider 9 having the main clock signal divided by 1/64 and compares it with the reference clock signal supplied from the oscillator 3, and then the phase difference signal. Is corrected by inputting to VCXO (8).

Accordingly, two types of synchronous clock signals and seven types of asynchronous clock signals are input to the MUX 4, where a selection stage of the MUX 4 is set to a '1000' value indicating the connection of the STM-1 of the PDH system. When set, the MUX 4 is a clock of 155.520 MHz, the clock signal of STM-1. The ruck signal is supplied to STM-1, which is the test stair device 11, to perform a normal test.

At this time, if the selection terminal of the MUX (4) is set to the value '0011' indicating the connection of the DS4E of the SDH system, the MUX (4) is a test signal for the test signal 139.264MHz clock signal of the DS4E 11 It supplies to phosphorus STM-1 and performs a normal test.

Therefore, if the 4-bit selection terminal of the MUX 4 is controlled as shown in FIG. 3 through the above process, the clocks of the hierarchy devices of various asynchronous or synchronous transmission systems can be supplied to one board.

As described in the above description, the present invention is to supply all the necessary clock signals to the respective devices of the SDH or PDH transmission equipment developed in various types from one clock board, so that each of the devices of the SDH or PDH system Each time it is developed and tested, it is not necessary to manufacture a separate clock generator, which has the advantage of significantly reducing the manufacturing cost of the transmission system.

In addition, according to the present invention, since the clock signal synchronized with one clock board as a whole is supplied to each developing device to be tested, it is possible to clearly perform the characteristic test of each of the device as a part of the whole system. It also has the effect of significantly improving reliability.

Claims (3)

A synchronous clock supply unit for supplying a test synchronous clock signal to the hierarchical devices of the synchronous transmission system; a synchronous clock supply unit configured to supply the test asynchronous clock signal to the hierarchical devices of the asynchronous transmission system; And an oscillator for supplying a reference clock signal to the synchronous and asynchronous clock supplies, and a MUX for selectively switching an output signal of the synchronous and asynchronous clock supplies to an external test stair device. The synchronous clock supply unit according to claim 1, wherein the synchronous clock supply unit generates a main clock signal and supplies the VCXO, a first divider which divides the main clock signal of the VCXO and outputs the first clock signal to the first synchronous clock and the second synchronous clock; And a PLL which feeds back the first synchronous clock of the first divider, compares it with a reference clock signal supplied from the oscillator, and inputs the phase difference signal to the VCXO. The VCXO of claim 1, wherein the asynchronous clock supply unit generates and supplies a main clock signal, a second divider that divides the main clock signal of the VCXO into a plurality of asynchronous clock signals, and the second divider. And a PLL which feeds back a synchronous clock of the signal, compares it with a reference clock signal supplied from the oscillator, and inputs the phase difference signal to the VCXO.