KR20020091848A - Turbo interleaving apparatus and method in cdma mobile communication system having turbo code - Google Patents

Abstract

PURPOSE: An apparatus and a method for turbo interleaving of a CDMA mobile communication system using a turbo code are provided to reduce a hardware process delay by improving a structure of a turbo interleaving apparatus. CONSTITUTION: An intra-row permutation portion(300) is formed with a buffer(301) for updating a row address value, a base sequence portion(303) for exchanging a row address within a row, a reduced q generation portion(305) for outputting a reduction q valve, an adder(307) for adding the reduced q value to the row address of the buffer(301), a comparator(309) for comparing an output value A of the adder(307) with a value of B of p-1, a multiplexer(313) for selecting one of 0 and the value of p-1, and a subtracter(311) for subtracting an output value of the multiplexer(313) from the value of A. An inter-row permutation portion(320) is formed with a multiplexer(321) for outputting one of a base sequence value, 0,1, and the value of p, an adder(323) for adding output values of the multiplexers(321), and a multiplied_PIP generation portion(325) for outputting selectively multiplied_PIP values. A pruning portion(330) is used for comparing a size of interleaver index with a size of interleaver and outputting a smaller value.

Description

Turbo interleaving apparatus and method for code division multiple access mobile communication system using turbo code {TURBO INTERLEAVING APPARATUS AND METHOD IN CDMA MOBILE COMMUNICATION SYSTEM HAVING TURBO CODE}

The present invention relates to a turbo interleaver and an interleaving method of a code division multiple access mobile communication system, and more particularly, to a turbo interleaver and an interleaving method capable of reducing processing delay.

In general, a digital communication system uses a channel coder such as Viterbi, a turbo coder, etc. to effectively remove noise generated in a transmission channel. The turbo coder consists of two encoders and one turbo interleaver. The turbo interleaver is a component added to maximize turbo coding performance and generates an interleaver address as large as the size of the interleaver. A prime interleaver (PIL) is used as the turbo interleaver. The PIL is based on a 2-dimensional matrix permutation operation, and when the interleaver index becomes larger than the turbo interleaver size through a pruning operation, there is an additional operation of puncturing. In other words, if the turbo interleaver size is K, the interleaving index is larger than K, which means that the index can be ignored.

The secondary matrix exchange consists of intra-raw permutation and inter-row permutation. The inter-row exchange is to exchange respective values in one row, and the inter-row exchange is to perform exchange on a row basis. In order to perform the inter-row and inter-row exchange, a plurality of parameters are required. In other words, the parameter must be set first before the exchange can be performed.

Hereinafter, parameters for in-row exchange and inter-line exchange are defined and described in three stages of operation.

In the first step, since PIL is a secondary matrix structure, the row (Row: "R") value corresponding to the turbo interleaver size K is obtained according to Table 1 below. Decimal value) and column value are obtained by the following equation.

TABLE 1

K R 40 <= K <159 5 160 <= K <200 10 201 <= K <480 20 481 <= K <530 10 531 <= K <5114 20

[Equation 1]

if (481 <= K <530) then p = 53 and C = p,

else

find minimum prime p such that (p + 1) -K / R> = 0,

and determine C such that

if (p-K / R> = 0) then

if (p-1-K / R)> = 0 then

C = P-1

else

C = p

end if

else

C = p + 1

end if

In Equation 1, p has one of 74 values of 7, 19, 23,... 251, and 257 depending on the value of K.

FIG. 1 is a diagram showing the size of an interleaver. FIG. 1A shows that the size of an interleaver is determined by a column value C and a row value R, and FIG. 1C shows that the interleaver index is read from the left to the top when reading the interleaver index. In FIG. 1, it can be seen that the size of the interleaver is determined as R * C.

When the R, C, and p parameters are determined by Table 1 and Equation 1, the primitive root value corresponding to each p value (hereinafter, referred to as "g0") is given in Table 3 below. You can find out the value one-to-one.

TABLE 2

In the second step, in-row exchange is first performed by the g0 and p values defined in the first step. In order to perform the in-row exchange, a base sequence must first be created. The base sequence is a result of exchanging a value from 0 to (p-1) by Equation 2 below.

[Equation 2]

c (0) = 1

c (i) = [g0 * c (i-1)] mod p (i = 1, 2, .., p-2)

The generated base sequence is used as a lookup table of exchanges for R rows. In order to perform the intra-row exchange from the first to the R-th row, the value of (p-1) and the q value required for each row are additionally required. The q value is a value for determining the exchange pattern. The q value of {1, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89} In a set of 21 elements, (R-1) numbers are selected without duplication. The method selected is selected in equation (3) below.

[Equation 3]

G.C.D {q (j), P-1} = 1, q (j)> 6, and q (j)> q (j-1), q (0) = 1

G.C.D stands for Greatest Common Divisor.

Q (j) is {1, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89 } 19 or 9 or 5 columns of} are specified without duplication. The value of q (j) does not satisfy any condition [GCD {q (j), p-1} = 1] of which two values of 21 values are to be excluded or excludes the rest when R-1 is selected. do. The q (j) value is replaced by the q (j) value according to the value of K using Tables 3 and 4 below.

TABLE 3

TABLE 4

Each intra-row exchange is made by Equation 4 below.

[Equation 4]

When C = p-1,

At j-th row, (j = 0, 1, 2, .., R-1)

C _j (i) = C ([i * q (j)] mod (p-1) (i = 1, 2, ..., p-2)

When C = P,

At j-th row, (j = 0, 1, 2, ..., R-1)

C _j (i) = C ([i * q (j))] mod (p-1) (i = 1,2, ..., p-2), C _j (p-1) = 0

When C = p + 1,

At j-th row, (j = 0, 1, 2, ..., R-1)

C _j (i) = C ([i * q (j))] mod (p-1) (i = 1,2, ..., p-2), C _j (p-1) = 0, C _j (p) = p

Equation 4 represents in-row exchange in the j-th row in the case where C is p-1, p or p + 1, and when C is p-1, only in-row exchange is performed, and C is If p, insert 0 into the last column of the row after performing an in-row exchange; if C is p + 1, insert 0 into the last second column of the row and insert into 0 the last column Indicates that the p value is to be inserted. Inserting 0 or / and p is to fill the remaining columns in the row when the C value is p or p + 1.

2 is a flowchart illustrating the operation of a general turbo interleaver. Hereinafter, an operation of a general turbo interleaver will be described with reference to FIG. 2.

First, if the size K of the turbo interleaver is determined in step 200, the parameters of the turbo interleaver are initialized in step 210. The initialization of the parameter consists of step 203 of finding parameters for the given K and generating a base sequence, and step 205 of generating the base sequence. Specifically, the initialization step 203 finds R, C, and p corresponding to the K value by using the given K and Equation 1. At this time, the additional parameter to be found is g0 obtained by Table 2 above. If the parameters are found, in step 205, the obtained parameters are applied to Equation 2 to generate a base sequence.

If the base sequence is generated in step 205, the process proceeds to step 220 to perform in-row exchange. In the step 220 of row exchange, step 221 of performing a modulo operation and a step 223 of storing a base sequence generated by the modulo in a register and performing an in-row exchange using the stored base sequence as a lookup table. It consists of. If the row exchange is performed in step 220, the row exchange is performed in step 230, and the flow proceeds to step 240 to perform a pruning operation. In other words, it is determined whether the interleaver index that has been exchanged between the rows is larger than the interleaver size, and if the interleaver index is smaller than the interleaver size, the controller proceeds to step 260 to output the turbo interleaver index. Perform interline exchange again. This operation is performed repeatedly until all interleaver indexes are output.

As described above, there is a problem in that a processing delay of hardware that performs calculations for intra-row exchange and inter-row exchange in order to perform turbo interleaving is very large. Specifically, a large delay is caused by modulo operation. In Equation 4, if [i * q (j)] mod (p-1) of C _j (i) = C ([i * q (j)] mod (p-1)) is A (i) C _j (i) = C (A (i)). And C () is a lookup table. Looking at A (i), the value of i * q is the number of intervals of values from 0 to 255 * 89, and the value of p-1 is the number of intervals from 0 to 256 sections. The I value is increased by one each time one turbo interleaver index is generated. That is, a problem arises because multiplication is necessary to find A (i) and the result of the multiplication is relatively large. In general, the larger the values of a and b in the modulo operation (a) mod (b), the greater the hardware processing delay.

Accordingly, an object of the present invention is to provide a turbo interleaver and a method thereof having low hardware processing delay in a mobile communication system using a turbo interleaver.

An object of the present invention is to provide an interline exchange apparatus and method of a turbo interleaver that can reduce hardware processing delay in a mobile communication system using a turbo interleaver.

In order to achieve the above object of the present invention, the present invention provides a turbo interleaver in a code division multiple access mobile communication system in which a parameter queue (q) value for performing intra-row exchange of interleaver indexes during turbo interleaving is reduced. When the inter-row exchanger performing the inter-exchange, the inter-interchange exchanger interchanging the interleaver index exchanged in the row, and the size of the interleaver index and the interleaver size at which the intra-interchange and inter-line exchange are performed are small. It is characterized by consisting of a pruning unit for outputting only.

In order to achieve another object of the present invention, the present invention provides a turbo interleaving method for a code division multiple access mobile communication system, in which a parameter queue (q) value for performing intra-row exchange of interleaver indexes during turbo interleaving is reduced. Intra-row exchange process for performing inter-exchange, inter-role exchange process for interchanging the interleaver index exchanged in the row, and interleaver index and interleaver size for performing inter-row exchange and inter-row exchange are small by comparing It is characterized by consisting of a pruning process that only outputs.

1A is a diagram showing the size of a turbo interleaver in a code division multiple access mobile communication system using a general turbo code.

1B is a diagram showing a recording method in a turbo interleaver in a code division multiple access mobile communication system using a general turbo code;

1C is a diagram illustrating a reading method in a turbo interleaver in a code division multiple access mobile communication system using a general turbo code.

2 is a flowchart illustrating a method of performing an exchange in a turbo interleaver of a code division multiple access mobile communication system using a general turbo code;

3 is a diagram illustrating a configuration of a turbo interleaver in a code division multiple access mobile communication system using a turbo code according to a first embodiment of the present invention.

4 is a diagram illustrating a configuration of a reduction q generation unit of a turbo interleaver of a code division multiple access mobile communication system using a turbo code according to an embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a base sequence generator of a turbo interleaver of a code division multiple access mobile communication system using a turbo code according to the present invention; FIG.

6 is a diagram showing the configuration of a multiplied_PIP generation unit of a turbo interleaver of a code division multiple access mobile communication system using a turbo code according to the present invention;

7 is a diagram showing the configuration of a turbo interleaver in a code division multiple access mobile communication system using a turbo code according to the first embodiment of the present invention.

Fig. 8 is a diagram showing the configuration of a selection signal generator of a turbo interleaver in a code division multiple access mobile communication system using a turbo code according to the present invention.

9 is a diagram showing the configuration of a change mode signal generator of a turbo interleaver in a code division multiple access mobile communication system using a turbo code according to the present invention;

10 is a flowchart illustrating an interleaving method of a turbo interleaver in a code division multiple access mobile communication system using a turbo code according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding the reference numerals to the components of each drawing, the same components have the same reference numerals as much as possible even if displayed on different drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

3 is a diagram illustrating a configuration of an interleaver according to the first embodiment of the present invention. In the following description of the present invention, a row address indicates a row address, a column address indicates a column address, and a count address is an address whose address is increased by one, and is generated by a general address generation algorithm. do.

In FIG. 3, reference numeral 300 is an in-row exchanger, 320 is an inter-row exchanger, and 330 is a pruning unit. The row exchange unit 300 has a value of '0' as an initial value, receives a row address, outputs a value of the row address, receives a predetermined value, and updates a value of the row address. And a base sequence unit 303 having a base sequence determined by the parameter and outputting an intra-row exchange by the base sequence upon inputting the buffered row address, and a Reduce_q value for the input row addresses. A reduction q generating unit 305 having a table having a plurality of rows and receiving the row address and outputting a decrease queue value corresponding to the row address, and a row address and the reduction q output from the buffer 301. An adder 307 that receives and adds the Reduce_q value output from the generation unit 305, and a value B that has a value of A and p-1 output from the adder 307. A comparator 309 that outputs a value of '0' when A is less than or equal to B and a value of '1' when A is greater than B, and a value of p-1 and a value of '0'. A multiplexer 313 (M1) for selecting one of p-1 or '0' and a value of A input from the adder 307; A subtractor 311 subtracts the value output from the firearm 313 and outputs the result to the buffer 301.

The q reduction unit 305 may have Reduce_q values for each address previously input as described above, and includes a table defining q and p values as shown in Table 5 below. It can also be calculated directly by However, in the present invention, since table operation can reduce the amount of calculation, the table is configured.

reduced_q = (q) mod (p-1)

Q is a value defined in Table 4 above, and p is a parameter for performing the exchange.

For example, if the p value is 17 and the q value is 71, then reduced_q = (71) mod (17) = 7. The reason why the q value can be reduced by performing a modulo operation in Equation 5 is as follows.

If C _j (i) = C ([i * q (j)] mod (p-1) = c (A (i, j))) in Equation 4, Equation 6 can be derived. It can be seen that.

A (i, j) = (i * q (j)) mod (p-1)

= (q (0) + q (1) + .... + q (j)) mod (p-1)

= [q (j) mod (p-1) + (q (j)) mod (p-1) + ... + q (j) mod (p-1)] mod (p-1)

= [A (i-1, j) + (q (j)) mod (p-1)] mod (p-1)

= [A (i-1, j) + reduced_q (j)] mod (p-1)

In Equation 6, reduced_q has a value from 0 to (p-2). Since A (i-1, j) is an ignition type, it has a value from 0 to (p-2). In order to make A (i, j) have a value from 0 to (p-2), Equation 6 may be divided into two cases as follows.

The first is when A (i-1, j) + reduced_q (j) is less than (p-1), and the second is when A (i-1, j) + reduced_q (j) is less than (p-1). Equal or greater.

In the first case, A (i, j) is A (i-1, j) + reduced_q (j) by the characteristics of the modulo operation, and in the second case, A (i, j) Is A (i-1, j) + reduced_q (j)-(p-1).

Table 6 below defines addresses and parameters corresponding to the addresses, that is, a p value and a g0 value when the selection signal is 0, and corresponds to the parameters defined in the addresses and the addresses, respectively. Reduced_q values are shown. If the selection signal is 1, use R10 in Table 7.

The reduction q generating unit 305 has the table shown in Table 6 above. 4 is a diagram illustrating a detailed configuration of the reduction q generation unit 305. Hereinafter, a detailed configuration and operation of the reduction q generation unit 305 will be described with reference to FIG.

address p G_0 R10 N / A 53 2 1, 7, 11, 19, 23, 29, 31, 37, 41

The reduction q generator 305 stores the p value storage unit 501, the comparator 503, the first switch 504, the second switch 506, and the g_0 value in the storage unit 505 and the Reduced_q value storage unit ( 507, an R10 storage unit 509, a multiplexer 511, and a reduction q register unit 513. The p value storage unit 501 has a table having p values corresponding to each of the addresses, receives an address, and outputs a p value for the address. The comparator 503 receives and compares the p-value output from the P-value storage unit 501 with a reference value. If the p value is X and the reference value is Y, the comparator 503 compares whether X is equal to or greater than Y. If X is equal to or greater than Y, the first switch 504 is connected to the upper end to output the p value, and the second switch 506 is connected to the lower end to convert the address count value into the g_0 storage unit 505 and reduced_q. Output to storage 507, but if X is less than Y, the address count is incremented by one. The g_0 storage unit 505 has a table having a g_0 value for each of the address count values, and outputs a g_0 value corresponding to the address count value when an address count is input through the second switch 506. . The reduced_q value storage unit 507 has a table having a reduced_q value corresponding to each of the address count values. When the address count value is input through the second switch unit 506, the reduced_q value storage unit 507 corresponds to the address count value. Print the value. The R10 storage unit 509 stores a fixed R value and outputs a fixed R value. The R value is 10 in the present invention, and the interleaver size K is 160 <K <200. This means that even though R = 10, there may be a K value in which R10 is not used and a reduced_q value is used. The multiplexer 511 receives a selection signal and selects one of the reduced_q value and the R value from the reduced_q storage unit 507 and the R10 storage unit 509 and stores the selected value in the reduced q register 513.

In FIG. 3, the base sequence generator 303 includes a multiplexer 401, a multiplier 403, a modulo operator 405, and a base sequence register 407. The multiplexer 401 receives a value of 1 and a predetermined feedback value, selects and outputs the 1 or feedback value by a reset signal. Specifically, if the reset signal is the enable signal, the value of 1 is selected and output, and if the disable signal, the feedback value is output. The output of the multiplexer 401 is input to the multiplier 403. The multiplier 403 multiplies the output of the multiplexer 401 by the value of g_0 and outputs the result to the modulo calculating unit 405. The modulo operation unit 405 receives the output value and the p value of the multiplier 403, performs an operation according to Equation 2 with the p value as an argument, and outputs the operation result. The operation result value is a base sequence. The base sequence is fed back to the multiplexer 401 and input to the base sequence register 407. The base sequence register 407 stores the base sequence and multiplies the value input from the buffer 301 by the value of the count address. In-row exchange is achieved by multiplying the base sequence by the count value as above. The address count value is a value input from the buffer of FIG. 3 and increments by one after the base sequence value is stored. The base sequence register 407, that is, the base sequence output from the base sequence generator 303 of FIG. 3, is input to the interline exchange unit 320.

The interline exchange unit 320 includes a multiplexer 321, an adder 323, and a multiplied_PIP generation unit 325. The multiplexer 321 receives a base sequence output from the base sequence generator 303 and 0, 1, and p values, receives a 2-bit selection signal, and receives one of the base sequence, 0, 1, and p values. Select to print. The multiplexer 321 receives a selection signal according to the condition of Equation 4 and selects one of the values. This is because the base sequence may not fill each row according to the C value. As shown in Equation 4, when C has a value of p-1, 1 is selected in the first column of the row, and in the subsequent column, the value of the base sequence is selected and output, and when C is p, Since there is one last column of each row than when C is p-1, a value of 0 is selected and output from the last column of each row. When C is p + 1, since the last column of each row remains than when C is p + 1, the value of p is selected and output to fill the last column of each row with p.

The value output from the multiplexer 321 is input to the adder 323. The multiplied_PIP generation unit 325 receives a row address and multiplied_PIP by the selection signals A, B, C, and D (hereinafter, expressed as "0", "1", "2", and "3"). Select and print the value.

5 is a diagram illustrating a detailed configuration of the multiplied_PIP generation unit 325. Hereinafter, a detailed description will be given with reference to FIG. 5.

The multiplied_PIP 325 includes a PIP storage unit 601, a multiplier 603, a subtractor 605, and a multiplied_PIP register 607 for storing PIP values for each selection signal.

The PIP storage unit 601 receives a selection signal and a read address counter value and reads a PIP value of the selection signal from the read address counter position. The multiplier 603 receives the output value of the PIP storage unit 601 and multiplies the C value by the output value. The adder 605 receives an output value of the multiplier 603 and a negative mode value, and subtracts the output value to a mode value to output the result. The negative mode value is a value output by the C value and the p-1 value and outputs 1 when the C value and the p-1 value are the same and 0 when the value is different.

The output value of the subtractor 605 is input to the multiplied_PIP register 607, and the multiplied_PIP 607 receives a write address count value and a read address row value, and the subtractor 605 of the subtractor 605 at the position of the write address count value. When the read value is stored and the read address row value is input, the PIP value is read from the read address row value position and output to the adder 323 of FIG.

The adder 323 of FIG. 3 adds and outputs the output value of the multiplexer 321 of FIG. 3 and the multiplied_PIP value. The pruning unit 331 outputs the output value of the adder when the output value of the adder 323 is smaller than the interleaver size K, and does not output the output value of the adder 323.

FIG. 7 is a diagram illustrating a structure of an interleaver according to a second embodiment of the present invention, in which only the configuration of the in-row exchanger 300 of FIG. 3 is configured differently. According to the second exemplary embodiment, only the positions of the comparator 703, the multiplexer 705, and the subtractor 707 are changed.

8 is a diagram illustrating a selection signal generator for generating a selection signal input to the multiplexer 321 of FIG. 3 and the multiplexer 713 of FIG.

The row and column of Fig. 8 are the values of the rows and columns of the two-dimensional matrix. The change mode (exchange_mode) is a signal required for changing the equation (4).

The comparator 801 compares whether the column is equal to 0 and outputs a value of 1 if it is the same and a value of 0 if it is different. The comparator 305 compares whether the row value is equal to the value of 0 and outputs a value of 1 if it is the same and a value of 0 if it is different. The comparator 809 compares whether the column value and the value of p are equal, and outputs a value of 1 if they are equal and a value of 0 if they are different. The comparator 813 compares whether the column value is equal to the value of p-1, outputs a value of 1 if it is the same, and outputs a value of 0 if it is different. The AND gate 803 receives and outputs the output values and the change mode values of the comparator 801 and the comparator 805, and outputs them. The AND gate 807 receives and outputs the output values and the change mode values of the comparator 805 and the comparator 809 and outputs them. The AND gate 811 AND gates and outputs the output value of the AND gate 807 and the output value of the comparator 809. An output of the AND gate 803, an output of the AND gate 807, an output of the AND gate 811, and an output value of the comparator 813 become selection signals. For example, if the column and row are zero and in change mode, then P is output. If the column is p, the row is 0, and the change mode, the value 1 is output. If the column is p and not in change mode or the row value is nonzero, the value of p is displayed. If the column is p-1, then 0 is printed. This may be shown in Table 8 below.

select (abcd) output 0000 Bass sequence 1000 p 0100 One 0010 p 0001 0

9 shows the configuration of a change mode signal generator 329 for generating a change mode value input to the selection signal generator 327. FIG.

The change mode signal generator 329 compares the multiplier 901 for multiplying the R value and the C value, and compares the output value of the multiplier 901 with the interleaver size K, and outputs 1 when it is the same and 0 when it is different. A comparator 903 and a comparator 905 and a comparator 903 and a comparator 905 which input values of C and p + 1 are compared and compare the same and output a value of 1 if they are equal, and a value of 0 if they are different. The AND gate 907 receives and outputs an output value of and outputs a change mode signal.

10 is a flowchart illustrating an interleaving method performed by the components according to the first and second embodiments of the present invention.

In FIG. 10, steps 1001, 1003, and 1005 correspond to steps 200 and 203 of FIG. 2. That is, the process of finding a parameter applied according to the present invention. When the parameters are determined in steps 1001, 1003, and 1005, it is determined in step 1005 whether the current mode is a negative mode based on the determined C and p-1 values. That is, when the C value is equal to the p-1 value, it is determined as a minus mode. If it is determined whether the mode is in the negative mode, a multiplied_PIP is generated in step 1009. When the multiplied_PIP is generated, the process proceeds to step 1013 to obtain a reduced_q value by using the parameter p value and g_0 value, and generates a base sequence in step 1015. When the base sequence is generated, the process proceeds to step 1017 to perform in-row exchange by the reduced_q value, and performs inter-line exchange by the base sequence. After the exchange is performed, pruning is performed and ends.

The above-described process will be described with an example as follows.

First, the interleaver size K is 321, and R = 20, C = 17, and P = 17 are determined by Equation 1 and Table 1 above.

Secondly, since p is 17, g_0 is 3 from the table in Table 2. Therefore, substituting the g_0 and p values into Equation 2 is represented by Equation 7 below, and the base sequence is represented by Table 9.

c (0) = 1

c (i) = [3 * c (i-1)] mod 17

i 0 One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C (i) One 3 9 10 13 5 15 11 16 14 8 7 4 12 2 6

The base sequence q _j is determined as shown in Table 10 below under the condition of Equation 3.

j 0 One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 q (j) One 7 11 13 17 19 23 29 31 37 41 43 47 53 59 61 67 71 73 79

When generated base_q is generated using Equation 5 as shown in Table 10, it is represented as shown in Table 11 below.

j 0 One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Reduced_q (j) One 7 11 13 One 3 7 13 15 5 9 11 15 5 11 13 3 7 9 15

In the case of C = p, if In-row permutation is substituted for the base sequence having the reduced_q (j) into Equation 4, cj (i) = c ([ixq (j)] mod (16)) (i = 1 (2, 15) and cj (16) = 0, in-row exchange is performed as shown in Table 12 below.

Third, when K = 321, if the exchange pattern is type A, interleaver index is generated as shown in Table 13 below when inter-row permutation = row-address offset permutation is performed (the generated interleaver index value is The value after adding the offset value to each row is displayed, for example, since C = 17, the first line of A is 19 in the first line, so 19 * 17 = 323 is added to the above value, and in the second line A Since the second value of is 9, 9 * 17 = 153 is added as follows). If you read the next table as a column by column and get a number larger than K-1 (since index is created from 0), ignore it and read the following.

154,239,69,?, 164,245,?., 255,187

A = {19,9,14,4,0,2,5,7,12,18,10,8,13,17,3,1,16,6,15,11}

Compare Case By Case

The following is divided into C = p + 1 (Case-A), C = P (Case-B) and C = P-1 (Case-C) when the R and p values are the same. Is a comparison.

As described above, the present invention has the advantage of reducing the processing delay by reducing the amount of modulo operation when performing the interleaving of the turbine.

Claims (6)

A turbo interleaver in a code division multiple access mobile communication system, An intra-row exchanger for performing intra-row exchange by decreasing a parameter queue q for performing intra-row exchange of interleaver indexes when performing turbo interleaving; An interline exchange unit for interchanging the interleaver indexes exchanged in the row with each other; And a pruning unit configured to compare the size of the interleaver index on which the intra-row exchange and the inter-row exchange is performed with the size of the interleaver, and to output only a small case. According to claim 1, wherein the in-row exchange unit, A buffer having an initial value, receiving a row address, outputting an initial value corresponding to the row address, and receiving a predetermined value and storing the initial value at the row address for updating the initial value; A base sequence generator for generating a base sequence, multiplying a value of the base sequence addressed to an output value of the buffer, and outputting the interleaver index to a value exchanged in a row; A decrement queue generating unit generating the dequeue queue values by applying queue q values according to a predetermined equation, and outputting decrement queue values corresponding to the row addresses when inputted to the row addresses; An adder for adding and outputting the decrement queue value output from the dequeue queue generator and an output value of the buffer; A comparator for comparing the added value with a parameter p-1 required for exchange and outputting a selection signal; A multiplexer configured to receive a value of 0 and the p-1, receive the selection signal, and selectively output the 0 or p-1 value; And a subtractor for subtracting the added value to an output value of the multiplexer and outputting the row address to the buffer to update the row address value. The apparatus as claimed in claim 2, wherein the equation is the following equation (8). reduced_q = (q) mod (p-1) The method of claim 2, wherein the decay queue generating unit, A P value storage unit for storing P values for each of the addresses and outputting P values of addresses corresponding to the row addresses; A comparator configured to receive a p value and a reference value output from the P value storage unit and compare whether the p value is equal to or greater than the reference value; A first switch switched by the output value of the comparator and outputting the p value; A second switch which is switched by an output value of the comparator to switch and output the row address; A g_0 value storage unit which stores g_0 values for each address, and outputs a g_0 value corresponding to the switched input row address; A decrement queue value storage unit which stores decrement queues for each address and outputs decrement queue values corresponding to the row addresses; An R10 storage unit which stores fixed R values and outputs them sequentially; A multiplexer configured to receive an output value of the R10 storage unit and an output value output to the decrease queue value storage unit, and receive and output a predetermined selection signal; And a decay queue register for storing an output value of the multiplexer. In a turbo interleaving method of a code division multiple access mobile communication system, An intra-row exchange process for performing inter-row exchange by reducing a parameter queue q for performing inter-row exchange of interleaver indexes when performing turbo interleaving; An inter-row exchange process of inter-exchanging the interleaved indexes exchanged in the rows; And a pruning process of comparing the size of the interleaver index and the size of the interleaver in which the intra-row exchange and the inter-row exchange are performed, and outputting only a small case. The method of claim 5, wherein the in-row exchange process, Finding the parameters p and g_0 required for in-row exchange, Generating a reduced queue (Reduced_q) value by using the parameter p value, g_0 value, and Equation 9 below; Generating a base sequence by the decrement queue; And performing in-row exchange by the base sequence. reduced_q = (q) mod (p-1)