KR20020088651A - Refresh circuit in sram using dram cell - Google Patents

Abstract

PURPOSE: A refresh circuit of an SRAM compatible memory device using a DRAM cell is provided to access a DRAM cell two or more times during an SRAM access block of one period. CONSTITUTION: A refresh circuit(311) receives a reserved mode signal(RSV) from a reserved block decision circuit(309) and an access control signal(ACC) from an access block decision circuit(313). The refresh circuit(311) generates a refresh driving signal(RFH), an access progressive signal(PFRSVP), and an inner counter driving signal(RFACT) to the access block decision circuit(313). A DRAM memory cell of a memory cell array(317) is refreshed when the refresh driving signal(RFH) is activated. The refresh circuit(311) generates a counting signal(ACNT) to a decoder(315). The reserved block decision circuit(309) generates a reserved mode signal according to an address sense signal(ATDPSB). The access block decision circuit(313) generates a low active signal(ACT) and the access control signal(ACC). A CS buffer(301) generates an inner chip selection signal(CS). A power-up generation circuit(304) generates a power-up signal. A WE buffer(305) generates an inner write enable signal(WE). An address signal buffer and ATD circuit(303) generates an inner address signal(INADD) and the address sense signal(ATDPSB). A data signal buffer and DTD circuit(307) generates an inner data signal(INDATA) and a data sense signal(DTDPSB).

Description

Refresh circuit of an SRAM-compatible memory device using DRAM cells {REFRESH CIRCUIT IN SRAM USING DRAM CELL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a refresh circuit of a static random access memory (SRAM) using a dynamic random access memory (DRAM) cell.

Random Access Memory (RAM) in a semiconductor memory device may be classified into an SRAM and a DRAM. A typical SRAM unit memory cell for storing one bit of information is implemented with four transistors forming a latch structure and two transistors serving as transfer gates. That is, since the conventional SRAM stores data signals in unit memory cells having a latch structure, a refresh operation for preserving the data signals is not required. In addition, compared to DRAM, SRAM has advantages of high operating speed and low power consumption.

However, since the SRAM unit memory cell is implemented with six transistors, the area required for layout is larger than that of the DRAM unit memory cell implemented with one transistor and one capacitor. That is, the layout area of the SRAM required to manufacture the memory device having the same capacity is about 6 to 10 times the layout area of the DRAM.

In order to overcome the drawbacks of DRAM and SRAM as described above, efforts have been made to implement SRAM using DRAM cells. One such effort is the "Applicant of the asynchronous SRAM compatible memory device using a DRAM cell and a method of driving the same" filed by the applicant of the Korean Patent Office (Patent Application No.:10-2000-0072815). According to the technology described in the Korean patent application, the DRAM cell may be accessed two or more times during the SRAM access period of one cycle. That is, as illustrated in FIGS. 1 and 2, a data signal may be input and output to and from a standby section and a DRAM cell having a time longer than a time required for performing a refresh operation during an SRAM access section of one cycle. A DRAM access section, that is, a read section or a write section, is assigned. Here, / CS denotes an external chip select signal for selecting an SRAM compatible memory device, ADDR denotes an external address signal input from the outside, / WE denotes a write enable signal that enables a write operation, and IO denotes a data signal. Indicates the input / output status. In addition, S_tRC represents the access cycle of the SRAM observed in the external state, and D_tRC represents the access cycle of the actual DRAM in the semiconductor memory device. 1 and 2 also show an operating state of a DRAM cell used in an SRAM compatible memory. As such, the semiconductor memory device according to the technology described in the Korean patent application is fully compatible with a conventional SRAM.

However, since the DRAM according to the technology described in the patent application uses a DRAM cell, it is necessary to perform a refresh to effectively preserve data stored in the DRAM cell and a refresh circuit therefor.

Accordingly, an object of the present invention is to provide a refresh circuit of an SRAM compatible memory device capable of accessing a DRAM cell two or more times during an SRAM access period of one cycle.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

FIG. 1 is a timing diagram illustrating an example of a read operation of an SRAM compatible memory device having a DRAM access period of two periods during an SRAM access period of one period.

2 is a timing diagram illustrating an example of a write operation of an SRAM compatible memory device having a DRAM access period of two periods during an SRAM access period of one period.

3 is a block diagram conceptually illustrating an SRAM compatible memory device including a refresh circuit according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating the refresh circuit 311 of FIG. 3 in more detail.

5 is a diagram illustrating the refresh timer of FIG. 4 in more detail.

6 is a diagram illustrating in detail the refresh display signal generator of FIG. 4.

FIG. 7 is a view illustrating the refresh driver of FIG. 4 in more detail.

FIG. 8 is a diagram illustrating in more detail the access progress controller of FIG. 4.

9 is a diagram illustrating in detail the refresh auxiliary signal generator of FIG. 8.

FIG. 10 is a timing diagram illustrating a case where a write operation is performed immediately after a refresh in an SRAM compatible memory device.

11 is a timing diagram of important terminals of a refresh circuit according to an embodiment of the present invention.

One aspect of the present invention for achieving the above technical problem relates to a refresh circuit of an SRAM compatible memory device. The refresh circuit of the present invention is an SRAM compatible memory device including DRAM memory cells which require a refresh operation within a predetermined refresh period in order to preserve stored data. In order to effectively access data from an external source, an input of a preceding address is required. A DRAM compatible memory device in which a predetermined SRAM access cycle is required to elapse from an input of an address to a subsequent address, wherein the DRAM access interval enables input / output of data to / from the DRAM memory cells within the SRAM access cycle and the refresh operation. The SRAM compatible memory device in which a preliminary section longer than the time required for the execution of the memory is assigned, wherein the preliminary section is adjacent to the DRAM access section and includes a waiting section having a size equal to that of the DRAM access section. In, for a refresh request command generated during the standby period doedoe which the refresh operation is performed in the preliminary period, and controls to be carried out in the preliminary period of the next frame.

Preferably, the refresh circuit of the SRAM compatible memory device includes a refresh timer, a refresh display signal generator, a refresh driver, and an address counter. The refresh timer generates a refresh request signal that oscillates at a predetermined refresh control period. In response to the refresh request signal, the refresh display signal generator generates a refresh display signal generated as a pulse at each refresh control period. However, in the waiting period or the access period, the response to the refresh request signal of the refresh display signal is blocked. The refresh driver generates a refresh drive signal and an internal counter drive signal in response to the refresh display signal. The refresh driving signal blocks data input / output to the outside during the refresh operation. The address counter controls to sequentially activate word lines of the DRAM memory cells in response to the internal counter driving signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

3 is a block diagram conceptually illustrating an SRAM compatible memory device including a refresh circuit 311 according to an embodiment of the present invention. Referring to FIG. 3, the refresh circuit 311 receives the standby mode signal RSV from the standby section determination circuit 309 and receives the access control signal ACC from the access section determination circuit 313. The refresh circuit 311 generates a refresh driving signal RFH, an access progress signal RFRSVP, and an internal counter driving signal RFACT, and provides the refresh driving signal RFH to the access section determining circuit 313. The refresh of the DRAM memory cell of the memory cell array 317 is performed in the period in which the refresh driving signal RFH is activated. The refresh driving signal RFH is a signal for blocking a normal path for inputting and outputting data signals. The internal counter driving signal RFACT is a signal for controlling refresh operations by sequentially changing internal addresses, and is controlled by a refresh request generated in an internal timer (shown in FIG. 4) or the like that controls a predetermined period. Thus, when the refresh driving signal RFH is activated at regular intervals, but a refresh request occurs in a waiting period, and a time for performing refresh is not secured or when a refresh request occurs in a DRAM access period, Activated after the DRAM access period has elapsed. The access progress signal RFRSVP performs an access operation on a DRAM memory cell (not shown) of the memory cell array 317 immediately after completion of the refresh operation with respect to input of new data generated during the refresh operation. Control as possible. The refresh circuit 311 generates a counting signal ACNT and provides the counting signal ACNT to the decoder 315 so that the rows of the memory cell array 317 may be sequentially selected.

The standby section determination circuit 309 generates the standby mode signal RSV in response to the address detection signal ATDPSB. The address detection signal ATDPSB is a signal generated by a pulse by detecting a transition of the external address signal ADDR. That is, the address detection signal ATDPSB is generated as a pulse when a new address is input from the outside. When the address detection signal ATDPSB is activated in the form of a "low" pulse, the standby mode signal RSV is activated to a width sufficient to secure a standby period.

In response to the transition of the external data signal DIN, the activation of the access progress signal RFRSVP, or the termination of the activation of the standby mode signal RSV, the access section determination circuit 313 activates the low active signal ACT and the access. Generate a control signal ACC. In this specification, the row active signal ACT is a signal for securing a section in which a word line (not shown) of the memory cell array 317 can be selected and is provided to the decoder 315. The access control signal ACC is a signal for securing a section in which a word line (not shown) of the memory cell array 317 can be selected and precharged, and is provided to the refresh circuit 311. Therefore, the activation width of the access control signal ACC is greater than the activation width of the low active signal ACT.

The CS buffer 301 buffers the external chip select signal / CS to generate the internal chip select signal CS. The internal chip select signal CS has the opposite phase to the external chip select signal / CS. The power-up generation circuit 304 generates a power-up signal VPUP that activates to "high" when the power supply voltage is supplied from the outside to a predetermined voltage or more. The WE buffer 305 buffers the external write enable signal / WE to generate the internal write enable signal WE. The internal write enable signal WE has an opposite phase to the external write enable signal / WE.

The address signal buffer and the ATD circuit 303 receive the external address signal ADDR to generate the internal address signal INADD and the address detection signal ATDPSB. The internal address signal INADD is a signal in which the external address signal ADDR is buffered. The address transition signal ATDPSB is input to the waiting period determination circuit 309 to provide information that a new external address signal ADDR has been generated.

The data signal buffer and the DTD circuit 307 receive the external data signal DIN and generate an internal data signal INDATA and a data detection signal DTDPSB. The internal data signal INDATA is a buffered signal of the external data signal DIN. The data detection signal DTDPSB is a signal generated by detecting a transition of the external data signal DIN. The data sensing signal DTDPSB is input to the access section determining circuit 313 to provide information that a new external data signal DIN has been input.

4 is a block diagram conceptually illustrating the refresh circuit 311 of FIG. 3. Referring to FIG. 3, the refresh circuit is implemented by a refresh timer 401, a refresh request signal generator 403, a refresh driver 405, an address counter 407, and an access progress controller 409.

When the power-up signal VPUP is " high ", the refresh timer 401 generates a refresh request signal REREFQ that oscillates at a predetermined refresh control period (e.g., 16us or the like). The refresh display signal generator 403 generates the refresh display signal RFHPB in response to the transition of the refresh request signal REREFQ. That is, each time the refresh request signal REFREQ transitions to "low", the refresh display signal RFHPB is activated by a "low" pulse. Therefore, the refresh display signal RFHPB is generated in pulses for each refresh control period. However, the refresh display signal RFHPB does not respond to the refresh request signal REREFQ when the SRAM compatible memory device is in the waiting period or the access period. That is, when the standby mode signal RSV, which is a signal indicating that the SRAM compatible memory device is in the standby period, is "high", or when the access mode signal ACC, which is a signal indicating that it is an access period, is "high", The refresh display signal RFHPB maintains a "high" state.

Preferably, the refresh display signal generator 403 initializes the refresh display signal RFHPB to " high " in response to the initialization signal VPUP.

As shown in FIG. 11, the refresh driver 405 generates a refresh drive signal RFH and an internal counter drive signal RFACT in response to the refresh display signal RFHPB. The refresh driving signal RFH is a signal for blocking communication between the memory cell of the DRAM memory array 317 (see FIG. 3) and the outside. That is, when the SRAM compatible memory device performs a refresh operation, the refresh driving signal RFH is activated to block data input and output to the outside.

The address counter 407 is a DRAM memory cell (not shown) arranged in a matrix of rows and columns of the DRAM memory array 317 (see FIG. 3) in response to an internal counter driving signal RFACT. By sequentially activating word lines, the control is performed to perform refresh on each memory cell. That is, the counting signal ACNT generated from the address counter 407 is a signal representing a bundle of a plurality of counter signals that sequentially transition in response to the internal counter driving signal RFACT. The word line of the DRAM memory cell to be activated is determined by the combination of the counter signals supplied to the decoder 315 (see FIG. 3).

The access progress controller 409 receives the refresh driving signal RFH and the data sensing signal DTDPSB, and generates an access progress signal RFRSVP. The access progress signal RFRSVP is activated after the completion of the refresh operation. As illustrated in FIG. 10, the access progress controller 409 causes the semiconductor memory device to execute when a transition of data for writing WRITE occurs while the refresh is being performed instead of the waiting section or the access section. The access operation is performed immediately after the refresh is performed. That is, as illustrated in FIG. 11, when data input from the outside occurs during the refresh operation of the current frame, the access progress signal RFRSVP responds to the transition of the refresh driving signal RFH to "low". Activate in the form of a pulse.

5 is a diagram illustrating the refresh timer 401 of FIG. 4 in more detail. Referring to FIG. 5, the refresh timer 401 includes an oscillating unit 501 and a period expansion unit 503. The oscillating unit 501 generates an oscillating signal VOSC having a predetermined oscillating period (for example, 1us) when the power-up signal VPUP is activated "high".

The periodic expansion unit 503 receives the oscillating signal VOSC and generates one or more periodic control signals PCNT1, PCNT2, PCNT3, PCNT4,... Preferably, the periodic extension 503 is implemented with one or a plurality of periodic counters 503a, 503b, 503c, 503d,... Which are connected in series. By such a configuration, the period of the period control signals PCNT1, PCNT2, PCNT3, PCNT4, ... can be extended at a predetermined expansion ratio. For example, assume that the period of the oscillating signal VOSC is 1us. Then, the period of the period adjusting signals PCNT1, PCNT2, PCNT3, PCNT4, ... is extended to 2us, 4us, 8us, 16us, and the like. Can be. More preferably, any one of the period control signals PCNT1, PCNT2, PCNT3, PCNT4, ... may be selectively requested by the mask operation during the manufacturing process of the SRAM compatible memory device. It may be connected to a signal REFREQ.

6 illustrates the refresh display signal generator 403 of FIG. 4 in more detail. Referring to FIG. 6, the refresh display signal generator 403 includes a transmission control signal generator 601, a delay stage 603, a transmission gate 605, and a pulse generator 607. The transmission control signal generator 601 receives the standby mode signal RSV, the access mode signal ACC, and the refresh driving signal RFH, and generates the transmission control signal TRCONB. When the standby mode signal RSV, the access mode signal ACC, or the refresh drive signal RFH is "high", the transmission control signal TRCONB is deactivated to "high". Therefore, the transfer control signal TRCONB can be activated to be "low" only in the period in which the semiconductor memory device is not the standby period and the access period and the normal path is not blocked.

The transmission gate 605 transmits the refresh request signal REFREQ, which is delayed for a predetermined time by the delay stage 603. While the transmission control signal TRCONB is in a "high" inactive state, the transmission gate 605 is "turned off", so that the transmission of the refresh request signal REFREQ is interrupted. The pulse generator 607 generates a refresh display signal RFHPB which is activated in the form of a "low" pulse in response to the transition of the refresh request signal REFREQ to "high" transmitted by the transfer gate 605. . On the other hand, when the power-up signal VPUP is activated to " high ", that is, in the " low " state, the NMOS transistor 509 is turned on, so that the refresh display signal RFHPB is initialized to " high ".

FIG. 7 illustrates the refresh driver 405 of FIG. 4 in more detail. Referring to FIG. 7, the refresh driver 705 includes first and second pulse generators 701 and 703. In response to the transition of the refresh display signal RFHPB to "low", the first and second pulse generators 701 and 703 generate the internal counter drive signal RFACT and the refresh drive signal RFH, respectively. The first pulse generator 601 is implemented including a short delay stage 601a, and the second pulse generator 603 is implemented including a long delay stage 603a. Therefore, the internal counter drive signal RFACT has an activation width smaller than the refresh drive signal RFH.

FIG. 8 is a diagram illustrating the access progress controller 409 of FIG. 4 in detail. Referring to FIG. 8, the access progress controller 409 includes a refresh preparation signal generator 801, a pulse generator 803, and a refresh auxiliary signal generator 805. The refresh preparation signal generator 801 inputs the standby mode signal RSV and the access control signal ACC to generate the refresh preparation signal REREFRE. The refresh preparation signal REFPRE is activated "high" in response to the activation of the refresh auxiliary signal REHDB to "low", but the activation is blocked in the waiting period or the access period. The refresh auxiliary signal RFHDB is a signal output from the refresh auxiliary signal generator 805. The refresh auxiliary generator 805 is shown in detail in FIG. 9. Referring to FIG. 9, the refresh auxiliary signal RFHDB is a signal for controlling the DRAM access period to proceed after the refresh to the transition of the input data DIN (see FIG. 3) generated during the refresh. That is, as shown in FIG. 11, when the data detection signal DTDPSB is activated with a pulse when the refresh driving signal RFH is "high", the refresh auxiliary signal RFHDB is connected to the data detection signal DTDPSB. Respond to activation of the pulse form Specifically, it is as follows. That is, suppose that the data detection signal DTDPSB is deactivated to "high" again after the transition from the deactivation state of "high" to the activation state of "low". Then, the logic "high" refresh drive signal RFH is input to the inversion logic circuit 913 via the first transfer gate 901 and the second transfer gate 905. Accordingly, the refresh auxiliary signal RFHDB is activated "low" in response to the activation of the pulse shape of the data detection signal DTDPSB. However, the deactivation of the refresh auxiliary signal RFHDB proceeds after the delay time by the delay stage 911 with respect to the deactivation of the refresh driving signal RFH. This is to secure a time for the access progress signal RFRSVP to be activated. On the other hand, the refresh drive signal RFH delayed by the delay unit 907 is input to one input terminal of the first NAND gate 903 and the second NAND gate 909. This is to prevent toggling of the refresh auxiliary signal RFHDB, which may be generated due to the deactivation of the refresh driving signal when the data detection signal DTDPSB is activated in a low state. Preferably, the delay time by the delay unit 907 is the same as the delay time by the delay unit 911. Referring back to FIG. 8, the pulse generator 803 is enabled by activating the refresh ready signal REFPRE to " high " and activating it in the form of a pulse in response to the refresh drive signal RFH. Generate a progress signal RFRSVP. As shown in FIG. 10, when there is data input during the refresh operation, the access progress signal RFRSVP is activated by a "high" pulse to write valid data immediately after the refresh operation of the current frame. This is a signal to control the progress. As shown in FIG. 11, when the refresh drive signal RFH is "low", the access progress signal RFRSVP is generated as a "high" pulse. The access progress signal RFRSVP is fed back to the refresh preparation signal generator 801. Thus, once the access progress signal RFRSVP transitions to " high ", even if the access mode signal ACC goes to " high ", the access progress signal RFRSVP continues to be " high. &Quot; Therefore, the activation of the access progress signal RFRSVP can be maintained at a width equal to or greater than a predetermined size.

The refresh preparation signal generator 801 specifically includes a latch unit 801a, an inverter 801b, and a logic unit 801b. The latch portion 801a includes first and second NAND gates 801a1 and 801a2 that are cross coupled. The first NAND gate 801a1 uses the access mode signal ACC and the output signals of the second NAND gate 801a2 as two input signals. The second NAND gate 801a2 uses the access progress signal RFRSVP and the output signals of the first NAND gate 801a1 as two input signals. Therefore, once the access progress signal RFRSVP transitions to "high", the output signals of the first NAND gate 801a1 and the second NAND gate 801a2 are activated to "high" and "low", respectively.

The inverter 801b inverts the logic state of the output signal of the first NAND gate 801a1. The logic unit 801c is enabled when the refresh auxiliary signal RFHDB is activated "low". The logic unit 801c negates the delayed standby mode signal RSV and the output signal of the inverter 801b. Preferably, the logic unit 801c is implemented as a NOR gate 801c1 that receives the standby mode signal RSV, the output signal of the inverter 801b, and the refresh auxiliary signal RFHDB as input signals.

As illustrated in FIG. 10, when the access progress controller 809 transitions data for write while the refresh is being performed instead of the waiting section or the access section, the SRAM compatible memory device may be configured. After the refresh is performed, the access operation is controlled to be performed again.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The refresh circuit may perform refresh in an SRAM compatible memory device in which an access section for inputting / outputting data and a waiting section for performing a refresh operation are allocated during one SRAM access cycle. In addition, the refresh circuit including the access progress control unit causes the SRAM-compatible memory device to perform a refresh on the transition of data for write (WRITE) while the refresh is being performed instead of the waiting section or the access section. Control to perform the access operation.

Claims (9)

An SRAM-compatible memory device including DRAM memory cells that require a refresh operation within a predetermined refresh period in order to preserve stored data. A SRAM compatible memory device requiring a lapse of a predetermined SRAM access cycle, comprising: a DRAM access period capable of inputting / outputting data to / from the DRAM memory cells within the SRAM access cycle and a time required for performing the refresh operation; The SRAM compatible memory device in which a spare section is allocated, wherein the spare section is adjacent to the DRAM access section, and includes the standby section having a size equal to that of the DRAM access section. Wherein the refresh operation is performed in the spare section, and a refresh request command generated during the waiting period is controlled to be performed in the spare section of a next frame. The method of claim 1, wherein the refresh circuit A refresh timer for generating a refresh request signal oscillating at a predetermined refresh control period; In response to the refresh request signal, a refresh display signal generated by a pulse is generated every refresh control period, and in the waiting period or the DRAM access period, a refresh display in which the response to the refresh request signal of the refresh display signal is blocked. A signal generator; A refresh driver for generating a refresh driving signal and an internal counter driving signal in response to the refresh display signal, wherein the refresh driving signal is configured to block data input / output to the outside during the refresh operation; And And an address counter configured to sequentially activate word lines of the DRAM memory cells in response to the internal counter driving signal. The method of claim 2, wherein the refresh request signal is And a reset state to an initial state in response to the refresh display signal. The method of claim 2, wherein the refresh timer An oscillating unit generating an oscillating signal having a predetermined oscillating period; And A periodic extension for receiving the oscillating signal and generating two or more periodic control signals for extending the oscillating period to a predetermined expansion ratio, The refresh circuit of an SRAM compatible memory device, wherein any one of the period control signals may become the refresh request signal by a mask operation during a manufacturing process of the SRAM compatible memory device. The display apparatus of claim 2, wherein the refresh display signal generator A transmission gate configured to transmit the refresh request signal and to block transmission of the refresh request signal in the waiting period or the DRAM access period; And And a pulse generator configured to generate the refresh display signal activated in the form of a pulse in response to the refresh request signal transmitted by the transfer gate. The display device of claim 5, wherein the refresh display signal generator And a delay stage for delaying the refresh request signal to a predetermined time. The method of claim 2, wherein the refresh circuit An access progress control unit configured to generate an access progress signal for controlling a DRAM access section in which data input is performed after the refresh operation is performed to the data input generated during the refresh operation of the current frame. And an access progress controller configured to control activation of the access progress signal in response to a signal. The method of claim 7, wherein the access progress control unit A refresh preparation signal generator that is activated in response to a predetermined refresh assistance signal, and generates a refresh preparation signal for which a response is blocked in response to the activation of the refresh assistance signal during the waiting period or the DRAM access period. The signal is the refresh preparation signal generator is activated in response to the input of new data generated during the refresh; And a pulse generator which is enabled by activation of the refresh ready signal and generates the access progress signal that is activated in the form of a pulse in response to disabling the refresh drive signal. Refresh circuit. The method of claim 8, wherein the refresh preparation signal generator A latch unit having a signal indicating the DRAM access period and first and second NAND gates respectively receiving the access progress signal as one input signal, wherein output signals of the first and second NAND gates are cross-coupled; The latch unit serving as another input signal of the second and first NAND gates, respectively; An inverter for inverting a logic state of an output signal of the first NAND gate; And And a logic unit enabled by the activation of the refresh auxiliary signal, the logic unit configured to perform an NOR operation on the signal indicating the waiting period and the output signal of the inverter.