KR20020086197A - Data input circuit and data input method for synchronous semiconductor memory device - Google Patents

Abstract

PURPOSE: A data input circuit and a data input method of a synchronous semiconductor memory device are provided, which can patch data of N bit stably by increasing a timing margin between a data strobe signal and an external clock signal. CONSTITUTION: A semiconductor memory device comprises a clock buffer(110), a data strobe buffer(130), a data input buffer(150), a data input circuit(170) and a data input driver(190). The clock buffer generates an internal clock signal(PCLK) in response to the first edge of an external clock signal(CLK), and the data strobe buffer generates the first internal data strobe signal(PDSb0) by buffering a data strobe signal(DQS). The data input buffer generates internal data(PDIN) having N bit data string by buffering external data(DIN) having N bit data string. The data input circuit converts N bit serial data(PDIN) into N bit parallel data in response to the internal clock signal and the first internal data strobe signal, and then outputs it to the data input driver. The data input driver drives an output signal of the data input circuit to a memory cell array.

Description

Data input circuit and data input method for synchronous semiconductor memory device

The present invention relates to a synchronous semiconductor memory device, and more particularly, to a data input circuit and a data input method capable of stably fetching valid data of N bits.

In order to improve the operation speed of the DRAM, a synchronous DRAM (synchronous DRAM, hereinafter referred to as SDRAM ') that operates in synchronization with an external system clock has been developed.

In order to further improve the data processing speed, a double data rate (DDR) SDRAM and Rambus DRAM have been developed to process data in synchronization with a rising edge and a falling edge of a clock.

DDR SDRAM uses a source synchronous interface because data is transferred at high speed. This means that the input and output of the data is delivered in synchronization with a data strobe signal (hereinafter referred to as 'DQS') made with the data at the data source.

1A is a block diagram of a conventional synchronous semiconductor memory device. FIG. 1B is a detailed circuit diagram of the data register of FIG. 1A. FIG. 2 is a timing diagram illustrating a data write operation of the semiconductor memory device of FIG. 1A. 1A, 1B, and 2 are described in detail in Korean Application No. 97-9191 and US Patent Registration No. 6,078,546, and thus a detailed description thereof will be omitted.

In conclusion, the prior art has a standard tDQSS indicating the timing margin of the external clock signal CLK and the data strobe signal DQS, that is, the data strobe signal DQS is the first logic from the rising edge of the external clock signal CLK. Since the time from the transition from 'low' to logic 'high' is small, the timing margin of the resynchronization between the external clock signal CLK and the data strobe signal DQS is small, which makes it difficult to configure the system.

Accordingly, the technical problem to be achieved by the present invention is to increase the timing margin between the data strobe signal and the external clock signal when data is input in synchronization with the data strobe signal and then resynchronized with the external clock signal to be written into the memory array. A data input circuit and a data input method for stably patching N bits of data are provided.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1A is a block diagram of a conventional synchronous semiconductor memory device.

FIG. 1B is a detailed circuit diagram of the data register of FIG. 1A.

2 is a timing diagram of a data write operation of the semiconductor memory device of FIG. 1A.

3 shows a block diagram of a data prefetch scheme according to a first embodiment of the present invention.

4 is a circuit diagram illustrating a data input circuit of FIG. 3.

5 is a timing diagram of a write operation of the data input circuit of FIG. 4.

6 is a block diagram illustrating a data prefetch scheme according to a second embodiment of the present invention.

FIG. 7 is a timing diagram of input / output waveforms of a data strobe buffer and a data input buffer according to the minimum tDQSS and the maximum tDQSS of FIG. 6.

FIG. 8 is a circuit diagram illustrating the data input circuit of FIG. 7.

9 shows a timing diagram of the output data of the serial input-parallel output circuit, the first latch circuit and the second latch circuit of FIG.

FIG. 10 shows a timing diagram of the data prefetch outline of FIG. 6.

According to an embodiment of the present invention, a semiconductor memory device that accesses data in synchronization with a rising edge of a clock and a falling edge of the clock includes 2 ^{(N + 1)} in response to a data strobe signal. N is a natural number.) A conversion circuit for outputting bit serial data as 2 ^{(N + 1)} bit parallel data, wherein each of the 2 ^{(N + 1)} bit parallel data is a 2 ^(N) clock of the data strobe signal. Has a valid data window corresponding to the 2 ^{(N + 1)} -bit parallel data in response to the first clock.

The conversion circuit includes a logic circuit, a first latch circuit, a second latch circuit, and an output circuit. The logic circuit generates two ^{(N + 1)} internal strobe signals by performing a logic operation on the data strobe signal and the divided signals obtained by dividing the data strobe signal by two ^(N) to two.

The first latch circuit latches the 2 ^{(N + 1)} bit serial data into the 2 ^{(N + 1)} bit parallel data in response to the internal strobe signals, and the second latch circuit latches the 2 ^{(N +1)} latches the output signals of the first latch circuit in response to the internal data strobe signal latching the 2 ^{(N + 1)} th data of the bit serial data.

The output circuit outputs the 2 ^{(N + 1)} bit parallel data to a data bus line in response to the first clock. The semiconductor memory device further includes a divider circuit for generating the first clock, and the divider circuit divides the internal clock 2 ^(N) in response to an internal clock.

According to an aspect of the present invention, there is provided a method of inputting data into a semiconductor memory device, which comprises: (a) dividing a data strobe signal and the data strobe signal by 2 ^(N) , where N is a natural number Generating two ^{(N + 1)} internal data strobe signals by performing a logical operation on the divided signals; (b) generating two ^{(N + 1)} bit serial data in response to the internal data strobe signals ^; Each latching into bit parallel data and (c) outputting parallel data of the 2 ^{(N + 1)} bits in response to the first clock.

The step (b) comprises the steps of: align the 2 ^{(N + 1)} bit 2 ^{(N + 1)} th data and the response to the internal data strobe signal to latch the 2 ^{(N + 1)} bits of parallel data in the serial data Further comprising: each of the 2 ^{(N + 1)} bits of parallel data has a valid data window corresponding to 2 ^(N) clocks of the data strobe signal, wherein the first clock has an internal clock of 2 ^(N) It's a busy clock.

In addition, the semiconductor memory device for accessing data in synchronization with the rising edge of the clock and the falling edge of the clock in accordance with another embodiment of the present invention for achieving the technical problem of the present invention, a plurality of strobe pulse generation circuit, A first latch circuit, a second latch circuit, and an output circuit are provided.

The frequency divider circuit generates a second data strobe signal obtained by dividing the first data strobe signal in response to an externally input first data strobe signal, and the plurality of strobe pulse generators generate the first data strobe signal and the first data strobe signal. Logically combine the second data strobe signals to generate a plurality of strobe pulse signals.

The plurality of first latch circuits sequentially latch each of a plurality of received serial data in synchronization with each of the plurality of strobe pulse signals, and the second latch circuit synchronizes the first strobe pulse signal with the first latch circuit. Receive and store data stored in the latch circuit.

The output circuit receives data stored in the second latch circuit in response to a predetermined clock signal, and simultaneously transmits the received data to a data bus line.

According to another aspect of the present invention, a semiconductor memory device that accesses data in synchronization with a rising edge of a clock and a falling edge of the clock includes a first division circuit, a second division circuit, and a number; Strobe pulse signal generating circuits,

A plurality of first latch circuits, a plurality of second latch circuits and an output circuit are provided. The first divider circuit outputs a second data strobe signal obtained by dividing the first data strobe signal in response to a first data strobe signal input from the outside, and the second divider circuit outputs a first clock signal input from the outside. In response, the second clock signal obtained by dividing the first clock signal is output.

The plurality of strobe pulse signal generation circuits generates a plurality of strobe pulse signals by logically combining the first data strobe signal and the second data strobe signal.

The first latch circuit sequentially latches a plurality of serial data received in synchronization with each of the plurality of strobe pulse signals, and the second latch circuit receives and stores an output signal of the first latch circuit. The output circuit simultaneously transmits the output signal of the second latch circuit to the data bus line in response to the second clock signal.

According to another aspect of the present invention, there is provided a semiconductor memory device that accesses data in synchronization with a rising edge of a clock and a falling edge of the clock, and includes a first division circuit, a second division circuit, and a strobe pulse. A circuit, a first latch circuit, a second latch circuit, and an output circuit.

The first divider circuit outputs a second data strobe signal obtained by dividing the first data strobe signal in response to a first data strobe signal input from the outside, and the second divider circuit outputs a first clock signal input from the outside. In response, the second clock signal obtained by dividing the first clock signal is output.

The plurality of strobe pulse generation circuits generates a plurality of strobe pulse signals by logically combining the first data strobe signal and the second data strobe signal.

The first latch circuit includes a plurality of latches sequentially latching a plurality of received serial data, respectively, in synchronization with each of the plurality of strobe pulse signals, and the second latch circuit finally receives a plurality of serial data. A plurality of latches are provided which are synchronized with a predetermined strobe pulse signal applied to latch the received data and simultaneously receive and latch the output signal of the first latch circuit.

The output circuit simultaneously transmits the output signal of the second latch circuit and the output signal of the first latch circuit latching the data finally received to the data bus line in response to the second clock signal.

A data input circuit for achieving the technical problem is a conversion circuit for converting serial data into parallel data in synchronization with the rising and falling edge of the data strobe signal; A data strobe counter that receives the data strobe signal and an internal clock signal and counts the number of pulses of the data strobe signal in an enable period of the data strobe signal to output a corresponding count signal; A first latch circuit for receiving and latching output data of the conversion circuit in response to the count signal; And a second latch circuit for receiving and latching output data of the first latch circuit in response to the internal clock signal.

The data strobe counter receives a write command signal and is initialized in response to the first clock signal of the internal clock after a valid data strobe signal is input, and the count signal is at the falling edge of the first pulse of the data strobe signal. It is preferably an output signal that is enabled in response and disabled in response to the falling edge of the last pulse of the data strobe signal.

The data input circuit may further include an instruction signal generation circuit for receiving the count signal and outputting an instruction signal, wherein the instruction signal is applied to the first latch circuit.

The conversion circuit includes a third latch circuit for latching odd-numbered data of the serial data in response to the data strobe signal; And a fourth latch circuit for latching even-numbered data of the serial data in response to the data strobe signal, wherein the count signal indicates the number of falling edges of the data strobe signal in an enable period of the data strobe signal. It is preferable that it is a signal generated by counting.

According to an embodiment of the present invention, a data input circuit includes a first register for latching first data input in response to a rising edge of a first pulse of a data strobe signal, and an output of the first register in response to a falling edge of the first pulse. A third register for receiving and latching data and a third register for receiving and storing output data of the second register in response to the rising edge of the second pulse of the data strobe and the third in response to the falling edge of the second pulse; First latch means having a fourth register for receiving and storing output data of a register; A fifth register for latching second data input in response to the falling edge of the first pulse of the data strobe signal and a sixth register for receiving and storing output data of the fifth register in response to the rising edge of the second pulse of the data strobe A second latch means having a register and a seventh register for receiving and storing output data of the sixth register in response to a falling edge of the second pulse, and in response to a rising edge of the second pulse of the data strobe signal; The third data input is stored in the third register through the first register and the second register, and the fourth data input in response to the falling edge of the second pulse of the data strobe signal is transmitted via the fifth register. Store in the sixth register, and store the data stream. Third latch means for receiving and storing data stored in a fourth register of the first latch means in response to an indication signal generated in response to a second falling edge of the lobe signal; Fourth latch means for receiving and storing data stored in a seventh register of the second latch means in response to the indication signal; Fifth latch means for receiving and storing data stored in a third register of the first latch means in response to the indication signal; And sixth latch means for receiving and storing data stored in the sixth register of the second latch means in response to the indication signal.

A data input circuit according to an embodiment of the present invention includes a first data latch circuit for latching odd-numbered data of 2N bit serial data in response to a data strobe signal and an even number of 2N bit serial data in response to the data strobe signal. A conversion circuit for converting the 2N bit serial data into 2N bit parallel data having a second data latch circuit for latching data respectively; A data strobe counter that receives the data strobe signal and an internal clock signal and counts the number of pulses of the data strobe signal in an enable period of the data strobe signal to output a corresponding count signal; An instruction signal generation circuit for generating an instruction signal in response to the count signal; A first latch circuit for receiving and latching output data of the conversion circuit in response to the indication signal; And a second latch circuit for receiving and latching an output signal of the first latch circuit in response to an internal clock signal.

A data input circuit according to an embodiment of the present invention includes a conversion circuit for converting 4-bit serial data into 4-bit parallel data in synchronization with the rising and falling edges of the first internal data strobe signal, respectively; A data strobe counter that counts the number of rising edges of the second internal data strobe signal and outputs a count signal corresponding to the number of rising edges; An instruction signal generation circuit for generating an instruction signal in response to the count signal; A first latch circuit for receiving and latching an output signal of the conversion circuit in response to the indication signal; And a second latch circuit for receiving and latching an output signal of the first latch circuit in response to a first internal clock signal.

Preferably, the first internal data strobe signal is a signal buffered with a predetermined external data strobe signal, and the second internal data strobe signal is a signal generated in response to a falling edge of the predetermined external data strobe signal.

Preferably, the data strobe counter generates a reset signal for initializing the data strobe counter in response to a second internal clock signal, and the data strobe counter is activated in response to the reset signal and deactivated in response to the count signal. Do.

The conversion circuit further comprises: a third latch circuit for latching odd-numbered data of the 4-bit serial data in response to the first internal data strobe signal; And a fourth latch circuit for latching even-numbered data of the 4-bit serial data in response to the data strobe signal.

A data prefetch method according to an embodiment of the present invention comprises the steps of converting N-bit serial data into N-bit parallel data in synchronization with the first and second edges of a predetermined data strobe signal; Receiving the data strobe signal and the internal clock signal, counting the number of second edges of the data strobe signal in an enable period of the data strobe signal, and outputting a corresponding count signal; Receiving the count signal and generating an indication signal; A first latch step of latching the N-bit parallel data in response to the indication signal; And a second latch step of receiving and latching data latched in the first latch step in response to a predetermined clock signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 shows a block diagram of a data prefetch scheme according to a first embodiment of the present invention. Referring to FIG. 3, the semiconductor memory device 100 includes a clock buffer 110, a data strobe buffer 130, a data input buffer 150, a data input circuit 170, and a data input driver 190.

The clock buffer 110 generates the internal clock signal PCLK in response to the first edge of the external clock signal CLK, and the data strobe buffer 130 buffers the data strobe signal DQS to generate the first internal data strobe. Generate the signal PDSb0.

The data input buffer 150 buffers external data DIN having an N-bit data string to generate internal data PDIN having an N-bit data string, and the data input circuit 170 has an internal clock PCLK. And in response to the first internal data strobe signal PDSb0, N-bit serial data PDIN is converted into N-bit parallel data and outputted to the data input driver 190. The data input driver 190 drives an output signal of the data input circuit 170 to a memory cell array (not shown).

4 is a circuit diagram illustrating a data input circuit of FIG. 3. The data input circuit 170 of FIG. 4 operates in 4-bit prefetch and latches 4-bit serial data into 4-bit parallel data in synchronization with the rising and falling edges of the first internal data strobe signal PDSb0. and a serial input parrel output circuit that writes 4-bit parallel data to the memory array in response to a predetermined clock.

Referring to FIG. 4, the data input circuit 170 according to the embodiment of the present invention includes a first latch circuit 10, a logic circuit 20, a second latch circuit 30, and an output circuit 40. And a clock frequency division circuit 50 is further provided.

5 is a timing diagram of a write operation of the data input circuit 170 of FIG. Hereinafter, the data write operation of the 4-bit prefetch data input circuit 170 according to the embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5.

The logic circuit 20 has an internal data strobe divider circuit 20a and a plurality of logic gates 1 to 7.

The internal data strobe divider circuit 20a may respond to the first internal DS (PDSb0) in response to the first internal DS (PDSb0) when the write enable signal PDIN_en generated from the memory controller (not shown) is activated (for example, logic high). A second internal DS (PDSb1) generated by dividing (PDSb0) by two is generated.

The internal data strobe divider circuit 20a is preferably composed of a D-flip flop, and the input terminal D and the second output terminal QB of the de-flip flop 20a are electrically connected to each other. do. Various modifications of the internal data strobe divider circuit 20a can be facilitated in the art.

The logic gate 1 logically multiplies the first internal DS PDSb0 and the second internal DS PDSb1 to output the third internal DS PDS0, and the logic gate 3 inverts the first internal DS PDSb0. The fourth internal DS PDS1 is output by ANDing the signal PDSb0b and the second internal DS PDSb1.

In addition, the logic gate 5 logically multiplies the signal PDSb1b inverting the first internal DS PDSb0 and the second internal DS PDSb1 to output the fifth internal DS PDS2, and the logic gate 7 The sixth internal DS PDS1 is output by performing a logical AND on the signal PDSb0b inverting the first internal DS PDSb0 and the signal PDSb1b inverting the second internal DS PDSb1.

Since the third internal DSs to sixth internal DSs PDS0 to PDS3, which are output signals of the logic gates 1, 3, 5, and 7, respectively divide the first internal DS PDSb0 by four, the third internal DS. The power consumption of the data input circuit 170 operating in response to the sixth to internal DSs PDS0 to PDS3 is reduced, and the re-synchronous timing margin of the data input circuit 170 is increased.

The first latch circuit 10 is composed of a plurality of latch circuits, for example de-flip flops 10a, 10b, 10c and 10d. The de-flip flops 10a, 10b, 10c, and 10d may have a first latch in response to rising edges of the third internal DSs to sixth internal DSs PDS0 to PDS3 when the write enable signal PDIN_en is activated. Each 4-bit data string (PDin) input to the circuit 10 is latched.

However, the de-flip flops 10a, 10b, 10c and 10d are respectively reset when the write enable signal PDIN_en is inactive (e.g., logic 'low').

Referring to the operation of the first latch circuit 10 in detail, the de-flip-flop 10a receives the first data D0 of the 4-bit data string PDin in response to the rising edge of the third internal DS PDS0. The de-flip-flop 10b latches the second data D1 of the 4-bit data string PDin in response to the rising edge of the fourth internal DS PDS1.

The de-flip-flop 10c latches the third data D2 of the data string PDin in response to the rising edge of the fifth internal DS (PDS2), and the de-flip-flop 10d receives the sixth internal DS (PDS3). Each of the fourth data D3 of the data string PDin is latched in response to the rising edges of the data strings PDin.

The second latch circuit 30 is composed of a plurality of latch circuits, for example de-flip flops 30a, 30b, and 30c. The second latch circuit 30 latches the output signals of the latch circuits 10a, 10b and 10c in response to the rising edge of the sixth internal DS (PDS3).

Therefore, the output signals Di0D to Di2D of the second latch circuit 30 may have a valid data window corresponding to two clocks of the data strobe signal DQS.

The clock frequency divider circuit 50 may generate a second command signal PCAS generated from the semiconductor memory device in response to a command such as a read and write command (column address strobe). When activated, the internal clock signal PCLK is received and the divided clock signal PCLK2T divided by two is output.

When the write enable signal PDIN_en is activated, the output circuit 40 outputs 4-bit parallel data to the data write driver 190 in response to the two-division clock signal PCLK2T.

Referring to FIG. 5, the first case (Case I) represents a case where the standard tDQSS indicating the timing margin of the internal clock signal PCLK and the data strobe signal DQS is the maximum tDQSSmax. Case II) shows the case where tDQSS is minimum (tDQSSmin).

In the semiconductor memory device according to the embodiment of the present invention, the timing margin is increased because the window between the maximum value and the minimum value of tDQSS corresponds to two clocks of the data strobe signal DQS.

Further, in synchronization with the data strobe signal ^{(DQS) 2 (N + 1} ) ( where N Hermit training a) bit data input circuit to the serial data 2 ^{(N + 1)} output to the bit parallel data by changing the 3 It's simple to implement.

Thus, reference to FIG. 3 in synchronization with the data strobe signal 2 ^{(N + 1) (where} N is a natural number) bit serial data 2 ^{(N + 1)} bit data, and outputting in parallel the data input circuit and a method for data input Briefly explain.

First, the logic circuit 20 sets the data strobe signal DQS to 2 ^(N) _. , 2 ² , 2 ¹ Logically divides the divided signals to generate 2 ^{(N + 1)} internal strobe signals.

For example, when 8-bit serial data is received and output as 8-bit parallel data (when N is 2), the logic circuit 20 connects the internal data strobe divider circuit 20a in series so as to connect the first internal DS. A signal obtained by dividing (PDSb0) by two and a signal divided by first internal DS (PDSb0) are generated.

Similarly to the embodiment of the present invention, eight three-input logic gates are used to logically combine the three signals to each of eight internal strobe signals that are activated in synchronization with the rising and falling edges of the data strobe signal. Generate.

The first latch circuit 10 latches the 2 ^{(N + 1)} bit serial data into the 2 ^{(N + 1)} bit parallel data, respectively, in response to the internal strobe signals. For example, the first latch circuit 10 includes eight latch circuits and latches 8-bit serial data into 8-bit parallel data in response to each of the rising edges of the eight internal strobe signals.

The second latch circuit 30 latches the output signals of the first latch circuit in response to the internal data strobe signal that latches the 2 ^{(N + 1)} th data of the 2 ^{(N + 1)} bit serial data. For example, the second latch circuit 20 includes seven latch circuits, each latch circuit output signal of the first latch circuit 10 in response to an internal data strobe signal latching the eighth data of the 8-bit serial data. Latch them.

The output circuit 40 outputs the 2 ^{(N + 1)} -bit parallel data in response to the clock divided by 2 ^(N ) of the internal clock PCLK. For example, the eight output terminals of the output circuit 40 have a data strobe signal ( Since eight data having valid data windows corresponding to four clocks of DS) are waiting, the output circuit 40 synchronizes the clock divided by four clocks of the internal clock PCLK to generate 8-bit parallel data of the memory array. It is output simultaneously to the write drivers.

In this case, the maximum and minimum windows of tDQSS correspond to four clocks of the data strobe signal (DQS), thereby increasing the resynchronization timing margin of the data strobe signal (DQS) and the clock.

6 shows a block diagram illustrating a data prefetch scheme according to a second embodiment of the present invention. According to the present invention, even when tDQSS varies from minimum to maximum, valid data can be fetched stably regardless of the change of tDQSS.

Referring to FIG. 6, the semiconductor memory device 200 includes a clock buffer 210, a data strobe buffer 220, a data input buffer 230, a data strobe counter 240, an indication signal generation circuit 250, and a data input. A circuit 260 and a data input driver 270.

The clock buffer 210 generates the first internal clock PCLK in response to a rising edge of the external clock signal CLK, and generates a first buffer in response to the falling edge of the external clock signal CLK. 2 Generate internal clock (PCLKB). Each of the first internal clock PCLK and the second internal clock PCLKB is a continuous short pulse signal.

The data strobe buffer 220 buffers the data strobe signal DQS to generate the first internal data strobe signal PDSD, and in response to the falling edge of the data strobe signal DQS, the second internal data strobe signal PDSBP. Occurs. The second internal data strobe signal PDSBP is a continuous short pulse signal.

The data input buffer 230 buffers the N-bit data string DIN. As shown in FIG. 10, the data strobe counter 240 initializes the data strobe counter 240 in response to the second internal clock PCLKB at the time when a valid data strobe signal is input after a write command. A counter reset signal CNTRST, which is a short pulse for generating a counter pulse, and the data strobe counter 240 activates the data strobe counter 240 in response to the rising edge of the counter reset signal CNTRST. (CNTEN).

The data strobe counter 240 is connected to the first rising edge and the second rising edge of the second internal data strobe signal PDSBP during the activation period of the counter enable signal CNTEN in response to the write signal PWA. The number is counted, and a first count signal CNT0 corresponding to the number of rising edges of the second internal data strobe signal PDSBP is generated.

For example, the data strobe counter 240 generates a first count signal CNT0 that is activated in response to the first rising edge of the second internal data strobe signal PDSBP and is inactivated in response to the second rising edge. The data strobe counter 240 may generate a second count signal CNT1 that is activated in response to the deactivation of the first count signal CNT0.

The counter enable signal CNTEN may be deactivated in response to the activated second count signal CNT1 or may be deactivated in response to the deactivation of the first count signal CNT0. When the counter enable signal CNTEN is deactivated, the data strobe counter 240 is deactivated.

The data strobe counter 240 counts the number of rising edges of the second internal data strobe signal PDSBP. The second internal data strobe signal PDSBP is a narrow pulse that is generated whenever the data strobe signal DQS transitions from logic 'high' to logic 'low'.

The data strobe counter 240 counts the number of falling edges of the data strobe signal DQS between the preamble and the postamble. When the data strobe counter 240 counts all the falling edges, the data strobe counter 240 is deactivated.

The instruction signal generating circuit 250 automatically pulses in response to the output signals CNTi, i of 0, 1, 2, 3, ... of the data strobe counter 240, that is, the first count signal CNT0 deactivated. Generate an indication signal (PDSEN) that is (auto pulse). The indication signal PDSEN is a signal indicating that the number of falling edges of the data strobe signal DQS has been counted.

The data input circuit 260 converts and latches the N-bit serial data PDIN into N-bit parallel data in response to the first internal data strobe signal PDSD, and is generated after all the N-bit parallel data is latched. After re-latching N-bit parallel data in response to (PDSEN), the N-bit parallel data (DINIi) latched in response to the first internal clock (PCLK) generated after the indication signal (PDSEN) is generated is input to the data input driver. Output at 270. The data input driver 270 outputs N bits of data latched in parallel to a memory cell array (not shown).

FIG. 7 illustrates a timing diagram of input / output waveforms of a data strobe buffer and a data input buffer according to the minimum tDQSS and the maximum tDQSS of FIG. 6.

The first case (CASE I) shows the input / output waveforms of the data strobe buffer 220 and the data input buffer 230 when tDQSS is the minimum (tDQSSmin). In the second case (CASE II), tDQSS is the maximum ( tDQSSmax) shows the input / output waveforms of the data strobe buffer 220 and the data input buffer 230. The data DIN is output in synchronization with the data strobe signal DQS. The sections A, A ', and B. B' represent an invalid first internal data strobe signal.

FIG. 8 is a circuit diagram illustrating the data input circuit of FIG. 7. Referring to FIG. 8, the data input circuit 260 includes a serial input-parallel output circuit 261, a first latch circuit 265, and a second latch circuit 267.

The serial input-parallel output circuit 261 includes a third latch circuit 262 and a fourth latch circuit 263, wherein the third latch circuit 262 includes a plurality of latch circuits, for example, a first internal data strobe signal. Four de-flip flops 261a, 261b, 261c, and 261d responsive to (PDSD).

The internal data PDIN is input to the de-flip flop 261a in response to the first internal data strobe signal PDSD, and each output terminal of the de-flip flops 261a, 261b, and 261c is de-flip-flop. And are electrically connected to respective input terminals of the fields 261b, 261c, and 261d.

The third latch circuit 263 includes N (N is a natural number) latches serially for latching odd-numbered data of the N-bit data string PDIN. The third latch circuit 262 of the 4-bit prefetch data input circuit 260, which is an embodiment of the present invention, has four de-flip flops and latches D0 and D2, which are odd-numbered data of the data string PDIN, respectively. do.

The fourth latch circuit 263 includes a plurality of latch circuits and a plurality of inverting circuits IN1, IN2, and IN3. The plurality of latch circuits have, for example, a plurality of de-flip flops 263a, 263b, 263c responsive to the first internal data strobe signal PDSD. The internal data PDIN is input to the input terminal of the inverting circuit IN1, the output terminal of the inverting circuit IN1 is at the input terminal of the de-flip flop 263a, and the input terminal of the de-flip flop 263b is the de-flip flop. To the output terminal of 263a, the input terminal of the de-flip flop 263c is connected to the output terminal of the de-flip flop 263b, respectively.

The input terminal of the inverting circuit IN2 is connected to the output terminal of the de-flip flop 261c, and the input terminal of the inverting circuit IN3 is connected to the output terminal of the de-flip flop 263b. The inverting circuits IN1, IN2, IN3 are for matching the phases of the output data DO1, DE1, DO2, DE2 of the serial input-parallel output circuit 261.

The fourth latch circuit 263 includes (N-1) latch circuits for latching even-numbered data of the N-bit data string PDIN. The fourth latch circuit 263 of the 4-bit prefetch data input circuit 260, which is an embodiment of the present invention, latches even-numbered data D1 and D3 of the data string PDIN, respectively. Accordingly, the serial input-parallel output circuit 262 converts and latches the N-bit serial data string PDIN into N-bit parallel data.

The first latch circuit 265 includes a plurality of latch circuits, for example, de-flip props 265a, 265b, 265c, and 265d, and the data DO1, which are latched in parallel when the indication signal PDSEN is activated. DE1, DO2, and DE2 are output to the second latch circuit 267.

The input end of the de-flip flop 265a is connected to the output end of the de-flip flop 261d, and the input end of the de-flip flop 265b is connected to the output end of the de-flip flop 263c, respectively. The input terminal of 265c is connected to the output terminal of the inverting circuit IN2, and the input terminal of the de-flip flop 265d is connected to the output terminal of the inverting circuit IN3, respectively. The first latch circuit 265 latching the N bit has N de-flip flops.

The second latch circuit 267 latches the output signals DP1, DP2, DP3, and DP4 of the first latch circuit 265 in response to the rising edge of the first internal clock signal PCLK and the data input driver 270. ) The second latch circuit 267 includes a plurality of latch circuits, for example, a plurality of de-flip flops 267a, 267b, 267c, and 267d. An input terminal of each of the plurality of de-flip flops 267a, 267b, 267c, and 267d is connected to an output end of each of the de-flip flops 265a, 265b, 265c, and 265d.

9 illustrates a timing diagram of output data of the serial input-parallel output circuit 261, the first latch circuit 265, and the second latch circuit 267 of FIG. 8. Referring to FIG. 9, the first latch circuit 265 latches the output data DO1, DE1, DO2, and DE2 of the serial input-parallel output circuit 261 in response to the indication signal PDSD, and latches the second latch. The circuit 267 latches the output signals DP1, DP2, DP3, DP4 of the first latch circuit 265 in response to the first internal clock signal PCLK.

FIG. 10 shows a timing diagram of the data prefetch outline of FIG. 6. Referring to FIG. 10, input / output signals of the data strobe buffer 220, the data strobe counter 240, and the activation circuit 250 when tDQSS is minimum (CASE I) and tDQSS is maximum (CASE II). Is a timing diagram respectively.

6 to 10, the data write operation of the data input circuit 260 is described in detail with reference to the external clock CLK to which the valid data strobe signal DQS is input after the write WRITE command. The internal data string PDIN of N bits is assumed to be 4 bits.

First, the operation of the serial input-parallel output circuit 261 is described. If the first internal data strobe signal PDSD is in the first state (e.g., logic 'low'), the de-flip-flop 261a returns data <D0. >, And when the first internal data strobe signal PDSD transitions to a second state (e.g., logic 'high') (hereinafter referred to as 'first rising edge'), data <D0> is de-flip. Latched to flop 261b and data <D1> latched to de-flip flop 263a, respectively.

When the first internal data strobe signal PDSD transitions to the first state (hereinafter referred to as 'first falling edge'), the data <D0> is de-flip-flop 261c and the data <D1> is depressed. -Flip-flop 263b and data <D2> are latched to de-flip-flop 261a, respectively. Subsequently, when the first internal data strobe signal PDSD transitions to a second state (hereinafter referred to as a 'second rising edge'), data <D0> is de-flip-flop 261d and data <D1> is de- -To flip-flop 263c, data <D2> is latched to de-flip-flop 261b and data <D3> to de-flip-flop 263a, respectively.

Subsequently, when the first internal data strobe signal PDSD transitions to the first state (hereinafter referred to as 'second falling edge'), data <D0> is de-flip-flop 261d, and data <D1> is depressed. Remain in the flip-flop 263c, and the data <D2> is latched in the de-flip flop 261c and the data <D3> in the de-flip flop 263b, respectively.

Therefore, the serial input-parallel output circuit 261 converts and arranges the 4-bit serial data string PDIN into 4-bit parallel data DO1, DE1, DO2, and DE2 in response to the valid data strobe signal DQS.

When the data strobe signal DQS has two falling edges, the first count signal CNT0 performs two logic transitions from logic 'low' to logic 'high' and from logic 'high' to logic 'low'. do.

Therefore, when the data strobe signal DQS has N rising edges and N falling edges in the data strobe enable period, the first count signal CNT0 performs N logic transitions, so that the indication signal generation circuit 250 generates N. In response to the first logic transition, an indication signal PDSEN is generated. Therefore, the activation signal PDSEN of the 4-bit prefetch data input circuit 260 is generated after the data strobe counter 240 counts two falling edges.

The first latch circuit 265 latches the output data DO1, DE1, DO2, DE2 of the serial input-parallel output circuit 261 in response to the indication signal PDSEN. The second latch circuit 267 latches the output signals DP1, DP2, DP3, and DP4 of the first latch circuit 265 in response to the first internal clock signal PCLK and the data of the second latch circuit 267. (DINi, I 1 to 4) are output to the data input driver 270.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the data input circuit and the data input method according to the present invention increase the timing margin of the tDQSS and thus have an advantage of easy system design. In addition, regardless of the tDQSS variable, N valid data can be fetched stably.

Claims (27)

A semiconductor memory device for accessing data in synchronization with a rising edge of a clock and a falling edge of the clock, In response to the data strobe signal 2 ^{(N + 1)} includes a conversion circuit that outputs (where N is a natural number) bit serial data to the 2 ^{(N + 1)} bits of parallel data, Each of the 2 ^{(N + 1)} bit parallel data has a valid data window corresponding to a 2 ^(N) clock of the data strobe signal, And the 2 ^{(N + 1)} bit parallel data is output in response to the first clock. The method of claim 1, wherein the conversion circuit, A logic circuit for generating two ^{(N + 1)} internal strobe signals by performing a logic operation on the data strobe signal and the divided signal which is two ^(N) to two main strobe signals; A first latch circuit for latching the 2 ^{(N + 1)} bit serial data into the 2 ^{(N + 1)} bit parallel data in response to each of the internal strobe signals; Latching the output signals of the first latch circuit in response to the internal data strobe signal latching the 2 ^{(N + 1)} th data of the 2 ^{(N + 1)} bit serial data to parallel the 2 ^{(N + 1)} bit. A second latch circuit for sorting data; And And an output circuit for outputting the 2 ^{(N + 1)} bit parallel data in response to the first clock. The semiconductor memory device of claim 1, And a divider circuit for generating the first clock, wherein the divider circuit divides the internal clock by 2 ^(N) in response to an internal clock. A semiconductor memory device for accessing data in synchronization with a rising edge of a clock and a falling edge of the clock, A conversion circuit for converting 4-bit serial data into 4-bit parallel data in synchronization with the data strobe signal, The 4-bit parallel data has a valid data window corresponding to two clocks of the data strobe signal, And outputting the 4-bit parallel data in synchronization with the first clock. The method of claim 4, wherein the conversion circuit, A logic circuit for logically combining the data strobe signal and the divided signal obtained by dividing the data strobe signal into two to generate internal data strobe signals that are activated in synchronization with the rising and falling edges of the data strobe signal; A first latch circuit sequentially latching the 4-bit serial data in synchronization with the internal data strobe signals; A second latch circuit arranged to align the 4-bit serial data by latching output signals of the first latch circuit in synchronization with the internal data strobe signal latching fourth data of the 4-bit serial data; And And an output circuit for outputting an output signal of the second latch circuit in response to the first clock. A method of inputting data into a semiconductor memory device that accesses data in synchronization with a rising edge of a clock and a falling edge of the clock, (a) generating two ^{(N + 1)} internal data strobe signals by performing a logical operation on the data strobe signal and the divided signals divided by 2 ^(N) (where N is a natural number) to 2 data strobe signals; (b) latching 2 ^{(N + 1)} bit serial data into 2 ^{(N + 1)} bit parallel data in response to the internal data strobe signals; And and (c) outputting parallel data of 2 ^{(N + 1)} bits in response to a first clock. According to claim 6, wherein step (b), Characterized by further comprising the step of alignment of the ^{2 (N + 1)} bits of parallel data to the 2 ^{(N + 1)} in response to the internal data strobe signal to latch 2 ^{(N + 1)} th data from the bit serial data Data entry method. 7. The method of claim 6, wherein each of the 2 ^{(N + 1)} bits of parallel data has a valid data window corresponding to 2 ^(N) clocks of the data strobe signal. 7. The data input method according to claim 6, wherein the first clock is a clock obtained by dividing an internal clock by 2 ^(N) . In synchronization with the rising and falling edge of the first clock, 2 ^{(N + 1)} (where N is a natural number) bit serial data is converted into 2 ^{(N + 1)} bit parallel data, and the 2 ^{(N + 1)} bit A conversion circuit for aligning valid data windows of parallel data; And An output circuit for outputting an output signal of the conversion circuit in synchronization with a second clock; And said 2 ^{(N + 1)} bit parallel data has a valid data window corresponding to 2 ^(N) clock of said first clock. The method of claim 10, wherein the conversion circuit, A logic circuit for generating two ^{(N + 1)} third clocks by performing a logical operation on the first clock and the divided signals divided by 2 ^(N) to 2 the first clock; A first latch circuit for latching the 2 ^{(N + 1)} bit serial data into the 2 ^{(N + 1)} bit parallel data in response to each of the third clocks; And The ^{2 (N + 1) 2 (} N + 1) th to for latching the data in response to the third clock the output signal of the first latch circuit 2 ^{(N + 1)} alignment to the bit serial data from the bit serial data And a second latch circuit. The method of claim 10, wherein the data input circuit, And a frequency divider circuit for generating the second clock, wherein the frequency divider circuit divides the internal clock by 2 ^(N) in response to an internal clock. A semiconductor memory device for accessing data in synchronization with a rising edge of a clock and a falling edge of the clock, A divider circuit configured to generate a second data strobe signal obtained by dividing the first data strobe signal in response to an externally input first data strobe signal; A plurality of strobe pulse signal generation circuits for generating a plurality of strobe pulse signals by logically combining the first data strobe signal and the second data strobe signal; A plurality of first latch circuits sequentially latching a plurality of serial data received in synchronization with each of the plurality of strobe pulse signals; A second latch circuit for receiving and storing data stored in the first latch circuit in synchronization with the predetermined strobe pulse signal; And And an output circuit for receiving data stored in the second latch circuit in response to a predetermined clock signal, and simultaneously transmitting the received data to a data bus line. A semiconductor memory device for accessing data in synchronization with a rising edge of a clock and a falling edge of the clock, A first divider circuit configured to output a second data strobe signal obtained by dividing the first data strobe signal in response to an externally input first data strobe signal; A second divider circuit configured to output a second clock signal obtained by dividing the first clock signal in response to a first clock signal input from an external device; A plurality of strobe pulse signal generation circuits for generating a plurality of strobe pulse signals by logically combining the first data strobe signal and the second data strobe signal; A plurality of first latch circuits sequentially latching a plurality of serial data received in synchronization with each of the plurality of strobe pulse signals; A second latch circuit for receiving and storing an output signal of the first latch circuit; And an output circuit for simultaneously transmitting an output signal of the second latch circuit to a data bus line in response to the second clock signal. A semiconductor memory device for accessing data in synchronization with a rising edge of a clock and a falling edge of the clock, A first divider circuit configured to output a second data strobe signal obtained by dividing the first data strobe signal in response to an externally input first data strobe signal; A second divider circuit configured to output a second clock signal obtained by dividing the first clock signal in response to a first clock signal input from an external device; A plurality of strobe pulse signal generation circuits for generating a plurality of strobe pulse signals by logically combining the first data strobe signal and the second data strobe signal; A plurality of first latch circuits sequentially latching a plurality of serial data received in synchronization with each of the plurality of strobe pulse signals; A plurality of second latch circuits simultaneously receiving and latching an output signal of the first latch circuit in synchronization with a predetermined strobe pulse signal applied to latch data finally received among the plurality of serial data; And And an output circuit for simultaneously transmitting to the data bus line an output signal of the second latch circuit and an output signal of the first latch circuit which latches data finally received in response to the second clock signal. Semiconductor memory device. A conversion circuit for converting serial data into parallel data in synchronization with the rising and falling edges of the data strobe signal; A data strobe that receives the data strobe signal and an internal clock signal, counts the number of pulses of the data strobe signal in an enable period of the data strobe signal, and outputs a count signal corresponding to the number of pulses of the data strobe signal counter; A first latch circuit for receiving and latching output data of the conversion circuit in response to the count signal; And And a second latch circuit for receiving and latching output data of the first latch circuit in response to the internal clock signal. 17. The data input circuit of claim 16, wherein the data strobe counter receives a write command signal and is initialized in response to a first clock signal of the internal clock after a valid data strobe signal is input. 18. The method of claim 17, wherein the count signal is an output signal that is enabled in response to the falling edge of the first pulse of the data strobe signal and is disabled in response to the falling edge of the last pulse of the data strobe signal. Data input circuit. 17. The data input circuit of claim 16, wherein the data input circuit further comprises an instruction signal generation circuit for receiving the count signal and outputting an instruction signal, wherein the instruction signal is applied to the first latch circuit. . 20. The apparatus of claim 16 or 19, wherein the conversion circuit comprises: a third latch circuit for latching odd-numbered data of the serial data in response to the data strobe signal; And A fourth latch circuit for latching even-numbered data of the serial data in response to the data strobe signal, And the count signal is a signal generated by counting the number of falling edges of the data strobe signal in the enable period of the data strobe signal. A first register latching the first data input in response to the rising edge of the first pulse of the data strobe signal, and a second register and the data receiving and latching the output data of the first register in response to the falling edge of the first pulse; A third register for receiving and storing the output data of the second register in response to the rising edge of the second pulse of the strobe and a fourth register for receiving and storing the output data of the third register in response to the falling edge of the second pulse. First latch means having a; A fifth register for latching second data input in response to the falling edge of the first pulse of the data strobe signal and a sixth register for receiving and storing output data of the fifth register in response to the rising edge of the second pulse of the data strobe Second latch means having a register and a seventh register for receiving and storing output data of the sixth register in response to a falling edge of the second pulse, The third data input in response to the rising edge of the second pulse of the data strobe signal is stored in the third register through the first register and the second register, The fourth data input in response to the falling edge of the second pulse of the data strobe signal is stored in the sixth register via the fifth register, Third latch means for receiving and storing data stored in a fourth register of the first latch means in response to an indication signal generated in response to a second falling edge of the data strobe signal; Fourth latch means for receiving and storing data stored in a seventh register of the second latch means in response to the indication signal; Fifth latch means for receiving and storing data stored in a third register of the first latch means in response to the indication signal; And And sixth latch means for receiving and storing data stored in the sixth register of the second latch means in response to the indication signal. In the data input circuit, A first data latch circuit for latching odd-numbered data of 2N bit serial data in response to a data strobe signal and a second data latch circuit for latching even-numbered data of the 2N bit serial data in response to the data strobe signal, respectively; A conversion circuit configured to convert the 2N bit serial data into 2N bit parallel data; A data strobe counter that receives the data strobe signal and an internal clock signal and counts the number of pulses of the data strobe signal in an enable period of the data strobe signal to output a corresponding count signal; An instruction signal generation circuit for generating an instruction signal in response to the count signal; A first latch circuit for receiving and latching output data of the conversion circuit in response to the indication signal; And And a second latch circuit for receiving and latching an output signal of the first latch circuit in response to an internal clock signal. A conversion circuit for converting 4-bit serial data into 4-bit parallel data in synchronization with the rising and falling edges of the first internal data strobe signal; A data strobe counter that counts the number of rising edges of the second internal data strobe signal and outputs a count signal corresponding to the number of rising edges; An instruction signal generation circuit for generating an instruction signal in response to the count signal; A first latch circuit for receiving and latching an output signal of the conversion circuit in response to the indication signal; And And a second latch circuit for receiving and latching an output signal of the first latch circuit in response to a first internal clock signal. The method of claim 23, wherein the first internal data strobe signal is a signal buffered a predetermined external data strobe signal, And the second internal data strobe signal is a signal generated in response to a falling edge of the predetermined external data strobe signal. The data strobe counter of claim 23, wherein the data strobe counter generates a reset signal for initializing the data strobe counter in response to a second internal clock signal. And the data strobe counter is activated in response to the reset signal and deactivated in response to the count signal. The method of claim 23, wherein the conversion circuit A third latch circuit for latching odd-numbered data of the 4-bit serial data in response to the first internal data strobe signal; And And a fourth latch circuit for latching even-numbered data of the 4-bit serial data in response to the data strobe signal. Converting N bits of serial data into N bits of parallel data in synchronization with the first and second edges of the predetermined data strobe signal; Receiving the data strobe signal and the internal clock signal, counting the number of second edges of the data strobe signal in an enable period of the data strobe signal, and outputting a corresponding count signal; Receiving the count signal and generating an indication signal; A first latch step of latching the N-bit parallel data in response to the indication signal; And And a second latching step of receiving and latching data latched in the first latching step in response to a predetermined clock signal.