KR20020085248A - System for reducing consumption power of fpga - Google Patents

Abstract

PURPOSE: A system for reducing the power consumption of an FPGA(Field-Programmable Gate Array) is provided to reduce the power consumption used by the entire system by converting the mode of an FPGA to a standby mode if a driving signal is not inputted or a predetermined counting time is over. CONSTITUTION: The system(100) comprises a processor(110) and the FPGA(120). The processor outputs a clock signal and a driving signal. The FPGA comprises a sensing circuit(130), a clock buffer(140), and an internal circuit(150). The sensing circuit comprises a counter outputting a count completion signal after a predetermined counting time is over and a logic outputting an enable signal or a disable signal to the clock buffer depending on the input of the count completion signal or the driving signal. The clock buffer comprises the first to the third clock buffers(141-143) converting the block signal into the first to the third internal clock signals. The internal circuit comprises the first to the third internal circuits(151-153) driving the system by using the first to the third clock signals outputted from the clock buffer.

Description

FFIAGE's Power Consumption Reduction System {SYSTEM FOR REDUCING CONSUMPTION POWER OF FPGA}

The present invention relates to a power consumption reduction system, and more particularly, an FPGA that can reduce the power consumption of the entire system by switching a field programmable gate array (FPGA) to standby mode when the system is not operating. The present invention relates to a system for reducing power consumption.

In general, as shown in FIG. 1, a system 10 having an FPGA includes a processor 20 and an FPGA 30.

The processor 20 applies a clock signal CLK to the FPGA 30.

The FPGA 30 includes a buffer unit 40 and an internal circuit unit 50.

The buffer unit 40 converts the clock signal CLK applied from the processor 20 into a first internal clock signal CLK1 to a third internal clock signal CLK3 necessary for the system, respectively. It consists of the 3rd buffer 43.

The internal circuit unit 50 inputs the first internal clock signal CLK1 to the third internal clock signal CLK3 output from the first buffer 41 to the third buffer 43 of the buffer unit 40, respectively. The first internal circuit 51 to the third internal circuit 53 for driving the system.

When the operation of the conventional FPGA 30 is described, first, the first buffer 41 to the third buffer 43 of the buffer unit 40 are inputted with the clock signal CLK output from the processor 20. The clock signal CLK is converted into the first internal clock signal CLK1 to the third internal clock signal CLK3 required for the system, respectively.

Next, the first internal clock signal CLK1 to the third internal clock signal CLK3 output from the first buffer 41 to the third buffer 43 of the buffer unit 40 respectively drive the system. Applied to the first internal circuit 51 to the third internal circuit 53, respectively. Then, the system is driven according to the output signal output from the first internal circuit 51 to the third internal circuit 53.

However, the first buffer 41 to the third buffer 43 of the FPGA 30 as described above may transmit the clock signal CLK output from the processor 20 to the first internal circuit 51 to the third internal circuit 53. As a buffer that simply buffers the first internal clock signal CLK1 to the third internal clock signal CLK3 necessary for the first internal clock signal CLK1 to the third internal clock signal CLK3, the clock source is applied to the first internal circuit 51 to the third internal circuit 53. It exists. This clock source causes the first internal circuit 51 to the third internal circuit 53 to operate the FPGA 30 even when the system does not operate, thereby causing unnecessary power consumption in the system.

Accordingly, an object of the present invention is to solve the above problems, and includes a sensing circuit inside the FPGA so that a drive signal (Transfer Start: TS) is not input or exceeds a preset counting time after the drive signal is input. In this state, the FPGA is put into standby mode to reduce the power consumption of the entire system.

1 is a block diagram showing the configuration of a system with a conventional FPGA

2 is a block diagram showing the configuration of a system for reducing power consumption of an FPGA in accordance with an embodiment of the present invention.

3 is a block diagram illustrating a configuration of a sensing circuit included in the FPGA of FIG. 2.

<Explanation of symbols for main parts of the drawings>

110: processor 120: FPGA

130: detection circuit 140: clock buffer unit

150: internal circuit portion 131: counter

132: logic unit 141 to 143: first clock buffer to third clock buffer

151 to 153: first internal circuit to third internal circuit

Features of the present invention for achieving the above object,

A processor for outputting a clock signal and a driving signal;

An FPGA for outputting a signal for driving a system by using a clock signal and a driving signal output from the processor,

The FPGA,

A sensing circuit that outputs an enable signal when a driving signal is input from the processor within a predetermined counting time;

A clock buffer unit converting a clock signal output from the processor into an internal clock signal necessary for a system when an enable signal is output from the sensing circuit;

And an internal circuit unit for driving the system by using the internal clock signal output from the clock buffer.

Here, the sensing circuit,

A counter for counting a clock signal output from the processor and outputting a count completion signal when a predetermined counting is completed;

If the time point at which the drive signal is input by inputting the count completion signal and the drive signal output from the counter is within the counting time of the counter, an enable signal is output to the clock buffer, and the drive signal is not input or the The logic unit outputs a disable signal to the clock buffer when the counting time of the counter is exceeded.

Hereinafter, a configuration of a system for reducing power consumption of an FPGA according to the present invention will be described in detail with reference to FIGS. 2 and 3.

2 is a block diagram illustrating a configuration of a system for reducing power consumption of an FPGA according to an embodiment of the present invention, and FIG. 3 is a block diagram illustrating a configuration of a sensing circuit included in the FPGA of FIG. 2.

2 and 3, the power consumption reduction system 100 of an FPGA according to an embodiment of the present invention includes a processor 110 and an FPGA 120.

The processor 110 outputs a clock signal CLK and a driving signal TS.

The FPGA 120 includes a sensing circuit 130, a clock buffer unit 140, and an internal circuit unit 150.

The sensing circuit 130 counts the clock signal CLK output from the processor 110 and outputs a count completion signal when a preset counting is completed, and

The logic unit 142 outputs an enable signal or a disable signal to the clock buffer unit 140 according to whether the count completion signal output from the counter 141 and the driving signal TS are input.

When the enable signal is output from the sensing circuit 130, the clock buffer unit 140 outputs the clock signal CLK output from the processor 110 to the first internal clock signal CLK1 to the third internal clock. The first clock buffer 141 to the third clock buffer 143 are converted into a signal CLK3 and output.

The internal circuit unit 150 uses the first internal clock signal CLK1 to the third internal clock signal CLK3 output from the clock buffer unit 140 to drive the first internal circuit 151 to the third. It consists of an internal circuit 153.

Hereinafter, the operation of the power consumption reduction system of the FPGA according to an embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.

First, the clock signal CLK is supplied from the processor 110 to the FPGA 120. In this state, when the driving signal TS is input to the FPGA 120, the sensing circuit 130 in the FPGA 120 senses it. Thereafter, when the input driving signal TS is within a predetermined counting time, the logic unit 132 in the sensing circuit 130 outputs an enable signal to the first clock buffer 141 to the third clock buffer 143. Then, the first clock buffer 141 to the third clock buffer 143, the first internal clock signal (CLK1) to the third internal clock signal (CLK3) suitable for the system to apply the clock signal (CLK) applied from the processor 110 The first internal clock signal CLK1 to the third internal clock signal CLK3 are applied to the first internal circuit 151 to the third internal circuit 153 for driving the system. Then, the system is driven according to the output signal applied from the first internal circuit 151 to the third internal circuit 153.

On the contrary, after the driving signal TS is input to the FPGA 120 while the clock signal CLK is being supplied from the processor 110 to the FPGA 120, the predetermined counting time is exceeded or the driving signal TS is exceeded. ), If there is no input, senses it in the sensing circuit 130 in the FPGA 120 and disables the signal from the first clock buffer 141 to the third clock buffer 143 by the logic unit 142 in the sensing circuit 140. Outputs Then, since the clock signal CLK that has been supplied first is not converted into the first internal clock signal CLK1 to the third internal clock signal CLK3 necessary for the system, the internal circuit 130 is not driven and thus the system is not driven. .

As described above, according to the system for reducing power consumption of the FPGA according to the present invention, when the driving signal TS is not input or has exceeded a preset counting time after the input of the sensing circuit in the FPGA, the FPGA 120 ) To the standby mode to reduce the power consumption of the entire system to maximize the use time of the system, such as mobile phones, radios, MP3 players, etc. to maximize the use of the product quality have.

Claims (2)

A processor for outputting a clock signal and a driving signal; An FPGA for outputting a signal for driving a system by using a clock signal and a driving signal output from the processor, The FPGA, A sensing circuit that outputs an enable signal when a driving signal is input from the processor within a predetermined counting time; A clock buffer unit converting a clock signal output from the processor into an internal clock signal necessary for a system when an enable signal is output from the sensing circuit; And an internal circuit unit for driving the system by using an internal clock signal output from the clock buffer. The method of claim 1, The sensing circuit, A counter for counting a clock signal output from the processor and outputting a count completion signal when a predetermined counting is completed; If the time point at which the drive signal is input by inputting the count completion signal and the drive signal output from the counter is within the counting time of the counter, an enable signal is output to the clock buffer, and the drive signal is not input or the And a logic unit outputting a disable signal to the clock buffer when the counting time of the counter is exceeded.