KR20020084420A - Memory for storing image data of plasma display panel and application-specific integrated circuit using the same - Google Patents

Abstract

PURPOSE: A memory device for storing an image data of a plasma display panel and an application specific integrated circuit(ASIC) for using the same and an image data storage method are provide to reduce a storage capacity of the memory by storing the image data of plasma display panel(PDP) at the optimum, thereby reducing manufacturing costs. CONSTITUTION: A memory device(30) for storing an image data of a plasma display panel, wherein the number of horizontal pixels is A and the number of sub-fields is B, the memory device(30) includes a column decoder for decoding a column address of the memory cell in response to an external control signal, a low decoder for decoding a low address of the memory cell in response to the external control signal, an input/output controller for controlling data input/outputs of the memory cell by a predetermined bit number and a memory cell for connecting to the column decoder, the low decoder and the input/output controller respectively and storing the data at the appointed column address and the low address. The number of columns corresponds to a value obtained by dividing the A x B bit number by the input/output bit number controlled by the input/output controller.

Description

Memory device for storing image data of a plasma display panel and a semiconductor using the same {Memory for storing image data of plasma display panel and application-specific integrated circuit using the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory used in a PDP device, and in particular, an optimal cell capacity for input / output image data when driving a plasma display panel (PDP) (hereinafter referred to as 'PDP'). The present invention relates to a memory device for storing image data of a plasma display panel and a custom semiconductor using the same, which are configured to store a memory cell so as to reduce the storage capacity of the memory and reduce the production cost.

In general, a PDP device is a display device that displays an image by exciting phosphors formed in a discharge cell. The PDP device stores one frame image data of a display image divided based on a vertical synchronization signal as a memory device. : It stores the data in the Random Access Memory and reads the image data of the previous frame stored in the RAM and outputs the image data of the next frame to the internal driving IC (not shown). Therefore, the PDP apparatus necessarily requires a memory element for temporarily storing continuous image data.

FIG. 1A is a block diagram schematically illustrating an internal configuration of a general memory device 10. The memory device 10 may include a memory unit 11, a column decoder 12, and a row decoder ( 13) and the input / output control unit 14 is configured.

The memory unit 11 includes a plurality of cells for storing data in bit units, and the memory unit 11 includes at least one bank as is well known. The column decoder 12 and the row decoder 13 are for decoding the column address and the row address of the memory unit 11 based on an external control signal, respectively, and the input / output The controller 14 controls the input / output operation of the data of the memory unit 11 to a predetermined number of input / output bits, and a detailed description thereof will be omitted since it is a general matter.

FIG. 1B briefly shows a cell configuration of the memory unit 11 shown in FIG. 1A, where the memory unit 11 is i × j × k (i, j, k being an integer of 1 or more) as shown in FIG. 1B. I x j x k cells 1 for storing data of bits, and each cell 1 stores one bit of data. Hereinafter, for convenience of description, the configuration of the memory device will be represented by the cell structure shown in FIG. 1B.

Hereinafter, a method of expressing grayscales of a PDP device related to a storage method of image data of a general PDP device will be briefly described. When one still image displayed on the entire screen of the PDP device is called one frame, one frame includes at least X subfields represented by the number of discharges of 2 ⁰ to 2 ^X-1 times (X is an integer of 0 or more). Sub-field, the PDP apparatus combines the number of discharges of each subfield to express the brightness of the discharge cells in 256 levels of gray scale. In this case, as the number of subfields increases according to the display characteristics of the PDP device, the image quality of the display image is further improved.

Therefore, the PDP apparatus needs to rearrange continuous image data having, for example, 256 gray levels, into X or more subfields for each pixel, and the rearranged image data is temporarily stored in the memory device 10. The data is transmitted to a driving IC (not shown) of the PDP apparatus and output as an image.

FIG. 2 illustrates a method of storing PDP image data in a general memory device 10, which is a memory device having two banks 10 ₁ and 10 ₂ each having i × j × k bits of storage capacity. (10) is shown.

In FIG. 2, reference numeral C _i denotes the number of columns of memory, which is related to the number of horizontal pixels of the PDP image data, B _j denotes the number of input / output bits of the memory, and R _k denotes the number of rows of the memory. It is related to the number of vertical lines of data.

The memory device 10 of FIG. 2 divides and stores image data arranged in at least eight subfields inputted from the outside in each bank 10 ₁ and 10 ₂ for each subfield, and facilitates processing of PDP image data. In order to store one vertical line data in one row of the memory device 10, about 400 columns of VGA class and about 800 columns C _i of XGA class are required.

However, in the case of the general memory device 10, since the number of columns is fixed to, for example, 256, in consideration of the production process and generality, when used in a PDP device, one vertical line of image data is stored in one row of the memory device 10. Since it is difficult to store, conventionally, there is a problem in that image data of one vertical line is stored over two rows of the memory element 10, or a plurality of memory elements 10 are connected in parallel to compensate for the insufficient number of columns. there was.

In this case, when the image data of one vertical line is stored over two rows, a time delay occurs due to a row address change every time the image data is stored, and the clock frequency of the PDP device is increased, which causes an EMI (Electro Magnetic Interference) problem. It causes the occurrence.

In addition, when a plurality of memory elements 10 are connected in parallel, for example, in the case of VGA class, 64 Mbit RAM is used as a memory element for storing PDP image data, and the memory capacity used for storing actual image data is approximately Considering that it is about 16 Mbit, there is a waste of memory capacity due to the unused number of rows, which increases the production cost.

FIG. 5 is a block diagram illustrating an internal configuration of a general PDP apparatus, and a configuration in which the memory device 10 is connected to the PDP apparatus will be described with reference to FIG. 5.

As shown in FIG. 5, the PDP device includes a panel 51, a scan electrode driver 52, a sustain electrode driver 53, an address electrode driver 54, a controller 55, a data array IC 56, and a frame memory. It is configured with at least one memory element 10 used as.

In FIG. 5, the panel 51 includes scan electrodes Y _{1 to} Y _M , sustain electrodes X _{1 to} X _M , and address electrodes A _{1 to} A _N to emit light through the discharge cells S. Referring to FIG. This is for initially displaying an image, and the scan electrode driver 52 is for supplying a driving pulse to the scan electrodes Y _{1 to} Y _M.

The sustain electrode driver 53 is connected to the sustain electrodes X _{1 to} X _M through one common sustain electrode X 'to supply driving pulses, and the address electrode driver 54 is an address electrode. The driving unit 55 supplies driving pulses to A _{1 to} A _N , and the control unit 55 performs image data based on a clock CLK, a horizontal synchronization signal HS, and a vertical synchronization signal VS which are external input signals. To control the operation of the scan electrode driver 20, the sustain electrode driver 30, and the address electrode driver 40 to control the output.

The data array IC 56 rearranges the image data input according to the clock CLK, the horizontal synchronization signal HS, and the vertical synchronization signal VS, which are external input signals, for each subfield and temporarily stores the image data in the memory device 10. After storing, the data is converted into predetermined address data and supplied to the address electrode driver 54.

The data array IC 56 includes a memory device 10, a control bus C1 including a data bus line D1 shown in FIG. 5, a column address signal line, a row address signal line, and a memory control signal line. It transmits and receives image data and various control signals, and is connected to an interface circuit (not shown) for the transmission and reception operation. Therefore, in the case of the PDP device using the general memory element 10 as a frame memory, the occupying volume of the plurality of memory elements 10, the data array ICs 56, and the interface circuits thereof becomes significant.

Accordingly, the present invention was created in view of the above circumstances, and configures a memory cell to store input / output image data at an optimal cell capacity when the PDP device is driven, thereby preventing occurrence of unnecessary storage capacity of the memory. The purpose of the present invention is to provide a memory device for storing image data of a plasma display panel and a custom semiconductor using the same, which can reduce production costs and reduce the occupied volume of memory-related devices.

1A is a block diagram schematically illustrating an internal configuration of a general memory device.

FIG. 1B is a diagram schematically showing a cell configuration of the memory unit 11 shown in FIG. 1A.

2 is a diagram for explaining a method of storing PDP image data in a general memory device;

3A is a schematic diagram illustrating a cell configuration of a memory device according to the present invention.

3B is a view showing an example in which a memory element according to the present invention is composed of a plurality of banks.

4 is a view for explaining an application example of a memory device for storing PDP image data according to the present invention;

5 is a block diagram showing the internal structure of a general PDP device;

6 is a block diagram schematically illustrating an internal configuration of a custom semiconductor to which the memory devices of FIGS. 3A and 3B are applied.

*** Explanation of symbols for the main parts of the drawing ***

10, 30: memory element, 11: memory part,

12: column decoder, 13: row decoder,

14: input / output control unit, 10 ₁ , 10 ₂ , 30 ₁ ~ 30 _n : bank,

60: on demand semiconductor, 61: data array,

611: image data preprocessor, 612: timing signal generator,

613: address data generator, SF ₁ to SF _x : subfield,

53: data array IC.

A memory device for storing image data of a plasma display panel according to the present invention for achieving the above object is a memory element for storing image data of a plasma display panel having A horizontal pixels and B number of subfields, The device includes a column decoder for decoding a column address of a memory cell according to an external control signal; A row decoder for decoding a row address of a memory cell according to an external control signal; An input / output controller for controlling data input / output of the memory cell by a predetermined number of bits; Number of input / output bits connected to the column decoder, row decoder, and input / output controller, respectively, to store data at a designated column address and row address, and the number of columns of which is controlled by the input / output controller by the number of A × B bits. And a memory unit including a memory cell so as to correspond to a value divided by.

In addition, an on-demand semiconductor of a plasma display panel having a memory according to the present invention for achieving the above object is an on-demand with data array IC provided to process image data of a plasma display panel having A horizontal pixels and B subfields. In a semiconductor; At least one memory element for storing image data arranged and input into a plurality of subfields through the data array IC; The memory device includes a column decoder for decoding a column address of a memory cell according to an external control signal, a row decoder for decoding a row address of a memory cell according to an external control signal, and data input / output of the memory cell. Connected to the column decoder, the row decoder, and the input / output controller, respectively, to control data by the number of bits, and store data at a designated column address and a row address, and the number of columns corresponds to the A × B bit number. And a memory unit including a memory cell so as to correspond to a value divided by the number of input / output bits controlled by the output control unit.

Therefore, according to the above configuration, the production cost can be lowered by optimizing the capacity of the memory device for storing PDP image data for each resolution of the PDP device.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

First, a basic algorithm used when fabricating a memory device according to the present invention will be described.

According to the experiments of the applicant, the number of horizontal pixels, the number of subfields, the number of input / output bits and the number of columns of the memory device 10 and the number of columns of the PDP image data can be described by the relational equation 1, which is optimal considering the resolution of the PDP device. When the memory capacity and one vertical line of the PDP image data are stored in one row of the memory, the number of columns required can be calculated.

Relationship 1: Number of horizontal pixels × Number of subfields = Number of input / output bits × Number of columns (Unit: bits)

Therefore, according to Equation 1, in order to store the PDP image data having m horizontal pixels and n subfields in one row of the memory element, the cells 1 of each m × n bit per row of the memory element 10 ) Is required. When the number of bits of one vertical line of the PDP image data is divided by the number of input / output bits of the memory device, the optimal number of columns of the memory device is calculated according to the above equation 1.

FIG. 3A illustrates the structure of the memory device 30 according to the present invention. The memory device 30 of FIG. 3A has one row (for example, R ₁ of FIG. 3A) and a storage capacity of the PDP image data. 1 Increase the number of columns C _i to satisfy the number of vertical lines (columns (C _i ) x number of input / output bits (B _j )), and consider the total number of vertical lines of the PDP image data. Further included is an i × j × k of the cell (1) reducing the number of rows (R _k) of the cell area.

Therefore, the memory device 30 having the structure of FIG. 3A has m horizontal pixels and can store PDP image data having _X subfields SF ₁ to SF _X in one row of the memory device 30.

FIG. 3B illustrates an example in which a memory device according to the present invention is composed of a plurality of banks 30 ₁ to 30 _n , in which case, as in the memory device 30 of FIG. 3A, one row storage capacity of PDP image data is considered. To increase the total number of columns of the entire banks 30 ₁ to 30 _n and to reduce the number of rows in consideration of the total number of vertical lines of the PDP image data.

Each bank 30 ₁ to 30 _n of FIG. 3B basically stores all the subfields of the PDP image data at the same ratio and stores the number of subfields divided and stored in each bank 30 ₁ to 30 _n . It is also possible to set other ratios. Accordingly, as shown in FIG. 3B, when the memory device according to the present invention includes a plurality of banks 30 ₁ to 30 _n , the PDP image data may be stored in fewer banks than the general memory device 10.

Hereinafter, an application example of the memory device for storing PDP image data according to the present invention will be described with reference to FIG. 4.

First, the number of columns, the number of rows, and the storage capacity of the memory device 30 are set to be proportional to the exponent of 2 in consideration of compatibility so that they can be applied to PDP devices having various resolutions, and the number of subfields of PDP image data is based on 12 pieces. It was made. Application Examples 1 and 2 described below are for memory devices applied to VGA class PDP devices having a display resolution of 852 × 480, and Application Example 3 is for memory devices applied to XGA class PDP devices having 1365 × 768 pixels. will be.

[Application Example 1]

Application Example 1 relates to a memory device applied to a VGA class PDP device having 16 input / output bits, 852 horizontal pixels, and 480 vertical lines.

According to the relation 1, the number of columns required per subfield is The number of columns per subfield proportional to the exponent of 2 is 64. Therefore, the number of columns required for 12 subfields is 768, and the number of columns in 12 subfields proportional to the exponent of 2 is 1024. Therefore, a memory structure having 1024 columns in 16 bits of input / output bits stores one vertical line of PDP image data.

Since the number of rows for mapping the data of the total vertical lines is 480, the number of rows proportional to the exponent of 2 is 512, and the total number of actual required is required because the write / read of image data must be performed alternately. Since the memory capacity is doubled, the total memory capacity required is:

Total memory capacity = Number of input / output bits (16) x number of columns (1024) x number of rows (512) x 2

≒ 16 Mbit

In the case of Application Example 1, since the number of columns is 1024 and the number of rows is 512, horizontal resolution can be accommodated up to 1024, and vertical resolution can accommodate up to 512.

[Application Example 2]

Application Example 2 relates to a memory device applied to a VGA class PDP device having 32 input / output bits, 852 horizontal pixels, and 480 vertical lines.

According to the relation 1, the number of columns required per one subfield is The number of columns per subfield proportional to the exponent of 2 is 32. The number of columns required for the 12 subfields is 384, and the number of columns in the 12 subfields proportional to the exponent of 2 is 512. Therefore, a memory structure having 512 columns in 32 bits of input / output bits stores one vertical line of PDP image data. Since the number of rows is the same as that of Application Example 1, the total memory capacity required is as follows.

Total memory capacity = number of input / output bits (32) x number of columns (512) x number of rows (512) x 2

≒ 16 Mbit

In the case of Application Example 2, since the number of columns per subfield is 32 and the number of rows is 512, the horizontal resolution can be accommodated up to 1024 and the vertical resolution can be accommodated up to 512.

[Application Example 3]

Application Example 3 relates to a memory device applied to an XGA-class PDP device having 32 bits of input / output bits, 1365 horizontal pixels, and 768 vertical lines.

According to the relation 1, the number of columns required per one subfield is The number of columns per subfield proportional to the exponent of 2 is 64. Therefore, the number of columns required for 12 subfields is 768, and the number of columns in 12 subfields proportional to the exponent of 2 is 1024. Therefore, a memory structure having 1024 columns in 32 bits of input / output bits stores one vertical line of PDP image data. Since the number of rows for mapping the data of the total vertical lines is 768, and the number of rows proportional to the exponent of 2 is 1024, the total memory capacity required is as follows.

Total memory capacity = number of input / output bits (32) x number of columns (1024) x number of rows (1024) x 2

≒ 64 Mbit

In the case of Application Example 3, since the number of columns is 1024 and the number of rows is 1024, horizontal resolution can be accommodated up to 2048, and vertical resolution can accommodate up to 1024.

4 shows address ranges used in the memory devices of Application Examples 1 to 3 for each subfield.

Meanwhile, in the case of the application examples 1 to 3, as the number of columns is set according to a multiple of 2, up to 16 subfields may be stored in the memory device according to the present invention according to the actual driving method of the PDP apparatus. In addition, when the memory device includes a plurality of banks, it may be desirable to reduce the number of columns required through bank-by-bank control.

FIG. 6 is a block diagram schematically illustrating an internal configuration of an application-specific integrated circuit (ASIC) 60 to which the memory devices of FIGS. 3A and 3B are applied, which is a data array unit 61 and a plurality of memory devices. It is comprised with 30. In FIG. 6, the plurality of memory devices 30 may be configured as a single bank as shown in FIG. 3A, or may be configured as a plurality of banks as shown in FIG. 3B. The block M1 formed by the data array IC 56 and the plurality of memory elements 10 is formed by one chip.

The data array 61 is an external input signal is the clock (CLK), a horizontal synchronizing signal (HS) and vertical synchronizing signal (VS) the image data of one frame of the input from the external X sub-fields (SF ₁ in accordance with the ~ SF _X) to transmit to a sensitive (arrangement) of the plurality of memory elements (30) temporarily stored after, 5 an address electrode driver (54 of the address data of the next frame image data input during temporarily stored image data of the) For this purpose, it is composed of an image data preprocessor 611, a timing signal generator 612, and an address data generator 613.

The image data preprocessor 611 is for compensating and gamma-processing the input image data, and rearranging the input image data for each subfield. The timing signal generator 612 is the image data preprocessor 611 and address data. It is for generating a predetermined control signal (for example, an enable signal) for driving the generator 613. The address data generator 613 is used to rearrange the address data of the image data rearranged and stored in each memory element 30. This is for generating and applying to the address electrode driver 54.

According to the configuration of FIG. 6, the data arranging unit 61 performs pre-arrangement of the PDP image data of X subfields SF according to the clock CLK, the horizontal synchronization signal HS, and the vertical synchronization signal VS which are external input signals. ₁ to SF _X ), the least significant bit (LSB) to the most significant bit (MSB) are arranged in pixels and stored in the memory device 30, respectively, and address data of rearranged image data is generated by one vertical line. 54).

At this time, the address data generated from the address electrode driver 54 is sequentially output from the least significant bit LSB to the most significant bit MSB of the image data.

Hereinafter, a practical application example of the application specific semiconductor 60 of FIG. 5 will be described.

In this application example, the on-demand semiconductor 60 is applied to a so-called dual scan mode PDP device in which a scan operation of a display image is divided into two areas (for example, 1 to 240 lines and 241 to 480 lines) of the PDP panel. In this application example, the resolution of the PDP device is 852 × 480 (VGA) and the memory capacity of the independent memory device 30 is 4 Mbit. It is based on.

The following Table 1 shows the number and specifications (columns, rows) of memory devices 30 required for the application-specific semiconductor 60 when the number of input / output bits of the memory device 30 according to the above criteria is 32 bits. .

Number of banks of memory elements Number of columns Low number Number of memory elements One 512 256 4 2 256 256 4 4 128 256 4 8 64 256 4

And the following Table 2 shows the number and specifications (columns, rows) of memory devices 30 required for the application-specific semiconductor 60 when the number of input / output bits of the memory device 30 according to the criteria is 16 bits. will be.

Number of banks of memory elements Number of columns Low number Number of memory elements One 1024 256 4 2 512 256 4 4 256 256 4

Each of the four independent memory elements 30 required in Tables 1 and 2 is for writing an upper region, reading an upper region, writing a lower region, and lowering according to the division of the PDP panel and the division of data writing / reading, respectively. It is configured for area reading.

As described above, according to the above-described embodiment, the number of columns is increased so that one row storage capacity of the memory element storing the PDP image data satisfies the number of bits of one vertical line of the PDP image data, and is suitable for the total number of vertical lines. By reducing the number of rows, unnecessary waste of memory capacity can be prevented.

In addition, by adjusting the number of columns and rows of the memory device to the maximum resolution of the PDP image data, it is possible to easily support various resolutions supported by the PDP device while reducing unnecessary storage capacity of the memory device. EMI can be avoided by storing data across two rows of the same memory device.

In addition, as shown in FIG. 5, a plurality of memory devices 30 are installed inside the application-specific semiconductor 60, and the data array unit 61 and the internal conductors are connected to each other to separate data array ICs and memories for controlling the memory devices as in the related art. Since no interface between elements is required, the occupied volume occupied by memory elements in a conventional PDP device can be greatly reduced, and the performance of the PDP device can be further stabilized.

As described above, according to the present invention, by storing the image data for the PDP with the optimal storage capacity, the storage capacity of the memory can be reduced, thereby reducing the production cost of the PDP device for image data storage of the plasma display panel It is possible to provide a memory device.

In addition, when the memory device according to the present invention is applied to a custom semiconductor in a PDP device, the performance of the PDP device can be more stabilized and the occupied volume of the memory device in the device can be reduced.

Claims (11)

A memory device for storing image data of a plasma display panel having A horizontal pixels and B subfields, The memory device may include a column decoder for decoding a column address of a memory cell according to an external control signal. A row decoder for decoding a row address of a memory cell according to an external control signal; An input / output controller for controlling data input / output of the memory cell by a predetermined number of bits; Number of input / output bits connected to the column decoder, row decoder, and input / output controller, respectively, to store data at a designated column address and row address, and the number of columns of which is controlled by the input / output controller by the number of A × B bits. And a memory unit including a memory cell so as to correspond to a value divided by. The method of claim 1, And the memory unit comprises memory cells such that the number of columns, the number of rows, and the storage capacity are proportional to the exponent of two. The method of claim 2, In the case of a PDP device having 16 input / output bits, at least 852 horizontal pixels, and at least 480 vertical lines, the memory cells of the memory unit have at least 1024 columns and at least 512 rows. And a memory device for storing image data of the plasma display panel. The method of claim 2, In the case of a PDP device having 32 bits of input / output bits, at least 852 horizontal pixels, and at least 480 vertical lines, the number of columns and rows formed by the memory cells of the memory unit is configured to be at least 512 or more, respectively. A memory element for storing image data of a plasma display panel. The method of claim 2, In the case of a PDP device having 32 bits of input / output bits, at least 1365 horizontal pixels and at least 768 vertical lines, the number of columns and rows formed by the memory cells of the memory unit is configured to be at least 1024 or more, respectively. A memory element for storing image data of a plasma display panel. The method of claim 1, And the memory device comprises a plurality of banks, the number of columns allocated to each bank being distributed at an equal ratio. In a custom semiconductor provided with data arranging means for processing image data of a plasma display panel having A horizontal pixels and B subfields, At least one memory element for storing image data arranged and input into a plurality of subfields through the data arranging means, The memory device may include a column decoder for decoding a column address of a memory cell according to an external control signal. A row decoder for decoding a row address of a memory cell according to an external control signal; An input / output controller for controlling data input / output of the memory cell by a predetermined number of bits; Number of input / output bits connected to the column decoder, row decoder, and input / output controller, respectively, to store data at a designated column address and row address, and the number of columns of which is controlled by the input / output controller by the number of A × B bits. And a memory unit including a memory cell so as to correspond to a value divided by. The method of claim 7, wherein And the memory unit includes memory cells such that the number of columns, the number of rows, and the storage capacity are proportional to the exponent of two. The method of claim 8, When the memory device is applied to a dual scan mode PDP device, the memory device includes four independent modules for writing the upper region, reading the upper region, reading the lower region, and reading the lower region. An on-demand semiconductor of a plasma display panel having a memory. The method according to claim 7 or 9, The data arranging means includes an image data preprocessor for gamma processing the input image data and rearranging the image data by subfields; An address data generator for generating address data of the image data rearranged and stored in the memory device; And a timing signal generator for generating a predetermined control signal for driving the image data preprocessor and the address data generator. The method according to claim 7 or 9, And the memory device comprises a plurality of banks, and the number of columns allocated to each bank is distributed at an equal ratio.